CN103094352A

CN103094352A - Thin film transistor, manufacturing method therefor, and display apparatus having thin film transistor, sputtering target material

Info

Publication number: CN103094352A
Application number: CN2012104409795A
Authority: CN
Inventors: 浅沼春彦; 楠敏明; 外木达也; 辰巳宪之
Original assignee: Hitachi Cable Ltd
Current assignee: SH Copper Products Co Ltd
Priority date: 2011-11-02
Filing date: 2012-11-02
Publication date: 2013-05-08
Anticipated expiration: 2032-11-02
Also published as: CN103094352B; JP6335226B2; JP2013118367A; JP2016197743A; KR20130048703A

Abstract

On condition that Cu alloy is used in wiring of a thin film transistor (TFT), TFT movability reduction occurs when oxidation treatment is performed on a semiconductor layer which is composed of silicon film. Additionally, when Cu alloy contacts with a semiconductor layer which is composed of oxide semiconductor film for heating, subthreshold coefficient increase, negative offset of threshold voltage and normal conduction operation of TFT occur. The present invention provides a thin film transistor which is provided with the following components on a substrate: a grid insulating film, a Si-series semiconductor layer, source/drain electrodes with a Cu alloy layer, and an oxide film which is formed on an interface between the source/drain electrodes and the Si-series semiconductor layer. The thin film transistor is characterized in that: the Cu alloy layer comprises Cu and at least one added element; the depth distribution peak of the oxygen atom concentration in the oxide film is between 40atom% and 60atom%; and furthermore, when the distance of 10atom% to the oxygen atom concentration peak or the oxygen distribution of the interface between the source/drain electrodes and the Si-series semiconductor layer is defined to film thickness of the oxide film, the film thickness of the oxide film is less than 1.8nm.

Description

Thin-film transistor and manufacture method thereof and the display unit, the sputtering target material that possess thin-film transistor

Technical field

The display unit, the sputtering target material that the present invention relates to thin-film transistor and manufacture method thereof and used the active array type of thin-film transistor.

Background technology

In recent years, thin-film transistor (TFT:Thin Film Transistor) is being used for the active matrix type display of image element circuit, the raising of the animation performance that require that it maximizes, the multiplication of the high-precision refinement of pixel, frame rate causes also requires the people's livelihood with the image quality raising of 3D display unit etc.On the other hand, the price of display unit continues to descend with the speed of super expection, and the main cause that the prices such as energy resources and rare metal are surging etc. raises manufacturing cost also continues to increase.Therefore, the task of top priority is the technology that exploitation is used for further reducing manufacturing cost.

For satisfying above-mentioned requirements, for example in liquid crystal indicator (LCD:Liquid CrystalDisplays), there is the semiconductor layer of attempting TFT to replace with microcrystal silicon and polysilicon or oxide semiconductor by amorphous silicon film, in addition, its wiring material is replaced with copper (Cu) by aluminium (Al) or Al alloy.Microcrystal silicon and polysilicon or oxide semiconductor and amorphous silicon relatively have high charge carrier degree of excursion, therefore, can the decrease driving voltage, can realize pixel high-precision refinement, reduce power consumption, in addition, can form drive circuit at the periphery of display unit.

The Cu distribution is lower than the resistance of Al distribution, therefore, can suppress to conduct the propagation delay phenomenon of the signal of telecommunication sluggishness of distribution, can realize the raising of the animation quality that the increase of the in more large-scale and frame rate of display unit brings.In addition, the Al distribution is made the stacked film structure with the Mo/Al/Mo that uses up and down molybdenum (Mo) clamping at high price of Al film usually in order to ensure the generation inhibition of hillock and the electrical connection of nesa coating, but, Cu can carry out being connected with the direct of nesa coating, therefore, can realize saving molybdenum.Therefore, can reduce manufacturing cost.

In addition, for maximization and the image quality raising of organic EL display, except the semiconductor layer of using high degree of excursion, seek the low low wiring material of resistance ratio Al distribution.The driving transistors of being located at the image element circuit of organic EL display uses the zone of saturation to be controlled at the electric current that organic EL layer flows, adjust its brightness, but, can not ignore the affecting of voltage drop that wiring resistance causes along with the maximization of display unit the time, the voltage of imagination can not be supplied with driving transistors and can not carry out driving in the zone of saturation, its result becomes the reason of brightness disproportionation.So, studied the application of the Cu distribution that is used for the display quality raising.

But, when using the Cu distribution in TFT, have following problem.The adaptation of Cu and glass substrate, semiconductor layer is poor.In addition, in the situation that Cu and semiconductor layer join, due to the heat that applies in the manufacturing process after distribution forms, Cu makes the TFT deterioration in characteristics to the semiconductor layer diffusion inside, and display quality is descended.As reply such adaptation and diffusion barrier impenetrability problem, the method that forms Mo, Mo alloy between counterdie and Cu film is arranged.But, be high price as aforementioned Mo, in addition, the stepped construction of the metal that electrochemical properties is different is difficult to carry out etching, and therefore, manufacturing cost increases.

So motion utilizes thermal technology's order, adopt the interpolation element of oneself is separated out at the interface method of the Cu alloy of the interpolation element oxide film of formation adaptation and diffusion barrier impenetrability excellence.At this, the alignment films sintering circuit of thermal technology's order imagination CVD (Chemical Vapor Deposition) operation liquid crystal indicator, be used for the annealing in process etc. of the curing of oxide semiconductor film, form the temperature of rear film transistor base experience at distribution.In adding own formation of element oxide film, need to be pre-existing in the sufficient oxygen atom of necessity at the interface of Cu alloy and the film that joins with it.

In following patent documentation 1, recommend the CuMn alloy, as use the method for Cu alloy in (SD:Source Drain) electrode is leaked in the source of TFT, motion has for example carries out oxygen plasma treatment before the film forming of Cu alloy, make silicon fiml upper strata modification, the temporary transient silicon oxide layer SiOx that forms gives necessary oxygen in the formation of adding the element oxide film.

In addition, in following patent documentation 2, disclose the method that the Cu alloy is used to oxide semiconductor.Oxide semiconductor film contains the oxygen that is necessary in advance in the own formation of adding the element oxide film.

The prior art document

Patent documentation

Patent documentation 1: JP 2008-282887 communique

Patent documentation 2: JP 2011-91364 communique

Summary of the invention

The problem that invention will solve

But, as patent documentation 1, in the situation that use the Cu alloy in distribution, when the semiconductor layer that is made of silicon fiml is utilized the oxidation processes of oxygen plasma, the damage of oxygen plasma treatment of resulting from is imported into the semiconductor layer that is made of silicon fiml, have that the degree of excursion that produces TFT reduces etc. problem.

In addition, as patent documentation 2, in the situation that use the Cu alloy in distribution, make the Cu alloy contact with the semiconductor layer that is consisted of by oxide semiconductor film, when heating, the increase, threshold voltage of subthreshold value coefficient occuring to the displacement of negative direction, exists TFT to become the problems such as normal ON Action.

The object of the invention is to, suppress the reduction of the electrical characteristics value of the TFT of use Cu alloy in distribution.

Be used for solving the means of problem

according to a viewpoint of the present invention, thin-film transistor is provided, it possesses in order from substrate-side on substrate: gate insulating film, Si based semiconductor layer, source/drain electrode with Cu alloy-layer, oxidation film at the interface formation of described source electrode and drain electrode and described Si based semiconductor layer, it is characterized in that, described Cu alloy-layer contains Cu and at least a interpolation element, the peak value of the depth distribution of the atomic concentration of the oxygen in described oxidation film is more than 40 atom % and below 66 atom %, and, will apart from the peak value of the atomic concentration of described oxygen or when being the thickness of described oxidation film apart from the distance definition that the distribution of the oxygen at the interface of described source electrode and drain electrode and described Si based semiconductor layer becomes 10 atom %, the thickness of described oxidation film is below 1.8nm.

At this, be formed at described Si based semiconductor layer, have the described oxidation film at interface, the back side of the source/drain electrode of described Cu alloy-layer, its adaptation and diffusion barrier impenetrability are excellent, and, be by the film formed own formation film of low-resistance oxidation film silica.At this moment, the oxide-film as thin as a wafer that gate insulating film is just being gone up oneself forms the oxidation film of adaptation and diffusion barrier impenetrability excellence too, therefore, is difficult to cause that the film of source electrode and drain electrode peels off.In addition, instruction suppresses the Cu atom to the diffusion of Si semiconductor layer, and playing a role as dead resistance at the near interface of source electrode and drain electrode and Si semiconductor layer does not have silicon oxide film (not observing the reduction of degree of excursion, i.e. the reduction of making current).

In addition, also can will apart from peak value or when being the silica thickness apart from the distance definition that the distribution of the interface oxygen of Cu alloy-layer and Si semiconductor layer becomes 15 atom %, its thickness is below 1.6nm, will apart from peak value or when being the silica thickness apart from the distance definition that the interface oxygen distribution of Cu alloy-layer and Si semiconductor layer becomes 20 atom %, its thickness is below 1.4nm, will apart from peak value or when being the thickness of silicon oxide film apart from the distance definition that the distribution of the interface oxygen of Cu alloy-layer and Si semiconductor layer becomes 25 atom %, its thickness is below 1.2nm.

In addition, preferably at the interface of described source electrode and drain electrode and described Si based semiconductor layer, the constituent material of described source electrode and drain electrode is every average below 7 apart from 480nm to the line density at the position of described Si based semiconductor layer diffusion.

In other words, as long as the constituent material of described source electrode and drain electrode is 7 * 7/480 * 480nm to the surface density at the position of described Si semiconductor layer diffusion ²Below (212.6/μ m ²Below), just can guarantee adaptation.

According to other viewpoint of the present invention, the manufacture method of thin-film transistor is provided, thin-film transistor possesses in order from substrate-side on substrate: gate insulating film, Si based semiconductor layer, have the source/drain electrode of the cu alloy-layer that contains Cu and at least a interpolation element, at the oxidation film of the interface formation of described source electrode and drain electrode and described Si based semiconductor layer, it is characterized in that, form gate electrode structure on described substrate, on piled up gate insulating film after, have: the step of piling up described Si based semiconductor film on described gate insulating film; Form the step of oxide-film as thin as a wafer by the plasma oxidation method on the surface of described Si based semiconductor layer; And the step that forms the source/drain electrode with described Cu alloy-layer, described oxidation film forms by the plasma oxidation method, and the RF power density in described plasma oxidation method is 0.22～0.67W/cm ²Below, and the processing time is more than 60 seconds and below 240 seconds.

In addition, the manufacture method of thin-film transistor is provided, it possesses in order from substrate-side on substrate: gate insulating film, Si based semiconductor layer, have the source/drain electrode of the Cu alloy-layer that contains Cu and at least a interpolation element and at the oxidation film of the interface formation of described source electrode and drain electrode and described Si based semiconductor layer, it is characterized in that, form gate electrode structure on described substrate, on piled up gate insulating film after, have: the step of piling up described Si based semiconductor film on described gate insulating film; Form the step of oxide-film as thin as a wafer by the plasma oxidation method on the surface of described Si based semiconductor layer; And the step that forms the source/drain electrode with described Cu alloy-layer, described oxidation film forms by the plasma oxidation method, and the long-pending value in the RF power density in described plasma oxidation method and described processing time is 26.4～52.8Wsec/cm ²

In addition; the invention provides thin-film transistor; it possesses in order from substrate-side on substrate: have oxidation film gate insulating film, oxide semiconductor layer, have the source/drain electrode of the Cu alloy-layer that contains Cu and at least a interpolation element, at oxidation film and the whole diaphragm of protection of the interface formation of described source electrode and drain electrode and described oxide semiconductor layer; it is characterized in that; in described oxidation film; interpolation element in described source electrode and drain electrode and the atomic concentration of oxygen have the peak, and the peak value that the peakedness ratio of oxygen adds element is large.

In the formation temperature of described diaphragm; be arranged in described source electrode and drain electrode lower floor described Cu the Cu atom and add element and separate out at the interface; with the dielectric film chemical combination that forms in advance, suppress the diffusion from the oxygen of described oxide semiconductor layer on described oxide semiconductor layer.Namely, before Cu alloy film forming, oxide semiconductor film is implemented oxidation processes, its surface temporarily is modified as insulator, thus, even add Elements Diffusion at film forming Cu alloy, in following the processing of heat, form and add the element oxide film, also there is necessary sufficient oxygen at the interface of Cu alloy and oxide semiconductor film, therefore, can not produce the diffusion from the oxygen in the deep of oxide semiconductor film.In addition, the peak value that the peakedness ratio of the atomic concentration of oxygen adds element is large, and therefore, the characteristic of the Current rise of TFT is good, can carry out described Cu alloy and use to the distribution of oxide semiconductor TFT.

In addition, oxidation is closed, oneself form low-resistance oxidation film, and thus, the adaptation of described source electrode and drain electrode and described oxide semiconductor layer and diffusion barrier impenetrability are good.Therefore, according to the said film transistor, can suppress the diffusion from the oxygen of oxide semiconductor layer, can carry out described Cu alloy and use to the distribution of oxide semiconductor TFT.

In addition, even also oneself form the oxidation film of adaptation and diffusion barrier impenetrability excellence on the described oxide-film as thin as a wafer that gate insulating film is just being gone up, therefore, the film that is difficult to produce source electrode and drain electrode is peeled off.

In addition, in above-mentioned, it is characterized in that, the equilibrium oxygen electromotive force of the oxide reaction of formation of the interpolation element in described source electrode and drain electrode is less than the equilibrium oxygen electromotive force of at least one element that consists of described oxide semiconductor layer.

The part of described diaphragm also can be made of silicon nitride film.

Formed at least a portion of diaphragm by silicon nitride film; thus, sometimes produce hydrogen to the diffusion of oxide semiconductor layer, cause the reduction of electrical characteristics, still; the dielectric film on the upper strata of oxide semiconductor layer suppresses this reduction is prevented that hydrogen is to the diffusion of oxide semiconductor film.

according to other viewpoint of the present invention, the manufacture method of thin-film transistor is provided, thin-film transistor possesses in order from substrate-side on substrate: the gate insulating film with oxidation film, oxide semiconductor layer, source/drain electrode with the Cu alloy-layer that contains Cu and at least a interpolation element, oxidation film at the interface formation of described source electrode and drain electrode and described oxide semiconductor layer, the diaphragm that protection is whole, it is characterized in that, in the step that forms described diaphragm, impose a condition for: in described oxidation film, interpolation element in described source electrode and drain electrode and the atomic concentration of oxygen have the peak, the peak value that the peakedness ratio of oxygen adds element is large.

In the formation temperature of described diaphragm; be arranged in described source electrode and drain electrode lower floor described Cu the Cu atom and add element and separate out at the interface; with the dielectric film chemical combination that forms in advance, suppress the diffusion from the oxygen of described oxide semiconductor layer on described oxide semiconductor layer.Namely, before Cu alloy film forming, oxide semiconductor film is implemented oxidation processes, its surface temporarily is modified as insulator, thus, even add Elements Diffusion forms and adds the element oxide film at film forming Cu alloy, in following the processing of heat, also there is necessary sufficient oxygen at the interface of Cu alloy and oxide semiconductor film, therefore, do not produce the diffusion from the oxygen in the deep of oxide semiconductor film.

In addition, the present invention can be also the display unit of having used the described thin-film transistor of any one in above-mentioned.

The effect of invention

According to TFT of the present invention, can not produce TFT the electrical characteristics value reduction realize that the distribution of Cu alloy uses.

Description of drawings

Fig. 1 is the main cause design sketch about degree of excursion.

Fig. 2 means the figure of the long-pending correspondence in standardization degree of excursion and RF power density processing time.

Fig. 3 is analyzed and the figure of clear and definite Elemental Composition cloth by TEM-EELS.

Fig. 4 means the figure of depth distribution of oxygen of the Si semiconductor side of the No.4 of table 1 and No.13.

Fig. 5 means the figure of result of EELS spectrum analysis of the oxygen of the No.4 of table 1 and No.13.

Fig. 6 A means the figure of the appearance that the interface of TEM is observed.

Fig. 6 B means the figure of the appearance that the interface of TEM is observed.

Fig. 6 C means the figure of the appearance that the interface of TEM is observed.

Fig. 6 D means the figure of the appearance that the interface of TEM is observed.

Fig. 7 means the oxygen of oxide semiconductor TFT and the figure of the distribution of the atomic concentration of adding element.

Fig. 8 means the profile of manufacturing process of the thin-film transistor of embodiment 1.

Fig. 9 means No.4, No.13, and the figure of the transmission characteristic of the TFT of prior art of table 1.

Figure 10 means the profile of manufacturing process of the thin-film transistor of embodiment 2.

Figure 11 means the figure of transmission characteristic of the TFT of embodiment 2 and prior art.

Figure 12 means the figure of pixel configuration example of thin film transistor base plate of the liquid crystal indicator of embodiment 3.

Figure 13 means the profile of configuration example of the liquid crystal indicator of embodiment 3.

Symbol description:

1: substrate

The 2:Cu alloy

3: pure Cu

4: gate electrode

5: gate insulating film

6: the active semiconductor layer

6a: dielectric film

7: contact membranes

7a: oxide-film as thin as a wafer

8: semiconductor layer (67)

The 9:Cu alloy

10: pure Cu

11: the source electrode

12: drain electrode

13: diaphragm

14: oxidation film (at the interface formation of SD electrode 1112 and semiconductor layer 8 (6.7))

15: oxidation film (at the interface formation of SD electrode 1112 and gate insulating film 5)

100: liquid crystal indicator

The 101:TFT substrate

102: scan line

103: holding wire

104：TFT

105: pixel electrode

106: energy storage capacitor

111: light source

112: polarizer

113: dielectric film

114: alignment films

115: liquid crystal layer

116: pad

117: common electrode

118: colour filter

119: black matrix

120: filter substrate

121: polarizing coating

Embodiment

Below, be elaborated to the manufacture method of the TFT of embodiment of the present invention and structure and with this technology that is applicable in the situation of display unit with reference to accompanying drawing.

At first, before explaining embodiment, in the TFT that has used the Cu alloy in distribution, produce reason and its improvement method that the electrical characteristics value reduces, be mainly the situation of silicon fiml and the situation analysis of oxide semiconductor film describes with semiconductor layer.The example of structure describes in embodiment 1.

＜semiconductor layer is the situation of silicon fiml 〉

Semiconductor layer is silicon fiml, in the situation that use the Cu alloy in the SD electrode wiring, silicon fiml is due to insufficient oxygen that oneself forms the necessity of adding the element oxide film that contains, before the film forming of Cu alloy, carry out in advance oxidation processes, make silicon fiml upper strata (top layer) modification, temporarily form silicon oxide film (SiO _x).Make TFT by the method identical with the method for patent documentation 1 record, estimate electrical characteristics, still, its degree of excursion significantly reduces than the TFT of the Mo that has used existing distribution.The reduction of this degree of excursion causes the reduction of making current, has the problem of the rising that causes driving voltage.

So, due to the main cause that determines that this degree of excursion reduces, make the L9 orthogonal arrage by 3 controlling elements of " intensity of oxidation processes ", " interpolation amount of element ", " thickness of Cu alloy ", investigated the main cause that degree of excursion reduces.The intensity of oxidation processes is adjusted with the RF power density of oxygen plasma treatment, has used manganese (Mn) as the interpolation element in Cu.Each standard is that the RF power density is 0.22,0.44,0.89W/cm ², the Mn concentration in the Cu alloy is made as 2,4,10 atom %, and the thickness of Cu alloy is made as 17,33,50nm.

It is that 10 μ m and channel width (W) are 100 μ m that the element of estimating is of a size of channel length (L), and degree of excursion is calculated for the zone of saturation of 10V by source-drain electrode voltage (Vds).The reason of selecting this component size is that in addition, channel length L is 1～100 μ m, can observe clearly the impact of dead resistance because in fact approach with the size that is applied to display unit.

In addition, degree of excursion carries out standardization with the value of the degree of excursion of the TFT of the Mo that has used existing distribution, will be made as 1.0 with the situation of value.

Fig. 1 is the main cause design sketch of degree of excursion.Its result distinguishes, (A1～A3, B1～B3, C1～C3), the standardization degree of excursion is the main cause that the earth changes according to different parameters, namely, the intensity of oxidation processes is the main cause that degree of excursion reduces, that is, the depth distribution of the oxygen in silicon fiml is important.

Therefore, the correspondence of the degree of excursion of the investigation depth distribution of oxygen and TFT has been obtained the depth distribution that does not produce the suitableeest oxygen that degree of excursion reduces.Adjust RF power density and the processing time of oxygen plasma treatment, adjusted the depth distribution of oxygen.The detailed manufacture method of TFT describes on the hurdle of following embodiment 1.Due to reason same as described above, it is that 10 μ m and channel width (W) are 100 μ m that the evaluation element is of a size of channel length (L).In addition, the degree of excursion of having used the TFT of Cu alloy distribution carries out standardization with the degree of excursion value of the TFT of the Mo that used existing distribution, will be made as 1.0 with the situation of value.In addition, as the index of the intensity that represents oxidation processes, determine that RF power density and processing time are long-pending, ask for the correspondence of its value and standardization degree of excursion.In addition, compare with the degree of excursion of the TFT of the Mo that has used existing distribution, with large situation be judged to be zero, will be roughly equal situation is judged to be △, can find out the situation that clearly reduces (deteriorated) be judged to be *.These results of table 1 expression.

Table 1

Observe table 1, degree of excursion mainly exists with ... the RF power density consumingly as can be known, and larger its of RF power density more reduces.Infer this be because, along with the increase of RF power density, the oxidation kind squeeze into grow, oxygen atom is directed to the degree of depth of Si semiconductor film, its result is not closed with adding the element oxide membranization, and is become dead resistance at the remaining silicon oxide film of semiconductor layer side.In addition, as can be known, be 0.44W/cm in the RF of No.5 power density ², the processing time is when being 120 seconds, degree of excursion begins to reduce than the TFT of existing distribution.

Therefore, for example, smaller in membranous deviation take the weakness reason time, as not produce the suitableeest oxygen that degree of excursion reduces depth distribution in the RF of No.4 power density as 0.44W/cm ², realize when the processing time is 60 seconds.Even the RF power density of No.7 is 0.67W/cm ², the processing time is 60 seconds, can obtain the degree of excursion than existing distribution excellence, still, the processing time that can find out No.8 is the clear and definite reduction of degree of excursion of 120 seconds, therefore, considers to wish to be No.4 when operation is affluent.

Fig. 2 means the standardization degree of excursion of table 1 and the figure of the long-pending correspondence in RF power density processing time.As shown in Figure 2, can find out that the standardization degree of excursion exists with ... the long-pending value in RF power density and processing time.And the long-pending value in RF power density and processing time is 52.8Wsec/cm as can be known ²When following, can obtain and the equal above degree of excursion of existing distribution.As can be known: when considering deviation, be preferably 60Wsec/cm ²Below, if be 50Wsec/cm ², more preferably.

Therefore, then relatively investigate the depth distribution of oxygen and the bonding state of chemistry thereof by transmission electron microscope electron energy loss optical spectroscopy (TEM-EELS:Transmission Electron Microscopy and ElectronEnergy Loss Spectroscopy).The sample that uses relatively for reference, has also represented that the Cu atom is diffused into the sample of the degree of depth of Si semiconductor film as No.1, No.4, the No.13 of table 1 in the lump.At first, Fig. 3 represents to analyze clear and definite Elemental Composition cloth ((a) has the Cu diffusion) by TEM-EELS.

At this, the phosphorus (P) that imports for the ohmic contact that obtains Cu alloy-layer and Si semiconductor layer can not detect in EELS analyzes, therefore, use energy dispersion type x-ray analysis method (EDX:Energy Dispersive X-ray spectroscopy), expression in the lump in the EELS analysis result.

As shown in Fig. 3 (a), be diffused in the sample of profound layer of Si semiconductor film at the Cu atom, the peak value of oxygen atom is low to moderate about 30 atom %, and No.1, the No.4 of the table 1 in the position of the diffusion of the Cu atom shown in inhibition Fig. 3 (b), (c), (d), the peak value of No.13 sample are more than 40 atom %.In the No.13 of the table 1 of Fig. 3 (d), electrical characteristics are obviously deteriorated.In the No.4 of the No.1 of the table 1 of Fig. 3 (b), Fig. 3 (c), table 1, electrical characteristics are good, in addition, are 40 atom %, 58% at the interface of Si semiconductor film oxygen atom, in these oxygen concentrations, can obtain good value.

Therefore, in order to suppress the Cu atom to the diffusion of Si semiconductor layer, need to be more than 40 atom % and below 66 atom % at the interface oxygen atom of Cu alloy-layer and Si semiconductor film.In addition, 66 atom % can not give the value that the form of the silicon dioxide film (SiO2) of oxygen gets after thus.

Below, consider from the viewpoint of degree of excursion, relatively the bonding state of the depth distribution of the oxygen of Si semiconductor layer side and chemistry thereof.Fig. 4 represent to have excellent degree of excursion table 1 No.4 and observe the figure of depth distribution of oxygen of Si semiconductor side of No.13 of the reduction of degree of excursion.

As shown in Figure 4, the peak value of oxygen is present in the roughly interface of Cu alloy and Si semiconductor layer, and therefore, the transverse axis of figure is made as from the peak position to the distance of Si semiconductor layer side.The depth distribution of the oxygen of the low sample to 0.62 No.13 of standardization degree of excursion is compared with existing distribution as shown in Figure 4 until the high No.4 of degree of excursion more obvious dark position (1～3nm left and right) shows high value.Therefore, supposition described above is such, as can be known more than the interface of Si semiconductor film oxygen atom enters 40 atom % and the main cause that reduces of the degree of excursion in the No.13 of the scope below 66 atom % be because become dead resistance at the remaining silicon oxide film of Si semiconductor layer side.At this, Fig. 4 outbound course generation by background for the oxygen of severals atom % of detecting in the deep of Si semiconductor layer (more than 3.0nm) think result.On this basis, when regulation does not produce the depth distribution degree of the oxygen that degree of excursion reduces, in the situation that will or be the silica thickness apart from the distance definition that the distribution of the oxygen at the interface of Cu alloy-layer and Si semiconductor layer becomes 10 atom % apart from peak value, its thickness can be set as below 1.8nm.In addition, in the situation that will or be the silica thickness apart from the distance definition that is distributed as 15 atom % of the oxygen at the interface of Cu alloy-layer and Si semiconductor layer apart from peak value, its thickness is below 1.6nm, in the situation that will or be the silica thickness apart from the distance definition that is distributed as 20 atom % of the oxygen at the interface of Cu alloy-layer and Si semiconductor layer apart from peak value, its thickness is below 1.4nm, in the situation that will or be the silica thickness apart from the distance definition that is distributed as 25 atom % of the oxygen at the interface of Cu alloy-layer and Si semiconductor layer apart from peak value, its thickness be below 1.2nm.

And, also carried out the comparison of No.4 (Fig. 5 (a)) and the No.13 (Fig. 5 (b)) of table 1 from the chemical binding state of oxygen.Fig. 5 means the figure of result of the EELS spectrum analysis of silicon, and transverse axis is energy loss, and the longitudinal axis is absorption intensity.The spot definition of beam is 0.7nm φ.In the sample of No.4, instruction silicon oxide film (SiO _x) energy loss 110eV near the peak only at the periphery of the peak value of the depth distribution of oxygen, be a little less than the interface (C) of Cu alloy-layer and Si semiconductor layer is seen, but, in the sample of No.13, even also clearly observe (C, and D) from the position of 1nm at the interface of distance Cu alloy-layer and Si semiconductor layer.Hence one can see that, and the main cause that degree of excursion reduces is at the remaining silicon oxide film of Si semiconductor layer side.

Fig. 6 A～Fig. 6 D means the figure with the result at the interface of the element of tem observation table 1.Observed element be from Fig. 6 A towards Fig. 6 D, 4 elements of the No.1 of table 1, No.3, No.4, No.13.

In element No.1, no problem for the value (reduction of value) of degree of excursion, still, the peeling off of film of Cu distribution occured in several months afterwards after making element.Fig. 6 A (a) is that 200000 times, Fig. 6 A (b) are the multiplying power of 500000 times.Below, Fig. 6 B～Fig. 6 D is too.

As shown in Figure 6A, when the line density that spreads number (diffusion part figure place) in the element of N0.1 is 12/480nm, more than other element.Like this, in the situation that diffusion part is many, the stress that produces from diffusion part increases, and film occurs peel off, and therefore, is difficult to use as goods.Therefore, in order to reach guaranteeing of long-term adaptation more than several months, need to make the number at diffusion position as much as possible little.In 14 elements except No.1 of table 1, do not cause that all film peels off.Therefore, for guaranteeing adaptation, the long-pending value in RF power density and processing time need to be set as 26.4Wsec/cm as can be known ²Above.In addition, according to the result of Fig. 6 B, Fig. 6 C as can be known, for guaranteeing adaptation, following as long as the line density of diffusion number is 7/480nm.In addition, so-called Cu alloy-layer and semiconductor layer, the membranous anisotropy that there is no two dimension, therefore, when using the surface density of diffusion number, as long as be 7 * 7/480 * 480nm ²Below, just can guarantee adaptation.In the No.13 of Fig. 6 D element, spreading the position is 0, still, can see as described above the obvious reduction of degree of excursion, therefore, can not be used for goods.

by above result, according to present embodiment, semiconductor layer is mainly silicon fiml, the depth distribution of the atomic concentration of the oxygen in oxidation film is is more than 40 atom % and below 66 atom % at peak value, and, in the time will being the silica thickness apart from the peak value of the atomic concentration of oxygen or apart from the distance definition that is distributed as 10 atom % of the oxygen at the interface of above-mentioned source electrode and drain electrode and above-mentioned semiconductor layer, above-mentioned silica thickness is below 1.8nm, in the situation that will be the silica thickness apart from the distance definition that is distributed as 15 atom % of the interface oxygen of peak value or Cu alloy-layer and S i semiconductor layer, its thickness is below 1.6nm, in the situation that will be the silica thickness apart from the distance definition that is distributed as 20 atom % of the interface oxygen of peak value or Cu alloy-layer and Si semiconductor layer, its thickness is below 1.4nm, in the situation that will be the silica thickness apart from the distance definition that is distributed as 25 atom % of the interface oxygen of peak value or Cu alloy-layer and Si semiconductor layer, its thickness is below 1.2nm.

In addition, be the plasma oxidation method in the situation that be used to form the oxidation processes of oxidation film, the RF power density of preferred plasma oxidation method is 0.22 above 0.67W/cm ²Below, and the processing time is more than 60 seconds and below 240 seconds, perhaps, the long-pending value in RF power density and above-mentioned processing time is 26.4Wsec/cm ²Above 52.8Wsec/cm ²Below, in addition, at the interface of source electrode and drain electrode and above-mentioned semiconductor layer, the constituent material of source electrode and drain electrode to the line density at the position of above-mentioned semiconductor layer diffusion preferred every be average below 7 apart from 480nm.

As can be known: by satisfying above-mentioned condition, can make the applicable thin film transistor base plate of Cu alloy distribution of electrical characteristics and reliability excellence.

＜semiconductor layer is the situation of oxide semiconductor film 〉

Secondly, the situation that is oxide semiconductor film to semiconductor layer describes.Be oxide semiconductor film at semiconductor layer, when using the Cu alloy in the SD electrode wiring, the oxygen that element interpolation oxidation film is captured in oxide semiconductor by the interpolation element in the Cu alloy forms.Therefore, the equilibrium oxygen electromotive force of the oxide reaction of formation of the interpolation element in the Cu alloy is got the little value than at least a element that consists of oxide semiconductor layer.At this moment, in the oxide semiconductor film of the near interface of having captured oxygen, the free electron number increases, to the n of the character with metal ⁺The oxide semiconductor film modification.Thus, have to intercept in the injection of adding the original charge carrier that exists between element oxide film and oxide semiconductor and reduce, the advantage that degree of excursion improves.

But, when the interpolation element in the Cu alloy is captured oxygen from oxide semiconductor, producing oxygen in the mode of replenishing it and spread towards the outside of Cu alloy film from semiconductor layer, oxygen defect increases in oxide semiconductor film, and the free electron number increases.Thus, produce the negative displacement of threshold voltage and the rising of subthreshold value coefficient, the rising characteristic variation of electric current.

In addition, originally, even compare oxide semiconductor more than the free electron number to be in grid voltage be the tendency that 0V also has normal connection (consumption) action of large current value with Si semiconductor etc., when the injection of the charge carrier that adds element oxide film and oxide semiconductor intercepts reduction, can realize faithfully the characteristic that it is original.The TFT that carries out normal ON Action is difficult to carry out circuit design, for example, is located at the drive circuit of panel periphery section and to the application difficult of the switching transistor of pixel.Therefore, do not make n ⁺Oxide semiconductor film produces, and the injection of keeping the charge carrier that adds element oxide film and oxide semiconductor intercepts, and becomes normal cutoff (enhancing) action, easily carries out circuit design.

By above viewpoint, in the situation that semiconductor layer is oxide semiconductor film, use the Cu alloy for the rising of the negative displacement that do not produce threshold voltage and subthreshold value coefficient and normal ON Action in distribution, require to suppress the diffusion of oxygen from oxide semiconductor film to the Cu alloy-layer.Its method is implemented oxidation processes to oxide semiconductor film before the film forming of Cu alloy, its surface temporarily is modified as insulator.Thus, even follow at film forming Cu alloy and add Elements Diffusion formation interpolation element oxide film in hot processing, also there is necessary sufficient oxygen at the interface of Cu alloy and oxide semiconductor film, therefore, can not produce the diffusion from the oxygen in the deep of oxide semiconductor film.

Fig. 7 means with Cu alloys/oxides film (for example, MnO _xWhen the interpolation element in)/oxide semiconductor layer is made as Mn for example, add the figure that element and oxygen concentration distribute, Fig. 7 (b) means the figure of the example of existing patent documentation 2 records, Fig. 7 (a) means the figure of the example of present embodiment.At this, as shown in Fig. 7 (a), the peak value of oxygen concentration need to be higher than the peak value of the concentration of adding element.So, as above-mentioned, there is necessary sufficient oxygen at the interface of Cu alloy and oxide semiconductor film, therefore, the diffusion from the oxygen in the deep of oxide semiconductor film can not occur.

As final form, as can be known, in the situation that the peak value of the concentration of the peakedness ratio of oxygen concentration interpolation element is low, the diffusion of oxygen reaches the Cu alloy-layer as shown in Fig. 7 (b).On the other hand, as shown in Fig. 7 (a), the interface that the atomic concentration of oxygen is distributed in oxide semiconductor and Cu alloy has the peak, the peak value of the interpolation element in its peakedness ratio Cu alloy is large, thus, the diffusion of oxygen does not reach the Cu alloy-layer, adds element and is difficult to spread to oxide semiconductor layer yet.Therefore, add as can be known element and oxygen and be parked in respectively in oxidation film, there is no its above diffusion.Like this, the detailed manufacture method of TFT is narrated in following embodiment 2.

Below, be that each embodiment in the situation of silicon fiml and situation that semiconductor layer is oxide semiconductor film describes to semiconductor layer.

[embodiment 1]

＜semiconductor layer is the situation of silicon fiml 〉

Below, the manufacture method of the TFT of embodiment 1 is described.The semiconductor layer of the TFT of the present embodiment 1 is made of silicon fiml, in bottom gate type, has the top contact structures that formed source electrode and drain electrode after the semiconductor layer having formed.In addition, the TFT structure becomes numerous and diverse when reflecting correct thickness and size, and therefore, figure is the presentation graphs of signal.

Fig. 8 means the figure of manufacturing process of the TFT of the present embodiment, the profile of the TFT when Fig. 8 (a)～(d) is each operation.

At first, on the substrate 1 that is consisted of by insulating properties materials such as alkali-free glasss, by sputtering method etc. with Cu alloy 2 film forming.The thickness of Cu alloy 2 is for example 10nm～150nm left and right, preferred 20hm～50nm.At this, the Cu alloy 2 that carries out film forming is undertaken the function of the adaptation of improvement and substrate 1.As the interpolation element in Cu alloy 2, be selected from such as more than a kind of manganese (Mn), magnesium (Mg), calcium (Ca), nickel (Ni), zinc (Zn), silicon (Si), aluminium (Al), barium (Be), gallium (Ga), indium (In), iron (Fe), titanium (Ti), vanadium (V), cobalt (Co), zirconium (Zr), hafnium (Hf), persimmon (Ce) etc., preferred addition is 0.5～20 atom %.In addition, due to the reason easy to manufacture and so on of sputtering target material, Cu alloy 2 also can contain the phosphorus (P) of 0.01～10 atom %.To interfacial diffusion, formation oxide, expectation substrate 1 contains the sufficient oxygen atomicity that is necessary in advance for the interpolation element in Cu alloy 2 in the manufacturing process of the heat after being accompanied by.For example, alkali-free glass substrate satisfies this condition.In the present embodiment 1, the Cu-Mn alloy film forming 50hm of 4 atom %Mn will have been added in Cu.The sputtering target material that uses in film forming is to make by following method.Being respectively oxygen-free copper more than 3N and the Mn sheet material more than 3N with purity packs in crucible with the mix proportion of 4.7at%, at the temperature of 1100～1200 ℃ airtight, atmosphere gas by the Ar gas displacement stove in melt.When molten soup concentration becomes full and uniform, will melt soup and inject mould.Remove the oxide scale film (casting skin) of the ingot surface that obtains, implement hot calender at 850 ℃, it is carried out cut, is finish-machined to fixed size, obtain thus the sputtering target material of the present embodiment.Be made as 4.7at% at this interpolation concentration of element with sputtering target material, the result of research is in order to find the interpolation concentration of element in electrode film to reduce by 15%～50% than the interpolation concentration of element in sputtering target material.This can consider that Cu one side preferentially adheres to as film because the plasmoid Cu in sputter departs from for the moment with the interpolation element.Because the ratio that reduces is different because of kind, the concentration of element, so can calculate reduced rate according to combination separately, with reduction part add in sputtering target material, can access the electrode film of fixed interpolation concentration of element in advance more.

Then the film forming of Cu-Mn alloy film, pass through the pure Cu3 of sputtering method continuous film forming equally.The thickness of pure Cu3 is about about 100～1000nm, preferred 200～500nm.In the present embodiment 1, on the Cu-Mn alloy with pure Cu only film forming be 300nm.After it is carried out photo-mask process, use the wet etch method composition, when peeling off resist, can form the gate electrode 4 shown in Fig. 8 (a).Substrate 1 also can use the metallic substrates such as flexible plastic base and stainless steel alloy except alkali-free glass.For the diffusion of inhibition of impurities from substrate 1 to the Cu layer, also can form silicon oxide film, silicon nitride film, silicon oxynitride film or their stacked film as Obstruct membrane on substrate 1.At this moment, in the situation that do not contain enough oxygen atoms in Obstruct membrane, also can use the method for carrying out oxidation processes before the film forming of Cu alloy, forming oxide-film on the Obstruct membrane surface.In addition, about gate electrode 4, also can use Mo, Ti in barrier metal, conductive layer is made of Al, Al alloy.

Secondly, by plasma CVD method, sputtering method, coating process etc., for example as gate insulating film 5 film forming (accumulation) silicon oxide film, silicon nitride film, silicon oxynitride film or their stacked film.This thickness is about 10nm～1000nm, preferred 50～400nm.Temperature when gate insulating film 5 forms is 200～500 ℃ of left and right, and the interpolation element in the Cu alloy 2 of gate electrode 4 lower floors is separated out at the interface, with the oxidation film (not shown) of the interface oneself formation adaptation excellence of substrate 1.Then, by plasma CVD method, sputtering method, coating process, for example, as active semiconductor layer 6 film forming hydrogenated amorphous silicon film successively (a-Si:H), as the adulterated hydrogenated amorphous silicon film (n of phosphorus (P) of contact membranes 7 film forming (accumulation) ⁺A-Si:H) form semiconductor layer 8.The thickness of active semiconductor layer 6 is 10～300nm left and right, and preferred 30～200nm, the thickness of contact membranes 7 are 1～100nm left and right, preferred 5～60nm.In the present embodiment 1, use plasma CVD method, silicon nitride film is formed the 350nm left and right on gate insulating film 5, form hydrogenated amorphous silicon film 180nm left and right as active semiconductor layer 6, form the hydrogenated amorphous silicon film 25nm left and right of adulterated phosphorus (P) as contact membranes 7.Then, as shown in Fig. 8 (b), implement photo-mask process, use dry ecthing method that semiconductor layer 8 is patterned into island, peel off resist.

Again, carry out oxidation processes, form on the surface of semiconductor layer 8 and suppress the Cu atom to the 7a of oxide-film as thin as a wafer of semiconductor layer 8 diffusions.At this moment, oxide-film 7a also forms simultaneously on the surface of gate insulating film 5 as thin as a wafer.As oxidation processes, such as the plasma oxidation method by having used oxygen, nitrous oxide gas, be exposed to method in the oxidizability atmosphere gas such as ozone gas, carrier of oxygen, nitrous oxide gas, the thermal oxidation method of heat-treating in oxidizability atmosphere gas, import ozone gas, the irradiation by UV light generates the excited state oxygen atom, make the UV Ozonation, Ozone Water oxidizing process of its oxidation etc.In the present embodiment 1, adopt the plasma oxidation method of having used oxygen, temporarily form the approximately 7a of oxide-film as thin as a wafer of 1～2nm on semiconductor layer 8.Preferred treatment conditions are RF power density 0.044～0.44W/cm ², 60～600 seconds processing times, be the scope of room temperature～200 ℃ as substrate temperature, consider from the aspect of the reduction of the raising of reliability and manufacturing cost, preferred condition is RF power density 0.22～0.44Wcm ², in 60～240 seconds processing times, substrate temperature is room temperature～150 ℃.

Secondly, by sputtering method, the stacked film that consisted of by Cu alloy 9, pure Cu10 of film forming (accumulation) in order.The thickness of Cu alloy 9 is 10～150nm left and right, and preferred 20nm～50nm, the thickness of pure Cu10 are 100～1000nm left and right, preferred approximately 200～500nm.As the element that adds to Cu alloy 9, such as selecting to be selected from more than a kind of Mn, Mg, Ca, Ni, Zn, Si, Al, Be, Ga, In, Fe, Ti, V, Co, Zr, Hf, Ce etc., preferred 0.5～20 atom % of addition.In addition, consider from the reason of easy manufacturing sputtering target material, Cu alloy 9 also can contain the phosphorus (P) of 0.01～10 atom %.In the present embodiment 1, will sneak into Cu-Mn alloy film forming (accumulation) 50nm of Mn 4 atom % in Cu, the pure Cu of film forming on the Cu-Mn alloy (accumulation) is 300nm.Afterwards, through photo-mask process, by the wet etch method composition, form source electrode 11, drain electrode 12.Secondly, as shown in Fig. 8 (c), the photoresist that the former state utilization is used in source electrode 11 and drain electrode 12 form removes the 7a of oxide-film as thin as a wafer and contact membranes 7 on dechannelling by dry ecthing method, peels off resist.Oxide-film 7a is about 1～2nm as thin as a wafer, and is very thin, therefore, do not hinder the carrying out of dry ecthing.

Again, for the active semiconductor layer 6 that will sustain damage because of dry ecthing solidifies, and carry out H plasma treatment, with the dangling bonds of silicon as the hydrogen terminal.Then, as shown in Fig. 8 (d), by plasma CVD method, sputtering method, coating process film forming (accumulation) for example silicon oxide film, silicon nitride film, silicon oxynitride film or the diaphragm 13 that formed by their stacked film.In the present embodiment 1, the formation of H plasma treatment and diaphragm 13 is to carry out continuously with not breaking vacuum.The thickness of diaphragm 13 is 100～1000nm left and right, preferred 200～500nm.At this moment, the formation temperature of diaphragm 13 is more than 200 ℃, therefore, be arranged in source electrode 11 and drain electrode 12 lower floors Cu alloy 9 the Cu atom and add element and separate out at the interface.The Cu atom of separating out at the interface and add element on contact membranes 7 with the 7a of the oxide-film as thin as a wafer chemical combination that in advance forms, own adaptation and diffusion barrier excellence and the low-resistance oxidation film 14 of forming.At this moment, oneself form too the oxidation film 15 of adaptation and diffusion barrier excellence in the 7a of oxide-film as thin as a wafer that gate insulating film 5 is just being gone up, therefore, can not cause that the film of source electrode 11 and drain electrode 12 is peeled off.In the present embodiment 1, formed the silicon nitride film of 300nm on diaphragm 13.It is carried out photo-mask process, offer for the contact hole (not shown) that carries out the exchange of the signal of telecommunication with external device (ED), peel off resist.Like this, can make the TFT of bottom gate type top contact structures of the display unit of ventilative embodiment 1.

At this, for the present embodiment 1 with adopted the TFT of the prior art of Mo, the narration comparative evaluation result of electrical characteristics values.The component size of the TFT that estimates is that channel width (also referred to as grid width) W is 100 μ m, channel length (also referred to as grid length) L is 10 μ m, in fact with display unit in the component size that adopts approach, the zone of the left and right that the value of the degree of excursion of dead resistance increases.Source-drain electrode voltage is 10V, and degree of excursion and threshold voltage are calculated by the zone of saturation.

Fig. 9 means No.4 (solid line), the No.13 (dotted line) of table 1 and has adopted the figure of transmission characteristic of TFT of the prior art (thick dashed line) of Mo.The longitudinal axis of chart is the logarithm of drain current.Adopt Mo/Cu/Mo in gate electrode 4, adopt Mo/Cu/Mo in source electrode 11 and drain electrode 12, omit oxidation processes in the operation of the present embodiment 1, when other estimated the electrical characteristics of existing TFT of made via same operation, saturated degree of excursion was 0.71cm ²/ Vs, saturation threshold voltage are 1.9V, and the S value is 0.86V/dec.The TFT electrical characteristics of the No.4 of the table 1 of the present embodiment 1 are that saturated degree of excursion is 0.76cm ²/ Vs, saturation threshold voltage are 1.9V, and the S value is 0.93V/dec, with the TFT of the prior art that has adopted Mo equal performance roughly.In addition, there is no the rising of cut-off current yet, equal with the TFT of prior art.This suppresses the Cu atom to the diffusion of semiconductor layer 8, the silicon oxide film that does not play a role as dead resistance at the near interface of source electrode 11 and drain electrode 12 and semiconductor layer 8.In the operation of the present embodiment, the RF power density is set as 1.11W/cm ², the No.13 element of the table 1 of in addition making via same operation as the silicon oxide film that above-mentioned existence plays a role as dead resistance, therefore, is observed degree of excursion and is reduced, that is and, making current reduces.

Like this, TFT according to the present embodiment 1, it is above and below 66 atom % that the interface oxygen atom that is presented at Cu alloy 9 and semiconductor layer 8 exists for 40 atom %, and, when the distance definition that will become apart from the distribution of the interface oxygen of Cu alloy 9 and semiconductor layer 8 10 atom % is the silica thickness, when its thickness satisfies condition below 1.8nm, do not produce the diffusion of Cu atom and the reduction of degree of excursion, can realize that the distribution of Cu alloy is applicable.

In the present embodiment 1, gate electrode 4, source electrode 11, drain electrode 12 are made of the stacked of Cu alloy and pure Cu, still, can be also the individual layers of Cu alloy.As the interpolation element in this situation, from being low-resistance reason consideration, preference such as Ca, Mg, Zn.In addition, can be also the 3-tier architecture of Cu alloy/pure Cu/Cu alloy.

At this, as active semiconductor layer 6, represented to have used the example of hydrogenated amorphous silicon film, still, it is also effective using the technology of the present embodiment in the micro-crystallization silicon with higher degree of excursion and polycrystal silicon, their stacked film.In addition, contact membranes 7 can be also micro-crystallization silicon and polycrystal silicon, or their stacked film.These general names are called Si based semiconductor layer (film).

In addition, the technology of the present embodiment 1 is effective to the semiconductor that does not contain intentionally aerobic, therefore, also can obtain effect same in such as SiGe film of having sneaked into germanium (Ge) in silicon fiml etc.In addition, for the improvement of TFT electrical characteristics, can certainly adopt the channel-etch barrier structure that makes etch stop at channel layer.Top gate type can be also to form the bottom contact structures of source electrode and drain electrode before forming semiconductor layer.

In the situation that think further to reinforce adaptation from semiconductor layer 8 outward extending source electrode 11 and drain electrode 12 and gate insulating film 5, carry out oxidation processes just having formed gate insulating film 5 after, the method for formation oxide-film is effective on gate insulating film 5.In addition, in the situation that the Cu atom from the interfacial diffusion of source electrode 11 and drain electrode 12 and diaphragm 13 and the adaptation of diaphragm 13 becomes fragile, also can carry out oxidation processes before just will forming diaphragm 13.

[embodiment 1 and 2～19]

As shown in table 2, making the element that adds in copper alloy electrode in embodiment 1 is Mo, but use respectively the composition of table 2, the target of interpolation concentration in embodiment 2～19, composition shown in table 2, target are added the copper alloy electrode film forming of concentration with method similarly to Example 1 in the same manner, carry out the manufacturing of thin-film transistor.The actual interpolation concentration of element of source/leakage copper alloy electrode is to take out substrate in manufacture process, use EDX (energy dispersion type x-ray optical spectroscopy) to carry out quantitatively.The thin-film transistor of making was placed 60 days for 25 ℃ in atmosphere, by scanning electron microscope investigate Si semiconductor layer and source/leakage copper alloy electrode peel off have or not.Also have, investigate having or not of the source of the manufacture process of the thin-film transistor/etch residue of leakage copper alloy electrode when forming by etching by SEM.Etching solution uses phosphoric acid: 5wt%, ammonium dihydrogen phosphate: 5wt%, hydrogen peroxide: 2wt%, water: surplus.These the results are shown in table 2.

As a comparative example, use pure Cu target and add the concentration copper alloy target different from scope of the present invention, the film forming copper alloy electrode, will to the Si semiconductor layer of the thin-film transistor made and source/leakages copper alloy electrode peel off have or not, etch residue have or not carry out investigating equally the results are shown in comparative example 1～3.

In embodiment 1～19, because the interpolation concentration of element of sputtering target material increases by 15%～50% than the aimed concn of source/leakage copper alloy electrode, so actual electrode concentration is also the same with target.Also have, make the element 0.5～20at% of adaptation raising due to interpolation, so also do not see peeling off of copper alloy electrode.Have again, do not see the generation of etch residue in the scope of 0.5～20at%.

On the other hand, because nothing in comparative example 1 is added element, peeling off of copper alloy electrode occured.In comparative example 2, to add concentration of element identical due to the target of the interpolation concentration of element of sputtering target material and copper alloy electrode, and the interpolation concentration of element of actual copper alloy electrode becomes below 0.5a t%, sees peeling off of copper alloy electrode.In comparative example 3, because the interpolation concentration of element in electrode surpasses 20%, produced etch residue when etching.

[embodiment 20]

＜semiconductor layer is the situation of oxide semiconductor film 〉

Below, the manufacture method of the TFT of embodiments of the invention 20 is described.The semiconductor layer of the TFT of the present embodiment 20 is made of oxide semiconductor film, has the top contact structures that formed source electrode and drain electrode after the semiconductor layer having formed in bottom gate type.In addition, when the correct thickness of reflection, size, the TFT structure becomes numerous and diverse, therefore, and the expression of illustrating in the drawings.In addition, be omitted in an one of repeat specification in the present embodiment 2 and embodiment 1.

The figure of the section of the TFT when Figure 10 (a)～(d) means each operation.At first, similarly to Example 1, on the substrate 1 that is consisted of by insulating properties materials such as alkali-free glasss, by sputtering film-forming (accumulation) Cu alloy 2.Secondly, equally by the pure Cu 3 of sputtering method continuous film forming (accumulation).This has been carried out after the photo-mask process, used the wet etch method composition, peeled off resist.At this, make the gate electrode 4 shown in Figure 10 (a).

Secondly, by film forming (accumulation) such as plasma CVD method, sputtering method, coating processs for example as silicon oxide film, silicon nitride film, silicon oxynitride film, pellumina, tantalum-oxide film or their stacked film of gate insulating film 5.Thickness is about 10nm～1000nm, preferred 50～400nm.At this moment, the temperature when film forms is 200～500 ℃ of left and right, and the interpolation element in the Cu alloy 2 of gate electrode 4 lower floors is separated out at the interface, with the oxidation film (not shown) of the interface oneself formation adaptation excellence of substrate 1.

Again, as required, carry out oxidation processes, form oxide-film (not shown) as thin as a wafer on the surface of gate insulating film 5.Its reason is because suppressing the Cu atom on the basis of the diffusion of gate insulating film 5, can reduce the hydrogen of sneaking into from gate insulating film 5 to oxide semiconductor film.

Secondly, by the oxide semiconductor of the film forming (accumulation) such as plasma CVD method, sputtering method, coating process as active semiconductor layer 6.Oxide semiconductor for such as: zinc oxide, indium oxide, gallium oxide, tin oxide, cupric oxide, zirconia, titanium oxide, aluminium oxide copper, zinc-tin oxide, indium zinc oxide, oxidation gallium indium, zinc-gallium oxide tin, indium oxide magnesium, indium zinc oxide hafnium, zinc oxide gallium indium etc. are made of the oxide that contains the element more than a kind that is selected from Zn, In, Ga, Sn, Al, Ti, Mg, Zr, Cu, Hf at least.Wherein, the oxide semiconductor that preferably uses the amorphous zinc oxide gallium indium (a-InGaZnO) of homogeneity excellence of the electrical characteristics of TFT to be.The thickness of active semiconductor layer 6 is about 1～200nm, for the grid voltage that will be made as dissengaged positions is adjusted near 0V, and preferred 10～100nm.

Again, as shown in Figure 10 (b), implement photo-mask process, use dry ecthing method or wet etch method that active semiconductor layer 6 is patterned into island, peel off resist.The composition of island uses stripping method also can form.In this case, implement photo-mask process before the film forming of active semiconductor layer 6.

Secondly, carry out oxidation processes, the upper strata of active semiconductor layer 6 and gate insulating film 5 temporarily is modified as dielectric film 6a.In the present embodiment 20, adopted the plasma oxidation method of having used nitrous oxide gas by the oxidation intensity of force.Thus, afterwards, even the interpolation Elements Diffusion in Cu alloy 2, form to add the element oxide film, also there is necessary sufficient oxygen at the interface of Cu alloy 2 and active semiconductor layer 6, therefore, can not produce diffusion from the oxygen in the deep of oxide semiconductor film 6.

Again, similarly to Example 1, by sputtering method, the stacked film that consisted of by Cu alloy 9, pure Cu 10 of film forming in order.The thickness of Cu alloy 9 is 10～150nm left and right, and preferred 20nm～50nm, the thickness of pure Cu10 are 100～1000nm left and right, preferred approximately 200～500nm.At this moment, add the element oxide film in order to form, the equilibrium oxygen electromotive force of the oxide reaction of formation of the interpolation element in Cu alloy 9 is selected in the mode than the little value of the a kind of element that consists of active semiconductor layer 6 at least.

For example, can select more than a kind preferred 0.5～20 atom % of addition from Mn, Mg, Ca, Zn, Si, Al, Be, Ga, Ti, V, Zr, Hf, Ce etc.Also have, becoming from the manufacturing of sputtering target material is easy to reason and considers, Cu alloy 9 also can contain phosphorus (P) 0.01～10 atom %.The manufacture method of sputtering target material can be taked method similarly to Example 1, and the interpolation concentration of element of sputtering target material adds concentration of element increase by 15%～50% than the target in copper alloy electrode and is advisable.In the present embodiment 20, adopt the Cu-Mn alloy in Cu alloy 9.The equilibrium oxygen electromotive force of the oxide reaction of formation of Mn satisfies the Constitution Elements I n of specific activity semiconductor layer 6, the condition that Ga, Zn are little.Afterwards, as shown in Figure 10 (c), through photo-mask process, by wet etch method or dry ecthing method composition, form source electrode 11, drain electrode 12.At this moment, the dielectric film 6a prolection semiconductor layer 6 on active semiconductor layer 6 is not subjected to the damage that produces in etching work procedure, play a role as the etching barrier layer yet.

Secondly, as shown in Figure 10 (d), the diaphragm 13 that is for example consisted of by silicon oxide film, silicon nitride film, silicon oxynitride film or their stacked film by film forming (accumulation) such as plasma CVD method, sputtering method, coating processs.The thickness of diaphragm 13 is 100～1000nm left and right, preferred 200～500nm.At this moment; the formation temperature of diaphragm 13 is more than 200 ℃; therefore; be arranged in source electrode 11 and drain electrode 12 lower floors Cu alloy 9 the Cu atom and add element and separate out at the interface; with the dielectric film 6a chemical combination that forms in advance, oneself form adaptation and diffusion barrier impenetrability excellence and low-resistance oxidation film 14 on active semiconductor layer 6.In addition; in the situation that the part of diaphragm 13 is made of silicon nitride film; produce hydrogen to the diffusion of active semiconductor layer 6; sometimes cause the reduction of electrical characteristics; but; the dielectric film 6a on the upper strata of active semiconductor layer 6 suppresses its reduction, also has to prevent that hydrogen is to the effect of the diffusion of oxide semiconductor film.In addition, also oneself form the oxidation film 15 of adaptation and diffusion barrier impenetrability excellence on the dielectric film 6a that gate insulating film 5 is just being gone up, therefore, the film that is difficult to produce source electrode 11 and drain electrode 12 is peeled off.Also have, to its row photo-mask process, offer for the contact hole (not shown) that carries out the exchange of the signal of telecommunication with external device (ED), peel off resist.Like this, can make the oxide semiconductor TFT of embodiment 2.

At this, the peakedness ratio of the atomic concentration of the present embodiment 20 and oxygen is added the TFT of the little prior art of its value of element, carry out the comparative evaluation of electrical characteristics.Figure 11 means the figure of schematic diagram of transmission characteristic of the TFT of the present embodiment 2 and prior art.The longitudinal axis of chart is the logarithm of drain current.When seeing the transmission characteristic of TFT of prior art, making current is large, still, causes the negative displacement of threshold voltage, the rising of subthreshold value coefficient, becomes normal ON Action.But the TFT of the present embodiment 2 that the peak value of the peakedness ratio interpolation element of the atomic concentration of oxygen is large becomes near the normal cutoff action of sharply rising grid voltage 0V.Therefore, according to the present embodiment 2, shown the diffusion that suppresses from the oxygen of active semiconductor layer 6, can carry out the Cu alloy and use to the distribution of oxide semiconductor TFT.

In the present embodiment 20, gate electrode 4, source electrode 11, drain electrode 12 are made of the stacked of Cu alloy and pure Cu, still, can be also the individual layers of Cu alloy.As the interpolation element in this situation, think low-resistance reason consideration, preference such as Ca, Mg, Zn.In addition, can be also the 3-tier architecture of Cu alloy/pure Cu/Cu alloy.In addition, the oxide semiconductor that is used for active semiconductor layer 6 can be also amorphous can be also many crystallizations, also can be applicable to their stacked film.In addition, the purpose that is improved as with the TFT electrical characteristics also can adopt the channel-etch barrier structure.Can be also top gate type and bottom contact structures.

In the situation that the Cu atom becomes fragile from the interfacial diffusion of source electrode 11 and drain electrode 12 and diaphragm 13, the adaptation of diaphragm 13, also can carry out oxidation processes before just will forming diaphragm 13.

In addition, stablize and homogeneous in order to make the TFT electrical characteristics, also can apply in addition heat treatment after forming oxide semiconductor.Heat treatment is preferably carried out after forming source electrode 11 and drain electrode 12.And due to the diffusion that can promote the interpolation element in source electrode 11 and drain electrode 12, easily form oxidation film 14, oxidation film 15.

[embodiment 20 and 21～34]

As shown in table 3, in embodiment 20, making the element that adds in copper alloy electrode is Mo, but use respectively the composition of table 3, the target of interpolation concentration in embodiment 21～34, composition shown in table 3, target are added the copper alloy electrode film forming of concentration with method similarly to Example 20 in the same manner, carry out the manufacturing of thin-film transistor.The actual interpolation concentration of element of source/leakage copper alloy electrode is to take out substrate in manufacture process, use EDX (energy dispersion type x-ray optical spectroscopy) to carry out quantitatively.The thin-film transistor of making was placed 60 days for 25 ℃ in atmosphere, by scanning electron microscope investigate Si semiconductor layer and source/leakage copper alloy electrode peel off have or not.Also have, investigate having or not of the source of the manufacture process of the thin-film transistor/etch residue of leakage copper alloy electrode when forming by etching by SEM.Etching solution uses phosphoric acid: 5wt%, ammonium dihydrogen phosphate: 5wt%, hydrogen peroxide: 2wt%, water: surplus.These results are shown in table 3 altogether.

As a comparative example, the equilibrium oxygen electromotive force of oxide reaction of formation that uses pure Cu target and add the concentration copper alloy target different from scope of the present invention and added element is than Ni, the In of the large value of the equilibrium oxygen electromotive force of the element of formation oxide semiconductor layer or equal value, the copper alloy target of Fe, Co, the film forming copper alloy electrode, will to the oxide semiconductor layer of the thin-film transistor made and source/drain electrode layer peel off have or not, etch residue have or not carry out investigating equally the results are shown in comparative example 6～12.

In embodiment 20～34, because the interpolation concentration of element of sputtering target material increases by 15%～50% than the aimed concn of source/leakage copper alloy electrode, so actual electrode concentration is also the same with target.Also have, make the element 0.5～20at% of adaptation raising due to interpolation, so also do not see peeling off of copper alloy electrode.Have again, do not see the generation of etch residue in the scope of 0.5～20at%.

On the other hand, because nothing in comparative example 6 is added element, peeling off of copper alloy electrode occured.In comparative example 7, to add concentration of element identical due to the target of the interpolation concentration of element of sputtering target material and electrode, and the interpolation concentration of element of actual electrode becomes below 0.5at%, sees peeling off of copper alloy electrode.In comparative example 8, because the interpolation concentration of element in electrode surpasses 20%, produced etch residue when etching.In comparative example 9～12, because the equilibrium oxygen electromotive force of the oxide reaction of formation of adding element is larger or equal than the equilibrium oxygen electromotive force of the element that consists of oxide semiconductor layer 6, do not add the element oxide layer and the adaptation reduction so generate at the interface with oxide semiconductor layer, see peeling off of copper alloy electrode.

[embodiment 35]

＜display unit 〉

Figure 12 and Figure 13 are the figure of the content of illustrated embodiment 35, be explanation take liquid crystal indicator as example, display unit is used the figure of method of the TFT of embodiment 1 and embodiment 2.In addition, for fear of numerous and diverse, omit the diagram of the detailed structure of TFT.

Figure 12 is the figure of the pixel configuration example on TFT substrate 101 in the active array type LCD 100 of illustrated embodiment 35.As shown in figure 12, the holding wire 103 that has scan line 102 and form in the direction of square crossing therewith on TFT substrate 101.Crosspoint at scan line 102 and holding wire 103 is provided with TFT104, and the part of the distribution of the TFT104 pair pixel electrode that is connected with TFT104 105 connects.In addition, use the part of pixel electrode 105 and scan line 102 to form energy storage capacitor 106.In addition, in the operation that forms scan line 102, the gate electrode 4 (not shown) of the TFT of embodiment 1 and embodiment 20, source electrode 11 (not shown) and the drain electrode 12 (not shown) of the TFT of formation embodiment 1 and embodiment 20 in the operation that forms holding wire 103.

Figure 13 means the profile of configuration example of the active array type LCD of embodiment 35.As shown in figure 13, liquid crystal indicator 100 has light source 111, polarizer 112, TFT substrate 101, TFT104, dielectric film 113, pixel electrode 105, alignment films 114, liquid crystal layer 115, pad 116, common electrode 117, colour filter 118, black matrix 119, filter substrate 120, polarizing coating 121.

At this, the display control method of liquid crystal indicator 100 is briefly described.The light of emitting from light source 111 utilizes polarizer 112 only by specific polarised light part, towards liquid crystal layer 115.Liquid crystal layer 115 is according to the voltage to pixel electrode 105 and common electrode 117 supplies, by adjusting the level of controlling pixel by the light transmission of polarizing coating 121.

Then, on one side the control method of liquid crystal layer 115 is narrated simply with reference to Figure 12 on one side.At first, TFT104 becomes on-state when applying signal from scan line 102 to TFT104, and the signal voltage that is added on holding wire 103 applies to pixel electrode 105 and energy storage capacitor 106 via TFT104.Thus, liquid crystal layer 115 is applied desirable voltage, light transmission is controlled in the liquid crystal molecule action.At this moment, energy storage capacitor 106 has the function that keeps voltage signal.That is, even TFT104 is cut off, before applying next signal, will be adjusted into necessarily to the voltage levvl that liquid crystal layer 115 is supplied with.

According to the TFT of the present embodiment, the reduction ground that does not produce the electrical characteristics value of TFT can realize that the distribution of Cu alloy uses.At this moment, suppress the depth distribution of the suitableeest oxygen of the reduction of resistance by prompting, can be with the electrode of Cu Alloyapplication in thin-film transistor.In the above-described embodiment, for illustrated formation in accompanying drawing etc., be not subjected to their restriction, can suitably change in the scope of performance effect of the present invention.In addition, as long as can suitably change in the scope that does not break away from purpose of the present invention.

Utilizability on industry

The present invention can be applicable to thin-film transistor.

Claims

1. thin-film transistor, it is for to possess on substrate: gate insulating film, Si based semiconductor layer, have the source/drain electrode of Cu alloy-layer and at the thin-film transistor of the oxidation film of the interface formation of described source electrode and drain electrode and described Si based semiconductor layer, it is characterized in that

Described Cu alloy-layer contains Cu and at least a interpolation element,

The peak value of the depth distribution of the atomic concentration of the oxygen in described oxidation film is more than 40 atom % and below 66 atom %, and, will apart from the peak value of the atomic concentration of described oxygen or when being the thickness of described oxidation film apart from the distance definition that the distribution of the oxygen at the interface of described source electrode and drain electrode and described Si based semiconductor layer becomes 10 atom %, the thickness of described oxidation film is below 1.8nm.

2. thin-film transistor as claimed in claim 1, it is characterized in that, at the interface of described source electrode and drain electrode and described Si based semiconductor layer, the constituent material of described source electrode and drain electrode is every average below 7 apart from 480nm to the line density at the position of described Si based semiconductor layer diffusion.

3. thin-film transistor as claimed in claim 1, it is characterized in that, described Cu alloy-layer comprises Cu and the interpolation element more than at least a kind of selecting from Mn, Mg, Ca, Ni, Zn, Si, Al, Be, Ga, In, Fe, Ti, V, Co, Zr, Hf, Ce, the concentration of adding element is 0.5～20at%.

4. the manufacture method of thin-film transistor, thin-film transistor possesses on substrate: gate insulating film, Si based semiconductor layer, have the source/drain electrode of the Cu alloy-layer that contains Cu and at least a interpolation element and at the oxidation film of the interface formation of described source electrode and drain electrode and described Si based semiconductor layer, it is characterized in that

Form gate electrode structure on described substrate, on piled up gate insulating film after, have:

Pile up the step of described Si based semiconductor film on described gate insulating film;

Form the step of oxide-film as thin as a wafer by the plasma oxidation method on the surface of described Si based semiconductor layer; And

Formation has the step of the source/drain electrode of described Cu alloy-layer,

Described oxidation film forms by the plasma oxidation method, and the RF power density in described plasma oxidation method is 0.22～0.67W/cm ²Below, and the processing time is more than 60 seconds and below 240 seconds.

5. the manufacture method of thin-film transistor, thin-film transistor possesses on substrate: gate insulating film, Si based semiconductor layer, have the source/drain electrode of the Cu alloy-layer that contains Cu and at least a interpolation element, at the oxidation film of the interface formation of described source electrode and drain electrode and described Si based semiconductor layer, it is characterized in that

Described oxidation film forms by the plasma oxidation method,

The long-pending value in the RF power density in described plasma oxidation method and described processing time is 26.4～52.8Wsec/cm ²

6. sputtering target material, it is characterized in that, it is to comprise the sputtering target material that uses in the formation of source/drain electrode of copper alloy of thin-film transistor of the record of any one in claim 1～3, compares in the scope concentration of (adding concentration of element * more than 15% and less than 50%) high with the interpolation concentration of element in copper alloy layer.

7. thin-film transistor; it possesses on substrate: have oxidation film gate insulating film, oxide semiconductor layer, have the source/drain electrode of the Cu alloy-layer that contains Cu and at least a interpolation element, at oxidation film and the whole diaphragm of protection of the interface formation of described source electrode and drain electrode and described oxide semiconductor layer; it is characterized in that

In described oxidation film, the interpolation element in described source electrode and drain electrode and the atomic concentration of oxygen have the peak, and the peak value that the peakedness ratio of oxygen adds element is large.

8. thin-film transistor as claimed in claim 7, is characterized in that, the equilibrium oxygen electromotive force of the oxide reaction of formation of the interpolation element in described source electrode and drain electrode is less than the equilibrium oxygen electromotive force of at least one element that consists of described oxide semiconductor layer.

9. thin-film transistor as claimed in claim 7, it is characterized in that, the Cu alloy-layer of described source electrode and drain electrode comprises Cu and the interpolation element more than at least a kind of selecting from Mn, Mg, Ca, Zn, Si, Al, Be, Ga, Ti, V, Zr, Hf, Ce, the concentration of adding element is 0.5～20at%.

10. thin-film transistor as claimed in claim 7, is characterized in that, the part of described diaphragm is made of silicon nitride film.

11. the manufacture method of thin-film transistor; thin-film transistor possesses on substrate: have oxidation film gate insulating film, oxide semiconductor layer, have the source/drain electrode of the Cu alloy-layer that contains Cu and at least a interpolation element, at oxidation film and the whole diaphragm of protection of the interface formation of described source electrode and drain electrode and described oxide semiconductor layer; it is characterized in that

In forming the step of described diaphragm, impose a condition into:

12. sputtering target material, it is characterized in that, it is to comprise the sputtering target material that uses in the formation of source/drain electrode of copper alloy of thin-film transistor of claim 7 record, compares with the interpolation concentration of element in copper alloy layer to add concentration of element * more than 15% and the scope concentration of less than 50% high.

13. display unit, it has used thin-film transistor claimed in claim 1.

14. sputtering target material, it comprises Cu and the interpolation element more than at least a kind of selecting from Mn, Mg, Ca, Ni, Zn, Si, Al, Be, Ga, In, Fe, Ti, V, Co, Zr, Hf, Ce, and the concentration of adding element is 0.7～40a t%.

15. sputtering target material, it comprises: the Mn of 0.7～29at%, and surplus is Cu.