JP2011150152A - Method of manufacturing display device, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a display device that hardly causes peeling of a drain electrode and a source electrode even when the drain electrode and source electrode using copper are exposed on a substrate when performing hydrogen termination processing of a semiconductor layer. <P>SOLUTION: The method of manufacturing the display device having the substrate arranged with a plurality of thin film transistors includes: an electrode forming step of forming the source electrode and drain electrode including a single layer or a plurality of conductive layers on a part of the semiconductor layer of the thin film transistor; and a hydrogen termination step of applying the hydrogen termination processing to the semiconductor layer with the source electrode and drain electrode exposed on the substrate. The electrode forming process includes a step of sticking copper on the substrate by introducing inert gas containing neon. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a display device including a TFT substrate driven by a thin film transistor, and a display device.

  A liquid crystal panel provided with a TFT substrate is applied to a large-screen thin television. In recent years, the driving frequency has been increased in order to improve the moving image quality, and accordingly, the resistance of the signal line needs to be lowered. Further, in the process of forming signal lines, thin film materials and process chemicals with good cost performance are required.

  Conventionally, in order to construct a signal line of a low-resistance TFT substrate, a Mo / Al / Mo laminated film (where / represents the interface of the lamination, where Is the lower layer, and the left side of / is the upper layer. In this specification, the same shall apply hereinafter). In order to further reduce the resistance of the signal line of this laminated film, the Al layer must be thickened. However, since the time spent for forming the Mo / Al / Mo laminated film becomes longer, the productivity is deteriorated. As a result, problems such as increasing the frequency of occurrence of hillocks that cause deterioration in manufacturing yield occur. In terms of material costs, in addition to using expensive molybdenum as the barrier film and cap film for the lower and upper layers of aluminum, phosphoric acid, the main component of the etching solution, is rising as fertilizer demand increases. There are many high-cost factors.

  Copper is an example of a signal line material having a low resistivity lower than that of aluminum and a reasonable material cost. Copper has a feature that the resistivity of a thin film is as low as about 2 μΩcm, and it can be in direct electrical contact with a transparent conductive film (generally an oxide containing indium as a main component). .

  As a method of using copper for a signal line, for example, as described in Patent Document 1, there is a method of applying a signal line made of a Cu / Mo laminated film. In this signal line film structure, molybdenum is responsible for securing adhesion to the base and also serves as a copper diffusion barrier to the semiconductor layer.

  As another method of using copper for the signal line, the wiring film is composed of copper and an alloy containing copper as a main component. In Non-Patent Document 1, as a method of forming source / drain electrodes of a TFT substrate, a surface of a contact layer of a semiconductor layer is pre-oxidized, a CuMn alloy is formed thereon, and then heat-treated in an argon atmosphere to form a CuMn alloy. / A method for depositing Mn as an oxide on the contact layer interface and the CuMn alloy surface is described. As a result, the adhesion, the copper diffusion barrier, and the low resistivity are realized. Although Non-Patent Document 1 uses a CuMn alloy, even when other Cu alloys are used, the same effect can be expected if an additive element of the Cu alloy can be precipitated as an oxide at the Cu alloy / contact layer interface. .

  In the above-mentioned Non-Patent Document 1, the base of the copper alloy contains oxygen, the additive element in the copper alloy reacts with the oxygen in the base to form an oxide layer of the additive element at the interface, and the oxide The layer functions as an adhesion layer or a copper barrier layer. However, the Cu alloy has a higher resistivity than Cu. Therefore, the resistance is reduced by adopting a laminated structure such as a Cu / CuMn alloy as the film structure of the source / drain electrodes.

JP 2004-163901 A JP 2007-27259 A

“Solving source and drain issues left on all low-resistance Cu alloys for large-screen LCD wiring”, Tohoku University Graduate School of Engineering press release, September 10, 2008

  However, when the drain layer and the source electrode using Cu are exposed on the substrate when the semiconductor layer is subjected to hydrogen termination, the drain electrode and the source electrode may be peeled off from the base.

  For example, when the inventors tried to create a thin film transistor substrate by adopting a film structure of Cu / Cu alloy, the channel was formed after forming the channel of the thin film transistor by processing the drain electrode, the source electrode, and the contact layer. In the process of hydrogen termination treatment of the surface of the semiconductor layer using hydrogen plasma, a phenomenon that the Cu / Cu alloy peels off from the contact layer and the gate insulating film occurred.

  In view of the above-described problems, the present invention provides a separation of the drain electrode and the source electrode even when the drain electrode and the source electrode using Cu are exposed on the substrate when performing the hydrogen termination treatment of the semiconductor layer. It is an object of the present invention to provide a method for manufacturing a display device that makes it difficult to cause a problem and a display device. Problems other than those described above will be clarified in this specification.

  In view of the above problems, a method for manufacturing a display device according to the present invention is a method for manufacturing a display device having a substrate on which a plurality of thin film transistors are arranged. An electrode forming step of forming a source electrode and a drain electrode including a conductive layer; a hydrogen termination step of performing a hydrogen termination process on the semiconductor layer in a state where the source electrode and the drain electrode are exposed on the substrate; The electrode forming step includes a step of depositing copper on the substrate by introducing an inert gas containing neon.

  In one embodiment of the method for manufacturing a display device according to the present invention, the electrode forming step includes a first vapor deposition step of depositing a copper alloy on the substrate, and a copper layer on the substrate after the first vapor deposition step. And a second vapor deposition step for vapor-depositing an inert gas, wherein at least one of the first vapor deposition step and the second vapor deposition step is introduced with an inert gas containing neon.

  In one aspect of the method for manufacturing a display device according to the present invention, the sputtering target in the first vapor deposition step is a copper alloy containing copper as a main component and containing at least one additive element, and in the second vapor deposition step. The sputtering target may be copper having a purity higher than that of the copper alloy.

  Moreover, in one aspect of the method for manufacturing a display device according to the present invention, the sputtering target in the first vapor deposition step is at least one kind of additive element containing copper as a main component and not less than 0.5 atom% and not more than 20 atom%. The sputtering target in the second vapor deposition step may be copper having a purity of 99.5 atomic% or more.

  In view of the above problems, a display device according to the present invention is a display device including a substrate on which a plurality of thin film transistors are arranged. The thin film transistor includes a semiconductor layer and a plurality of layers over a part of the semiconductor layer. Alternatively, it has a source electrode and a drain electrode formed by laminating a single conductive layer, and the source electrode and the drain electrode have at least one conductive layer containing copper and neon. To do.

  In the display device according to the aspect of the invention, the source electrode and the drain electrode may include a first conductive layer containing a copper alloy containing copper as a main component and at least one additive element, and the first conductive layer. A second conductive layer containing copper having a purity higher than that of the copper alloy, and at least one of the first conductive layer and the second conductive layer is neon. It may be characterized by containing.

  In the display device according to the aspect of the invention, the second conductive layer may include 99 atomic% or more of copper and 0.01 atomic% or more and 1 atomic% or less of neon. .

  In one embodiment of the display device according to the present invention, the source electrode and the drain electrode are introduced with an inert gas containing neon or argon using a copper alloy containing at least one additive element as a sputtering target. And a second conductive layer deposited by introducing an inert gas containing neon using copper having a higher purity than the copper alloy as a sputtering target. , That may be characterized.

  According to the present invention, when hydrogen termination treatment of a semiconductor layer is performed, even if the source electrode and drain electrode using Cu are exposed on the substrate, a method for manufacturing a display device that hardly causes peeling. And a display device can be provided.

1 is a diagram schematically showing an in-plane switching type liquid crystal display device according to Embodiment 1. FIG. 2 is a schematic view of a TFT substrate included in the liquid crystal panel in Embodiment 1. FIG. 1 is a schematic cross-sectional view of a liquid crystal panel in Embodiment 1. FIG. 6 is a diagram illustrating a state of a TFT substrate in a first photolithography process in Embodiment 1. FIG. FIG. 3 is a flowchart of a first photolithography process in the first embodiment. 6 is a diagram illustrating a state of a TFT substrate in a second photolithography process in Embodiment 1. FIG. 6 is a flowchart of a second photolithography process in Embodiment 1. FIG. 6 is a diagram illustrating a state of a TFT substrate in a third photolithography process in Embodiment 1. FIG. 5 is a flowchart of a third photolithography process in Embodiment 1. FIG. 6 is a diagram showing a state of a TFT substrate in a fourth photolithography process in Embodiment 1. FIG. FIG. 6 is a flowchart of a fourth photolithography process in the first embodiment. 6 is a diagram illustrating a state of a TFT substrate in a fifth photolithography process in Embodiment 1. FIG. 6 is a flowchart of a fifth photolithography process in Embodiment 1. FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. It goes without saying that the present invention can be modified as appropriate without departing from the technical idea of the embodiments described below.

[Embodiment 1]
FIG. 1 is a diagram schematically showing an in-plane switching type liquid crystal display device 700 according to the present embodiment. In the liquid crystal display device 700, a liquid crystal panel 800 is held so as to be sandwiched between an upper frame 710 and a lower frame 720, as shown in FIG. A backlight (not shown) is disposed below the liquid crystal panel 800. The liquid crystal panel 800 includes a TFT substrate on which a plurality of thin film transistors are arranged, and a counter substrate. FIG. 2 is a schematic view of a TFT substrate 800a included in the liquid crystal panel 800 according to the present embodiment. As shown in the figure, a plurality of scanning signal lines 802 and a plurality of video signal lines 809 are laid in a grid pattern on the TFT substrate 800a. Scanning signal lines 802 and video signal lines 809 are supplied with signals from drive circuits 830 and 840. In addition, a pixel region 810 that functions as one pixel of the liquid crystal display device 700 is formed corresponding to the division by these signal lines.

  FIG. 3 is a schematic cross-sectional view of the in-plane switching type liquid crystal panel 800 according to the present embodiment. As shown in the figure, the liquid crystal panel 800 has a TFT substrate 800a and a counter substrate 800b, and the liquid crystal 16 is sealed between them. In the thin film transistor according to the present embodiment, the semiconductor layer is constituted by the first semiconductor layer 6 and the second semiconductor layer 7, the gate electrode 2 is constituted by the transparent conductive film 2 a and the wiring layer 2 b, and the drain electrode 9 and the source electrode 10 are formed. Is composed of first conductive layers 9a and 10a, second conductive layers 9b and 10b, and oxide layers 9c and 10c. In this embodiment, the drain electrode 9 is connected to the video signal line 809 and the gate electrode 2 is connected to the scanning signal line 802. The drain electrode 9 and the video signal line 809, and the gate electrode 2 and the scanning signal line 802 are formed in the same process and have the same stacked structure.

  A method for manufacturing the TFT substrate 800a will be described with reference to FIGS. 4A to FIG. 8A, FIG. 4A, FIG. 5A, FIG. 6A, FIG. 7A, and FIG. 8A show schematic views of the TFT substrate 800a in each step, and FIG. FIG. 8B shows the flow of each process.

  FIGS. 4 to 8 are divided according to each photolithography process, and FIGS. 4A, 5A, 6A, 7A, and 8A show the stage where the photoresist is removed. In the following description, resist pattern formation refers to a series of steps from application of a photoresist to selective exposure using a mask until development and baking, and repeated description is avoided. The following explanation is based on the divided steps.

  FIG. 4A is a diagram illustrating a state of the TFT substrate 800a in the first photolithography process, and FIG. 4B is a flowchart of the first photolithography process. As shown in FIG. 4A, the gate electrode 2 is formed by the transparent conductive film 2a and the wiring layer 2b, the common electrode is formed by the transparent conductive film 3a, and the common signal line is formed by the wiring layer 3b.

  In the flowchart of FIG. 4B, first, in S101, a transparent conductive film made of indium tin oxide is formed on the glass substrate 1 made of non-alkali glass by sputtering, and a wiring layer is formed by sputtering. Here, the transparent conductive film may be indium zinc oxide or indium tin zinc oxide. The film thickness is about 10 nm to 150 nm, and preferably about 20 nm to 50 nm. The wiring layer may be formed using aluminum or copper.

  Next, a resist pattern is formed using a half exposure mask (S102). Here, the resist is formed thickly without exposing the portions constituting the wiring layer 2b (including the scanning signal line 802) and the wiring layer 3b (common signal line), and the transparent conductive film 3a (common electrode) is formed. In the portion, a resist is thinly formed as half exposure. Thereafter, the wiring layer in the portion where the resist is not formed (binary exposure portion) is selectively removed by etching (S103), and then the transparent conductive film is selectively removed by etching (S104).

  Next, the resist in the half exposure portion is removed by ashing (S105). After ashing, the wiring layer in the half-exposure part is selectively removed by etching (S106), and the resist is peeled off (S107).

  Through the first photolithography process, the scanning signal line 802 (including the gate electrode 2 and the scanning signal line terminal), the common signal line (including the common signal line terminal), and the common (transparent) electrode are formed.

  FIG. 5A is a diagram illustrating a state of the TFT substrate 800a in the second photolithography process, and FIG. 5B is a flowchart of the second photolithography process. As shown in FIG. 5A, in the second lithography process, the gate insulating film 5, the first semiconductor layer 6, and the second semiconductor layer 7 are formed.

  The flowchart of FIG. 5B will be described. As shown in the figure, first, in S201, plasma is applied to the gate insulating film 5 made of silicon nitride, the first semiconductor layer 6 made of amorphous silicon, and the second semiconductor layer 7 made of n + type amorphous silicon. Films are continuously formed by chemical vapor deposition. The first semiconductor layer 6 is a semiconductor layer that controls a current between the source electrode 10 and the drain electrode 9 when an electric field is applied from the wiring layer 2b, and the second semiconductor layer 7 includes the source electrode 10 and the drain electrode. 9 is a semiconductor layer in contact with 9 respectively.

  Next, a resist pattern is formed using a binary exposure mask (S202). Thereafter, the second semiconductor layer 7 and the first semiconductor layer 6 are selectively removed by etching (S203). Then, when the resist is removed, a so-called island pattern is formed (S204). Here, the surface of the second semiconductor layer 7 is oxidized (S205). The oxidation treatment method may be any of oxygen plasma treatment, ozone water treatment, hydrogen peroxide solution treatment, hot water treatment, atmospheric oxidation treatment, or other methods.

  In particular, FIG. 6A is a diagram illustrating a state of the TFT substrate 800a in the third photolithography process, and FIG. 6B is a flowchart of the third photolithography process. The third lithography process is a process of forming the source electrode 10 and the drain electrode 9 on a part of the second semiconductor layer 7 (electrode formation process). As shown in FIG. 6A, in this embodiment, the drain electrode 9 is formed including two layers of the first conductive layer 9a and the second conductive layer 9b, and the first conductive layer 10a and the second conductive layer 9b are formed. The source electrode 10 is formed including the two layers 10b. Further, the first conductive layers 9a and 10a are formed so as to contain a copper alloy containing at least one kind of additive element and containing copper as a main component. The second conductive layers 9b and 10b include It is formed so as to contain copper having a higher purity than the copper alloy.

  In S301 of the third photolithography step shown in FIG. 6B, first, the first conductive layer is formed by the first vapor deposition step, and then the second conductive layer is formed by the second vapor deposition step. .

  The sputtering target in the first vapor deposition step is a copper alloy containing copper as a main component and containing at least one additional element that is 0.5 atomic% or more and 20 atomic% or less. Moreover, the sputtering target in a 2nd vapor deposition process is copper which has a purity of 99.5 atomic% or more. By the first vapor deposition step and the second vapor deposition step, copper is deposited on the TFT substrate 800a. In the present embodiment, specifically, in the first vapor deposition step, the first conductive layer is vapor-deposited on the TFT substrate 800a using a sputtering target made of an alloy containing 4 atomic% of manganese and containing copper as a main component. Is done. In the second vapor deposition step, the second conductive layer is vapor-deposited on the TFT substrate 800a using a sputtering target made of 99.99% purity copper as a raw material. In particular, the first vapor deposition step and the second vapor deposition step are continuously performed by magnetron sputtering by introducing neon gas as a sputtering gas in the same sputtering apparatus. As described above, the Cu / Cu alloy film including the first conductive layer and the second conductive layer is formed on the TFT substrate 800a. Further, by setting the neon gas pressure to 0.1 Pa to 5 Pa, the second conductive layers 9b and 10b contain 99 atomic% or more of copper and 0.01 atomic% to 1 atomic% of neon. Become. When neon gas is used as the sputtering gas, due to the principle described later, the tensile stress of the deposited film can be reduced as compared with the case of using argon gas, and peeling due to hydrogen plasma treatment is less likely to occur.

  In order to prevent peeling of the drain electrode 9, the video signal line 809 (including the video signal line terminal), and the source electrode 10 during the hydrogen plasma processing described later in FIG. 7B, the second conductive layer 9b contains neon. It is better to increase the amount, but considering the increase in resistivity of the second conductive layer 9b and the stability of sputtering discharge, the neon gas pressure is set to about 0.12 Pa to 0.2 Pa, and the neon content is set from 0.5. It is desirable to be about 1 atomic%.

  In the present embodiment, neon gas is used as the sputtering gas for both the first vapor deposition process and the second vapor deposition process. However, neon may be used for at least one of the sputtering gas for the first vapor deposition process and the second vapor deposition process. . Thereby, the tensile stress generated in the source electrode 10 and the drain electrode 9 is reduced, and peeling during the hydrogen plasma treatment is suppressed. Further, the sputtering gas introduced in at least one of the first vapor deposition step and the second vapor deposition step may be an inert gas containing neon, or may be an inert gas in which argon and neon are mixed. Even in the case of an inert gas in which argon and neon are mixed, peeling during the hydrogen plasma treatment is suppressed according to the mixing ratio. The film thickness of the first conductive layers 9a and 10a is about 10 nm to 100 nm, preferably about 20 nm to 50 nm. The film thickness of the second conductive layers 9b and 10b is about 100 nm to 1000 nm, preferably about 200 nm to 500 nm.

  The additive element of the copper alloy in the first conductive layers 9a and 10a can be selected from aluminum, beryllium, calcium, gallium, magnesium, titanium, vanadium, and zinc in addition to manganese in the present embodiment. Of these, manganese and magnesium are preferable in that there is little fear of leaving an etching residue in the channel portion 12, and the drain electrode 9 and the video signal line 809 (video signal line) during the hydrogen plasma processing described later with reference to FIG. 7B. In order to prevent peeling of the source electrode 10 and the source electrode 10 more reliably, manganese is optimal. One kind or two or more kinds of additive elements may be used.

  In the third photolithography step shown in FIG. 6B, a resist pattern is formed using a binary exposure mask in S302. Thereafter, in S303, the second conductive layer and the first conductive layer are selectively removed by etching. Further, the second semiconductor layer 7 is selectively removed by etching (S304), and the resist is peeled off (S305). Through S301 to S305, the drain electrode 9, the video signal line 809 (including the video signal line terminal), and the source electrode 10 are formed, and the channel portion 12 of the thin film transistor is exposed on the TFT substrate 800a.

  FIG. 7A is a diagram illustrating a state of the TFT substrate 800a in the fourth photolithography process, and FIG. 7B is a flowchart of the fourth photolithography process. As shown in FIG. 7A, in the fourth lithography process, a protective insulating film 11 is formed so as to cover the channel portion 12, the drain electrode 9, and the source electrode 10 of the first semiconductor layer 6, and further, through holes are formed. 14 is opened. In addition, oxide layers 9c and 10c are formed at the interface between the second semiconductor layer 7 and the first conductive layers 9a and 10a.

  In the fourth photolithography process shown in FIG. 7B, in particular in S401, a hydrogen plasma process is performed as a hydrogen termination process on the surface of the first semiconductor layer 6 of the channel portion 12 (hydrogen termination process). The hydrogen plasma treatment in this embodiment is performed in a state where the source electrode 10 and the drain electrode 9 are exposed on the TFT substrate 800a. As described above with reference to FIG. 6B, in the third photolithography process, the drain electrode 9, the video signal line 809 (including the video signal line terminal), and the source electrode 10 are formed using a sputtering gas containing neon. These peelings due to hydrogen plasma treatment can be suppressed. Subsequently, in S402, a protective insulating film 11 made of silicon nitride is formed by plasma chemical vapor deposition. Further, the temperature of the hydrogen plasma treatment in S401 and the formation of the protective insulating film 11 in S402 is about 230 ° C. At this time, the second semiconductor layer 7 (S205) pre-oxidized in the second photolithography step and the first semiconductor layer 7 are used. An oxidation reaction of the additive element of the first conductive layer 9a occurs at the interface with the conductive layer 9a, and a thin oxide is generated. The oxide layers 9c and 10c serve as barrier layers that block diffusion of copper contained in the first conductive layer 9a and the second conductive layer 9b into the second semiconductor layer 7 and the first semiconductor layer 6. Or, it functions as an adhesion layer. Thereafter, a resist pattern using a binary exposure mask is formed (S403), and a through hole 14 is opened in the protective insulating film 11 on the source electrode 10. At the same time, a through hole (not shown) is opened in the protective insulating film 11 on the video signal line terminal, and a through hole (not shown) is formed in the protective insulating film 11 and the gate insulating film 5 on the scanning signal line terminal. Is opened (S404). In step S405, the resist is removed.

  FIG. 8A is a diagram illustrating a state of the TFT substrate 800a in the fifth photolithography process, and FIG. 8B is a flowchart of the fifth photolithography process. As shown in FIG. 8A, in the fifth lithography process, the pixel electrode 15 connected to the source electrode 10 through the through hole 14 is formed.

  As shown in the fifth photolithography step of FIG. 8B, first, in S501, a transparent conductive film made of indium tin oxide is formed by sputtering. Next, a resist pattern using a binary exposure mask is formed (S502). Thereafter, the transparent conductive film is selectively etched away except for the pattern portions of the pixel electrode 15, the scanning signal line terminal (not shown), the common signal line terminal (not shown), and the video signal line terminal (not shown). (S503). Then, the resist is peeled off (S504). The TFT substrate 800a is formed including the steps as described above.

  In the present embodiment, the drain electrode 9 and the source electrode 10 have a two-layer structure of the first conductive layer and the second conductive layer as described above. For example, a two-layer structure of copper and molybdenum ( Cu / Mo) or a single layer structure of copper. In the case of a two-layer structure, the films may be continuously formed in the same chamber, or may be formed separately using different sputtering apparatuses. Further, the drain electrode 9 and the source electrode 10 may be composed of three or more conductive layers. Note that in the case of a single layer structure made of high-purity copper, the adhesion to the base is weaker than in the case of the present embodiment, and copper diffuses into the second semiconductor layer 7 to deteriorate transistor characteristics. It becomes easy.

  When the drain electrode 9 and the source electrode 10 have a two-layer structure (Cu / Mo) of copper and molybdenum, the lower molybdenum is responsible for securing adhesion with the base, and copper is formed on the second semiconductor layer 7. It also serves as a diffusion barrier that prevents diffusion. However, in order to process this Cu / Mo, a wet etching solution using unstable hydrogen peroxide as an oxidizing agent must be used. In order to maintain the performance, it is necessary to keep the liquid composition substantially constant. To that end, it is necessary to increase the renewal frequency of the etching liquid. This leads to an increase in the amount of liquid used, which in turn is a high cost factor. In addition, the use of expensive molybdenum for the barrier film is also a high cost factor. Therefore, the two-layer structure of the first conductive layers 9a and 10a and the second conductive layers 9b and 10b as in the present embodiment is more preferable than the drain electrode 9 and the source electrode 10 having a two-layer structure of copper and molybdenum. It is desirable to do. This is because the problem of the wet etching solution can be avoided without using expensive molybdenum.

  The film stress of the Cu / Mo film sputtered using argon gas as the sputtering gas was compared with the film stress of the Cu / Mo film sputtered using neon as the sputtering gas. Each Cu / Mo film was formed with a film thickness of 300 nm / 20 nm. This is because when the Mo film is employed as the lower layer, the Mo film functions as an adhesion layer, so that even when the Cu layer is subjected to high stress, the film is difficult to peel off and the film stress can be easily measured. As a result, the tensile stress was about 150 MPa when argon gas was used as the sputtering gas, whereas the compressive stress was about 150 MPa (that is, about −150 MPa tensile stress) when neon gas was used. Further, when these Cu / Mo films were subjected to hydrogen plasma treatment, the stress of the film using argon gas as the sputtering gas was about 700 MPa, whereas the neon gas was about 400 MPa.

  A Cu / Cu alloy film sputtered using argon gas as a sputtering gas and a Cu / Cu alloy film sputtered using neon as a sputtering gas were prepared, and the presence or absence of peeling due to hydrogen plasma treatment was examined. Each Cu / Cu alloy film was formed with a film thickness of 300 nm / 20 nm. As a result, peeling occurred in the film using argon gas as the sputtering gas, but peeling did not occur in the case of neon gas. Further, when the neon element in the Cu film using this neon gas as the sputtering gas was quantitatively analyzed, about 1 atomic% when the sputtering gas pressure was 0.12 Pa, about 0.01 atomic% neon when the sputtering gas pressure was 5 Pa in the Cu film. It was taken in. Therefore, neon is inevitably taken into the Cu film when the sputtering gas is neon. And it is thought that Cu film | membrane containing neon showed the property of the low tensile stress and by extension, the peeling tolerance with respect to the hydrogen plasma process was provided. Such an effect is manifested in accordance with the mixing ratio even when the sputtering gas is a mixed gas of argon and neon.

  Note that the efficiency with which copper is ejected from the surface of the sputtering target is reduced by using a neon gas having a molecular weight lower than that of the argon gas as the sputtering gas. However, since the atomic weight of neon is lower than the atomic weight of argon, the copper ejected from the surface of the target is less likely to be scattered while being deposited on the TFT substrate 800a, and is attached to the substrate with a high momentum. It is thought that. Based on such a principle, it is considered that the case where neon gas is used as the sputtering gas exhibits a lower tensile stress of the formed Cu film than the case where argon gas is used. Further, even if a Cu film or a Cu alloy film formed by introducing neon gas according to a principle different from the above principle exhibits a low tensile stress, it is within the scope of the present invention.

In the present embodiment, aluminum or copper may be used for the wiring layers 2b and 3b in the first lithography process. Like the drain electrode 9 and the source electrode 10 in the third lithography step, the wiring layers 2b and 3b have a first conductive layer containing a copper alloy containing copper as a main component and a higher purity than the copper alloy. More preferably, the second conductive layer containing copper is formed. Specifically, the wiring layers 2b and 3b are formed by sputtering a first conductive layer made of 99.99% purity copper using a sputtering target made of an alloy containing 4 atomic% manganese and containing copper as a main component. A second conductive layer is continuously formed by magnetron sputtering using a target as a raw material. The sputtering gas may be neon gas, argon gas, or a mixed gas of argon and neon. The film thickness of the first conductive layer is about 10 nm to 100 nm, and preferably about 20 nm to 50 nm. The film thickness of the second conductive layer is about 100 nm to 1000 nm, preferably about 200 nm to 500 nm. In addition to manganese, the additive element of the copper alloy that is the sputtering target for forming the first conductive layer can be selected from aluminum, beryllium, calcium, gallium, magnesium, titanium, vanadium, and zinc. However, it is preferable to use the same material as that of the first conductive layer of the video signal line, the source electrode, and the drain electrode formed in the third photolithography process because the material procurement becomes efficient. Further, the deposition temperature of the gate insulating film 5 in S201 of the second lithography process is about 300 ° C. At this time, a metal is formed at the interface between the transparent conductive film formed in the first photolithography process and the first conductive layer. An oxide layer (in this case, a manganese oxide layer) is formed, which functions as an adhesion layer.

Note that, as described above, the display device according to the present embodiment has an in-plane switching (In
Although it is a plane switching (LCD) liquid crystal display device, it may be a liquid crystal display device of another method such as a TN (Twisted Nematic) method or a VA (Vertical Alignment) method. The display device according to the present embodiment is a liquid crystal display device, but may be another display device such as an organic EL (Electro-Luminescence) display device.

  1 glass substrate, 2 gate electrode, 2a, 3a transparent conductive film, 2b, 3b wiring layer, 5 gate insulating film, 6 first semiconductor layer, 7 second semiconductor layer, 9 drain electrode, 10 source electrode, 9a, 10a first 1 conductive layer, 9b, 10b 2nd conductive layer, 9c, 10c oxide layer, 11 protective insulating film, 12 channel portion, 14 through hole, 15 pixel electrode, 16 liquid crystal, 17 glass substrate, 18 alignment film, 19 Black matrix, 21 Flattening film, 22 Polarizing plate, 23 Color filter, 700 Liquid crystal display device, 710 Upper frame, 720 Lower frame, 800 Liquid crystal panel, 800a TFT substrate, 800b Counter substrate, 802 Scanning signal line, 809 Video signal line 810 pixel region, 830, 840 drive circuit.

Claims (8)

In a method for manufacturing a display device having a substrate on which a plurality of thin film transistors are arranged,
An electrode forming step of forming a source electrode and a drain electrode including a single layer or a plurality of conductive layers on a part of the semiconductor layer of the thin film transistor;
A hydrogen termination step of subjecting the semiconductor layer to a hydrogen termination process in a state where the source electrode and the drain electrode are exposed on the substrate,
The electrode forming step includes a step of depositing copper on the substrate by introducing an inert gas containing neon.
A manufacturing method of a display device, In the manufacturing method of the display device according to claim 1,
The electrode forming step includes
A first vapor deposition step of depositing a copper alloy on the substrate;
A second vapor deposition step of depositing copper on the substrate after the first vapor deposition step;
In at least one of the first vapor deposition step and the second vapor deposition step, an inert gas containing neon is introduced.
A manufacturing method of a display device, In the manufacturing method of the display device according to claim 2,
The sputtering target in the first vapor deposition step is a copper alloy containing copper as a main component and containing at least one additive element,
The sputtering target in the second vapor deposition step is copper having a purity higher than that of the copper alloy.
A manufacturing method of a display device, In the manufacturing method of the display device according to claim 3,
The sputtering target in the first vapor deposition step is a copper alloy containing copper as a main component and containing at least one additional element that is 0.5 atomic% or more and 20 atomic% or less,
The sputtering target in the second vapor deposition step is copper having a purity of 99.5 atomic% or more.
A manufacturing method of a display device, A display device having a substrate on which a plurality of thin film transistors are arranged,
The thin film transistor has a semiconductor layer and a source electrode and a drain electrode configured by laminating a plurality of layers or a single conductive layer on a part of the semiconductor layer,
The source electrode and the drain electrode have at least one conductive layer containing copper and neon,
A display device characterized by that. The display device according to claim 5,
The source electrode and the drain electrode have a first conductive layer containing a copper alloy containing copper as a main component and at least one additional element, and a higher side of the first conductive layer than the copper alloy. A second conductive layer containing copper that is pure,
At least one of the first conductive layer and the second conductive layer contains neon;
A display device characterized by that. The display device according to claim 6,
The second conductive layer contains 99 atomic% or more of copper and 0.01 atomic% or more and 1 atomic% or less of neon.
A display device characterized by that. The display device according to claim 5,
The source electrode and the drain electrode are
A first conductive layer deposited by introducing an inert gas containing neon or argon using a copper alloy containing at least one additive element as a sputtering target;
A copper layer having a higher purity than the copper alloy as a sputtering target, and a second conductive layer deposited by introducing an inert gas containing neon,
A display device characterized by that.

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