JP5308760B2 - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display of low cost and high picture quality, in which a stagger type polycrystal Si-TFT structure with good characteristic is compatible with a low resistance wiring structure which is advantageous to a larger display. <P>SOLUTION: A TFT driving a plurality of pixels arranged in matrix is configured as a stagger type polycrystal Si-TFT. An electrode wiring 2 positioned at a layer lower than a polycrystal Si layer 4 which forms a channel of the TFT has a lamination structure including the first alloy layer 2a consisting of an Al alloy containing rare earth element as an additive element and the second alloy layer 2b which is made of an alloy of rare earth element, high melting-point metal, and Al and is positioned at a layer higher than the first layer. Thus, a low resistance wiring configuration is provided which resists a high temperature at the time of forming polycrystal Si. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a display device such as an organic light emitting display device or a liquid crystal display device.

  As a thin film transistor applicable to a display device such as an organic light emitting display device or a liquid crystal display device, there is a thin film transistor (TFT) using a semiconductor layer made of polycrystalline silicon (also expressed as polycrystalline Si or p-Si).

  As an example, in an active matrix organic light emitting display device, a switching element composed of a plurality of TFTs and a driving element composed of a capacitor are connected to an organic light emitting element that constitutes each pixel. It is a configuration that can be fully lit. It is considered that an active matrix organic light emitting display device is advantageous for high definition and large screen because the lifetime of the organic light emitting element is increased without increasing the luminance.

  TFTs that drive organic light emitting elements are required to have high mobility and low threshold (Vth) shift characteristics. Usually, instead of a staggered amorphous Si-TFT used for a liquid crystal display device or the like, a coplanar TFT in which polycrystalline Si having good characteristics is applied to a semiconductor layer is used.

  Formation of a polycrystalline Si film usually requires a high-temperature film formation at a temperature higher than the thermal decomposition temperature of the source gas and about 600 ° C., or a high-temperature heat treatment process. However, in order to apply to a large-area display device or the like, since the display device or the like uses an inexpensive glass substrate having a low softening temperature, the polycrystalline Si film needs to be formed at a low temperature of 500 ° C. or lower. .

As a method for forming a polycrystalline Si film at a low temperature, for example, a plasma CVD method using SiH ₄ or SiF ₄ diluted with hydrogen (H ₂ ) as a source gas, or heat using a compound containing hydrogen and a compound containing halogen. A CVD (hereinafter referred to as reactive thermal CVD) method (Non-Patent Document 1) has been proposed.

  In addition, as a low resistance metal wiring material, Cu adhesion, oxidation resistance, workability and corrosion resistance are ensured, and the reaction with Si that is a constituent material of a semiconductor layer or an insulating film is suppressed, so that Cu is Cu. It is more desirable if Al, which is more versatile than can be used. When Al is used as a wiring material, since the thermal expansion coefficient of Al is larger than that of an insulating substrate such as glass, it elastically changes from tensile stress to compressive stress during heat treatment. When this compressive stress exceeds the yield stress of the Al thin film, stress relaxation occurs due to plastic deformation, and a projection called hillock is formed. On the other hand, when it cools, it changes to the tensile stress side to form a defective portion called a void, which causes wiring short-circuiting or disconnection. Non-patent documents 2 and 3 are techniques for suppressing the formation of hillocks and voids in an Al alloy.

  In addition, laser annealing is applied as a method for forming a high-quality polycrystalline Si film at a low temperature, and the wiring portion has a clad laminated wiring structure composed of an electrode made of a high heat-resistant metal and a main wiring portion made of a low-resistance metal. Patent Document 1 proposes a method for avoiding thermal damage of wiring by selectively irradiating a laser while avoiding the portion.

JP 2007-35963 A J.Vac.Soc.Jpn. (Vacuum), Vol.47, No.9, p.702-711 (2004) J. Vac. Sci. Technol. B, Vol. 14, No. 5, p. 3257-3262 (1996) J.Vac.Sci.Technol.A, Vol.15, No.4, p.2339-2348 (1997)

  In the case of a coplanar type TFT structure used for polycrystalline Si, the characteristics can be easily secured as compared with a stagger type TFT, but the number of processes increases because the structure becomes complicated. In addition, the manufacturing requires a specific process such as selective doping of impurities into the channel junction and a specific manufacturing facility such as an ion implantation apparatus, which is a significant disadvantage in terms of cost. The process temperature is high, such as the impurity activation step. Although it is desirable in terms of cost if a staggered polycrystalline Si TFT structure can be realized, there are the following problems to be solved in practical use.

  A staggered TFT has a structure in which either the gate electrode or the source / drain electrode of the TFT is disposed below the semiconductor layer forming the channel in principle. Specifically, in the case of an inverted stagger TFT structure, the gate electrode is disposed below the semiconductor layer in the case of a normal stagger TFT structure.

  Therefore, it is necessary for the electrode or wiring arranged in the lower layer to be resistant to wiring short-circuiting or disconnection due to generation of hillocks or voids due to heat treatment, contact failure due to thermal diffusion, etc., and low resistance such as commonly used Al or Cu There was a limit to wiring materials and structures, such as the use of refractory metal materials instead of metals. Although it is possible to reduce resistance by increasing the thickness of the wiring, it is difficult to control the forward taper processing of the thick film wiring. Since it becomes difficult to ensure, a short circuit at the wiring intersection and a disconnection failure of the wiring arranged in the upper layer are caused, and there is a limit to increasing the film thickness. For this reason, it is necessary to consider signal delay due to wiring resistance, and there is a limit to enlargement of the display.

  Even according to the low-temperature formation process as described in Non-Patent Document 1, the formation of polycrystalline Si still requires a high temperature of 400 ° C. or higher.

  In addition, since the alloy precipitation reactions described in Non-Patent Documents 2 and 3 are all completed within a temperature range of 200 to 350 ° C., it is difficult to apply to applications that require heat resistance of 400 ° C. or higher. It was. Moreover, since the addition of these impurities causes an increase in specific resistance, the amount of addition is limited, and it is difficult to achieve both low resistance and heat resistance.

  In the case of Patent Document 1, since there is a limit to the area that can be crystallized at a time by laser irradiation, it is difficult to form a uniform polycrystalline Si film over a large area, which increases the size of the display. Is still limited. In addition, since a new laser annealing process is required, and it is necessary to perform a patterning process by photolithography more than usual for forming the laminated wiring, the process cost becomes high.

  The object of the present invention is to achieve both a staggered TFT structure having good characteristics and a low-resistance wiring structure that is advantageous for increasing the size of the display without increasing the number of steps and processes. It is to provide an advantageous display device.

  In view of the above problems, the present invention is a display device having a plurality of pixels arranged in a matrix and a TFT for driving the pixel, and the TFT is formed on a gate electrode, an insulating film, and a semiconductor layer on an insulating substrate. , An inverted stagger type TFT in which a source electrode and a drain electrode are arranged in this order. The TFT has a gate wiring connected to the gate electrode and a drain wiring connected to the source electrode and the drain electrode. The gate wiring is disposed closer to the insulating substrate than the semiconductor layer, and the gate electrode and the gate wiring are made of an Al alloy containing at least one of rare earth elements as an additive element in order from the insulating substrate side. And a second alloy layer made of an alloy of at least one of rare earth elements and at least one of refractory metals and Al.

  The display device includes a plurality of pixels arranged in a matrix and a TFT for driving the pixel. The TFT includes a source electrode, a drain electrode, an insulating film, a semiconductor layer, and a gate electrode on an insulating substrate. This is a positive stagger type TFT arranged in this order. The TFT has a gate wiring connected to the gate electrode and a drain wiring connected to the source electrode and the drain electrode. The source electrode, the drain electrode, and the drain wiring are The first alloy is arranged on the insulating substrate side of the semiconductor layer, and the source electrode, the drain electrode, and the drain wiring are made of an Al alloy containing at least one of rare earth elements as an additive element in order from the insulating substrate side. A second alloy layer comprising an alloy of at least one of the rare earth elements and at least one of the refractory metals and Al. And configuration.

  Provides a staggered TFT structure with good characteristics and a low-resistance wiring structure that is advantageous for increasing the size of the display without increasing the number of processes and processes, providing a display device that is advantageous in terms of cost and performance it can.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS The best mode for carrying out the present invention will be described below in detail with reference to the drawings.

  FIG. 1 is a cross-sectional view of a main part for explaining an application example to a reverse stagger type TFT as a stagger type TFT constituting a pixel of a display device which is Embodiment 1 of the present invention.

  In the case of an inverted staggered TFT, an electrode and a wiring to which the present invention is applied are a gate electrode and a gate wiring that are disposed below a channel semiconductor layer that requires high temperature formation.

  The present embodiment is a display device having a plurality of pixels arranged in a matrix and a TFT for driving the pixel, and the TFT is formed on a gate electrode, an insulating film, a semiconductor layer, and a source electrode on an insulating substrate. And a reverse stagger type TFT in which the drain electrodes are arranged in this order. The TFT has a gate wiring connected to the gate electrode and a drain wiring connected to the source electrode and the drain electrode. The gate electrode and the gate wiring are In this structure, the TFT is disposed closer to the insulating substrate than the semiconductor layer of the TFT.

  First, a first alloy layer 2a made of an Al alloy layer that plays a role of a low resistance layer, in order from the insulating substrate 1 side, on the insulating substrate 1 suitable for a glass substrate, and the first alloy layer The second alloy layer 2b located on the upper layer and serving as a hillock / void suppression layer was continuously formed to form a laminated film serving as the gate electrode wiring 2 of this example. In the present invention, the first alloy layer 2a includes, as rare earth elements, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. Is formed of an Al alloy containing at least one of the above as an additive element, and includes at least one of the rare earth elements described above and Mo, Ti, Zr, Hf, V, Nb, Ta, Cr, W as the refractory metal. Each of them is made of an alloy with Al containing at least one of the above. Any of the above alloy films can be formed by a sputtering method using an alloy target having these compositions. Since the rare earth element has a small solid solubility limit with respect to Al, an alloy is easily formed by precipitation, and movement of Al atoms is easily inhibited by precipitation hardening of the alloy.

  Moreover, it is also possible to set it as the structure containing at least one of Si, Cu, Mg, and Ni as additive elements other than the said rare earth elements. In the above structure, since it is not necessary to consider thermal damage of the wiring for the semiconductor layer, a film including a Si or SiGe polycrystalline film that needs to be formed at a high temperature can be used. As the semiconductor layer, for example, a polycrystalline film formed by a thermal CVD method using a compound containing hydrogen and a compound containing halogen can be used.

  In this example, a binary alloy film of Nd and Al was formed as the first alloy layer 2a, and an alloy film of Nd, Mo, and Al was formed as the second alloy layer 2b. The film thickness was 400 nm and 50 nm, respectively.

The melting point of Al is as low as 660 ° C., and this is one reason why the heat resistance of Al is inferior. However, in this example, a high melting point can be expected by alloying a refractory metal with Al, and the Al atoms in the alloy We thought that we could suppress movement of In particular, Mo is advantageous in terms of workability of the laminated wiring described later and fixing of the crystal grain boundaries. An experiment was conducted using the above-described novel multi-element alloy layer made of a rare earth element, a refractory metal and Al as the second alloy layer, and it was found that the heat resistance of the Al alloy wiring can actually be remarkably improved. Compared to the case of laminating refractory metal layers such as Mo, Ti, Cr, etc., which are usually used to improve contact characteristics with upper layer wiring, and also an alloy layer of refractory metal and Al that does not contain rare earth elements Compared with the case of laminating, heat resistance can be remarkably improved, and generation and growth of hillocks and voids can be significantly suppressed even after heat treatment at 450 ° C. As an example of the multi-element alloy of the present invention, when Nd or Ce is used as a rare earth element and Mo is used as a refractory metal, a ternary alloy layer made of Al ₂₀ XMo ₂ (X: rare earth element) can be formed. . Although the alloy composition of MoAl ₁₂ , Mo ₃ Al, etc. is well known for binary alloys with Mo, the heat resistance against hillocks and voids is remarkably higher than when such binary alloy layers are formed. I was able to improve.

  Next, this laminated film was collectively processed into a pattern of the gate electrode wiring 2 by a photolithography method. Since both the first alloy layer 2a and the second alloy layer 2b are composed of an Al alloy layer, batch processing of the laminated film is facilitated, and an increase in the photolithography process can be avoided.

Next, a gate insulating film 3 was formed on the gate electrode wiring 2. As a material of the gate insulating film 3, it is possible to use SiO ₂ or SiN. These insulating films can be formed by PECVD or sputtering. Alternatively, plasma oxidation, photooxidation, or the like may be used in combination. In this example, a SiO ₂ film formed by a plasma CVD method using TEOS was used. The film thickness was 300 nm.

Next, a polycrystalline film was formed as a semiconductor layer 4 on the gate insulating film 3 by a thermal CVD method capable of obtaining good crystallinity at a high temperature of 400 ° C. or higher. Specifically, a polycrystalline SiGe film was formed under the conditions of a substrate temperature of 450 ° C. using GeF ₄ , F ₂ , Si ₂ H ₆ as a reactive gas and He as a diluent gas. The film thickness was 200 nm. In this embodiment, a combination of GeF ₄ and Si ₂ H ₆ is used as a reactive gas. However, for example, by using F ₂ instead of GeF ₄ , a polycrystalline Si film can be formed. Moreover, it is also possible to use a plasma CVD method instead of the thermal CVD method.

  Next, p + Si films to be the doped layers 5 and 6 as contact layers were formed by a plasma CVD method. The film thickness was 40 nm. Incidentally, the polarity of the doped layers 5 and 6 is not limited to the n + Si film, and can be arbitrarily changed to a p + Si film depending on the TFT configuration of the pixel circuit. Thereafter, the n + Si film as the doped layers 5 and 6 and the laminated film of the semiconductor layer 4 were processed into an island shape by using a photolithography method.

  Next, a source electrode wiring 7 and a drain electrode wiring 8 were formed thereon. As materials for the source electrode wiring 7 and the drain electrode wiring 8, metals such as Nb, Mo, W, Ta, Cr, Ti, Fe, Ni, Co, and alloys thereof, and laminated films thereof can be used. Furthermore, since it is a step after the formation of a semiconductor layer that requires a high temperature, the upper limit temperature of the process can be lowered. Therefore, it is possible to use a low resistance metal such as Al or Cu. These films were formed by a sputtering method. In this example, a Ti / AlSi alloy / Ti laminated film was used in consideration of the compatibility with the contact characteristics, and the film thickness was 50/300/50 nm. Subsequently, the pattern of the source electrode wiring 7 and the drain electrode wiring 8 was processed using the photolithography method. Next, the n + Si film on the channel region 9 was etched using the source electrode wiring 7 and the drain electrode wiring 8 as a mask to form contact layers (dope layers 5 and 6).

  Next, a SiN film was formed as a protective insulating film 10 on the source electrode wiring 7 and the drain electrode wiring 8 by a plasma CVD method. The film thickness was 500 nm. Next, a through hole 11 was formed in the protective insulating film 10 using a photolithography method.

  Finally, a reflective metal film or a transparent conductive film was formed as the electrode material of the pixel electrode 12. In this embodiment, an ITO film, which is a transparent conductive film, is formed as the pixel electrode 12 by a sputtering method and processed using a photolithography method. The film thickness was 70 nm.

  Further, in this embodiment, the required film thickness of the second alloy layer can be reduced as much as the hillock and void suppressing ability of the second alloy layer can be increased. The film thickness of the second alloy layer is desirably 5 to 200 nm, more desirably 10 to 100 nm. As a result, the step generated by the electrode and wiring pattern can be reduced, so that the insulating film and wiring formed on the electrode and wiring, specifically, the gate insulating film and semiconductor layer of the TFT, and further the drain wiring located in the upper layer (In the case of the positive stagger TFT of FIG. 5, the gate wiring) can be secured, and a short circuit and disconnection due to a step can be suppressed. In addition, it becomes easy to secure the forward tapered shape of the electrode and the wiring pattern by thinning the film.

  In the present embodiment, the alloy laminated structure of the present invention excellent in heat resistance of hillocks and voids is applied to the gate electrode wiring 2 of the inverted stagger type TFT disposed below the semiconductor layer 4, that is, the first An electrode of Al atoms in the first alloy layer that causes hillocks and voids by forming a second alloy layer composed of a rare earth element, a refractory metal, and Al continuously on the upper layer of the alloy layer. As compared with the case where the first alloy layer containing only rare earth elements is used as a single layer, the generation of hillocks and voids caused by heat treatment and its growth can be greatly restricted. Can be greatly suppressed. Accordingly, the concentration of the rare earth added element in the first alloy layer, which becomes a resistance increasing factor, can be greatly reduced, and it is easy to secure low resistance.

  As described above, it is possible to use an Al alloy wiring material whose use is limited in a normal polycrystalline Si TFT process. Further, since the wiring resistance can be significantly reduced by applying the low resistance Al, the display device can be easily enlarged without considering the signal delay due to the wiring resistance. Further, since a polycrystalline film having good characteristics can be used for the semiconductor layer 4, a staggered TFT having high characteristics with high mobility and a small threshold (Vth) shift can be obtained. A display device advantageous in terms of cost and performance can be provided.

Further, by using the second multi-component alloy layer containing a refractory metal as an upper layer, the oxidation resistance of the electrode and the wiring surface can be improved as compared with the case where the first alloy layer is used as a single layer. Therefore, it is easy to secure the contact characteristics at the connection portion with the upper layer electrode such as the pixel electrode, the circuit connection portion with the upper layer wiring, or the terminal connection portion. In actual connection with an upper layer electrode or wiring, a wet etching method using a hydrofluoric acid-based etching solution or an fluorine film is used for an interlayer insulating film made of SiO ₂ or SiN formed on the TFT electrode and wiring. Although it is necessary to open through-holes by dry etching using a system gas, the use of the second multi-component alloy layer containing Al as an upper layer makes it easy to improve resistance to these through-hole opening processes. .

  FIG. 2 is a cross-sectional view of a main part for explaining an application example to a reverse stagger type TFT as a stagger type TFT constituting a pixel of a display device that is Embodiment 2 of the present invention.

  The difference from Example 1 is that in the configuration of Example 1, a third alloy layer 2c made of a refractory metal or an alloy of a refractory metal is provided on the first and second alloy layers. This is the point that the layered gate electrode wiring 2 is formed. That is, the gate electrode and the gate wiring are stacked on the opposite side of the second alloy layer 2b from the side on which the first alloy layer 2a is disposed, and are formed of at least one of the refractory metals. This is a point having three alloy layers 2c.

  In the three-layer laminated wiring configuration of the second embodiment, the second alloy layer 2b made of a rare earth additive element, a refractory metal, and Al can be formed by the same method as that of the first embodiment. However, after the third alloy layer 2c is laminated on the first alloy layer 2a, a heat treatment step is provided, and Al and rare earth elements contained in the first alloy layer 2a are contained in the third alloy layer 2c. As a result of the interfacial interaction with the refractory metal, the second alloy layer 2b can be formed.

  First, a first alloy layer 2a made of an Al alloy layer that plays a role of a low resistance layer, in order from the insulating substrate 1 side, on the insulating substrate 1 suitable for a glass substrate, and the first alloy layer A third alloy layer 2c serving as a refractory metal supply layer for forming the second alloy layer 2b serving as a hillock / void suppressing layer was continuously formed. In the present invention, the first alloy layer 2a includes, as rare earth elements, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. The third alloy layer 2c is made of at least one of Mo, Ti, Zr, Hf, V, Nb, Ta, Cr, and W as a refractory metal, or It is an alloy of these metals, and more desirably, Mo or an alloy film with Mo is formed. Any of the above alloy films can be formed by a sputtering method using an alloy target having these compositions. In this example, a binary alloy of Nd and Al was formed as an alloy layer that is the basis of the first alloy layer 2a, and a Mo film was formed as the third alloy layer 2c. The film thickness was 450 nm and 100 nm, respectively. Next, this laminated film was collectively processed into a pattern of the gate electrode wiring 2 by using a photolithography method.

  Next, heat treatment is performed at 450 ° C. in a vacuum, so that a first interface between Nd, Mo, and Al is applied to the stacked interface between the first alloy layer 2a and the third alloy layer 2c using an interfacial interaction. A second alloy layer 2b was formed. The film thickness of the second alloy layer 2b is 50 nm, and the film thickness of the first Al alloy layer 2a that contributes to low resistance is formed in advance by the thickness of the second alloy layer 2b. , Ensure wiring resistance.

  Next, a gate insulating film 3 was formed on the gate electrode wiring 2. In the subsequent steps, an inverted staggered TFT having the gate electrode wiring 2 and the semiconductor layer 4 of the present invention was formed in the same manner as in Example 1.

  In the second embodiment, the heat treatment process necessary for forming the second alloy layer 2b can be used as it is in the polycrystalline Si film forming process requiring high heat resistance. In this case, since heat resistance can be ensured at the same time, it is possible to avoid an extra increase in the heat treatment step. In addition, if a heat treatment step of 400 ° C. or higher can be secured, it is of course possible to also use the gate insulating film 3 formation step.

  FIG. 8 is an example of formation of the second alloy layer 2b obtained by experiments by the present inventors in Example 2. This is a case where Nd is used as the rare earth element and Mo is used as the refractory metal, and a ternary alloy of Nd, Mo and Al is formed as the second alloy layer 2b. The vertical axis represents the formed film thickness of the second alloy layer 2b, and the horizontal axis represents the heat treatment temperature. It can be seen that the second alloy layer 2b can be formed with good controllability by heat treatment at 400 ° C. or higher.

  FIG. 9 is an example of forming the second alloy layer 2b in Example 2 when Ce is used as the rare earth element and Mo is used as the refractory metal. In this case, a ternary alloy of Ce, Mo, and Al is formed as the second alloy layer 2b. As in the case of FIG. 8 described above, it can be seen that the second alloy layer 2b can be formed with good controllability by heat treatment at 400 ° C. or higher.

  In the above-described embodiment, the case where Nd and Ce are used as the rare earth element has been described. However, instead of Nd and Ce, Sc, Y, La, Pr, Sm, Eu, Gd, Tb, Dy, Ho, Er , Tm, Yb, and Lu can be used. In the above-described embodiments, the case where Mo is used as the refractory metal has been described, but it is of course possible to use Ti, Zr, Hf, V, Nb, Ta, Cr, W instead of Mo.

  In the above-described embodiment, the second alloy layer 2b can be continuously formed by interfacial interaction, so that the movement of Al atoms in the first alloy layer 2a can be more restricted. Further, since the second alloy layer 2b is uniformly formed in the film thickness direction, local stress concentration and stress relaxation on the first alloy layer 2a and the second alloy layer 2b are performed. , And the generation and growth of hillocks and voids can be greatly suppressed.

  As described above, in the three-layer laminated wiring structure, the second alloy layer composed of the rare earth additive element, the refractory metal, and Al is subjected to the heat treatment step after the third alloy layer is laminated on the first alloy layer. The second alloy layer can be formed as a result of the interfacial interaction between the Al and rare earth elements contained in the first alloy layer and the refractory metal contained in the third alloy layer.

  According to the examination results of the present inventors, the onset temperature of the interfacial reaction was 400 ° C. or higher. As a result, the heat treatment step necessary for forming the second alloy layer can be used as it is in the polycrystalline Si film forming step requiring high heat resistance as it is, and the heat increase can be ensured at the same time. Can also be avoided. In this case, the kind of rare earth additive elements contained in the first alloy layer and the second alloy layer is the same.

  In addition, as a result of the interfacial interaction, a loss occurs for the film thickness of the first Al alloy layer that contributes to low resistance by an amount corresponding to the interface reaction. Can also be avoided.

  On the other hand, since it is consumed in the formation and precipitation reaction of the second alloy layer, the diffusion of the rare earth-added element in the first alloy layer to the interface is promoted. The element concentration can be substantially reduced. Accordingly, the specific resistance of the first alloy layer can be brought close to that of pure Al, and the specific resistance can be reduced. Also in this case, due to the above diffusion promotion, the concentration of the rare earth additive element in the second alloy layer precipitated as a multi-element alloy is higher than the concentration of the rare earth additive element in the Al alloy layer constituting the first alloy layer. .

  In addition, since the second alloy layer is formed as a result of the interfacial interaction between the first alloy layer and the third alloy layer, the connection with the crystal grains and grain boundaries in the first alloy layer is reduced. The second alloy layer can be continuously formed while maintaining the film thickness direction. As a result, the presence of crystal grains in the second alloy layer continuously formed in the film thickness direction can regulate the position of crystal grains and crystal grain boundaries in the first alloy layer. The movement of Al atoms can be more restricted not only in the film thickness direction but also in the in-plane direction, and the growth of voids and hillocks can be suppressed not only on the electrode and wiring surfaces but also on the side surfaces. Further, in the process of forming the second alloy layer by reaction, the film stress applied to the first alloy layer is also relaxed.

  In addition, since the second alloy layer continuously formed as a result of the interfacial interaction is uniformly formed in the film thickness direction so as to cover the entire surface of the first alloy layer, the second and first alloys Local stress concentration in the layer and local stress relaxation in the first alloy layer can be prevented, and movement of Al atoms in the alloy layer can be suppressed uniformly.

  Even when voids are generated and grown in the first alloy, the wiring path is secured in the second alloy layer portion formed uniformly in the film thickness direction on the upper layer, so that disconnection due to voids is prevented. Can be avoided.

  The above-described cross-sectional configuration of the multilayer wiring of the present invention can be examined by evaluating each concentration distribution in the film thickness direction of Al, Mo, and rare earth elements. As the analysis means, for example, a depth direction composition analysis method such as AES (Auger Electron Spectrometer) or SIMS (Secondary ion mass spectrometry) can be used.

  FIG. 10 shows a depth direction AES composition analysis example of the gate electrode wiring film 2 in Example 2 when Nd is used as the rare earth element and Mo is used as the refractory metal. The vertical axis represents the composition ratio of Nd, Mo, Al, and O, which are components of the laminated film and the insulating substrate, and the horizontal axis represents the sputtering time in the film thickness direction. In order from the insulating substrate 1 side, the first alloy layer 2a made of an alloy layer of rare earth and Al, the second alloy layer 2b made of Nd, Mo, Al, and the third alloy layer 2c made of Mo You can see how they are stacked one after another. The main component of the second alloy layer is Al, and the concentration of Nd, which is a rare earth additive element in the second alloy layer, is 2 at% in the first alloy layer. It can be seen that the second alloy layer is as high as 7 at%. This makes it easier to ensure both low resistance, which is the role of the first alloy layer, and hillock and void suppression, which are the roles of the second alloy layer. From the viewpoint of coexistence of the above characteristics, the rare earth additive element concentration in the second alloy layer of the present invention is desirably 1 to 10 at%, more desirably 2 to 7 at%. Moreover, the rare earth additive element concentration in the first Al alloy layer is preferably from 0.01 to 3 at%, more preferably from 0.05 to 2 at%.

  FIG. 3 is a cross-sectional view of an essential part for explaining an application example to a reverse stagger type TFT as a stagger type TFT constituting a pixel of a display device which is Embodiment 3 of the present invention.

  The difference from Example 2 is that in the configuration of Example 2, a four-layer laminate in which a fourth alloy layer 2d made of an alloy of a rare earth element, a refractory metal and Al is provided below the first alloy layer. The gate electrode wiring 2 is used. That is, the gate electrode and the gate wiring are stacked on the opposite side of the first alloy layer from the side on which the second alloy layer is disposed, and at least one of the rare earth elements and the refractory metal This is a point having a fourth alloy layer 2d made of an alloy of at least one and Al.

  Because of the presence of the fourth alloy layer 2d, the movement of Al atoms in the first alloy layer 2a to the electrode and wiring surface and side surfaces can be restricted from the lower interface side of the first alloy layer 2a. As compared with the case where the second and third alloy layers 2b and 2c are laminated on the upper layer, generation of hillocks and voids can be further suppressed. The fourth alloy layer 2d can be formed by the same method as the second alloy layer 2b of the first embodiment.

  FIG. 4 is a cross-sectional view of an essential part for explaining an application example to a reverse stagger type TFT as a stagger type TFT constituting a pixel of a display device which is Embodiment 4 of the present invention.

  The difference from Example 3 is that in the configuration of Example 3, a five-layer laminated structure in which a fifth alloy layer 2e made of a refractory metal or an alloy of a refractory metal is provided in the lower layer of the fourth alloy layer. This is the gate electrode wiring 2. In other words, the gate electrode and the gate wiring are stacked on the side opposite to the side on which the first alloy layer is disposed with respect to the fourth alloy layer, and the fifth electrode made of at least one of the refractory metals. This is a point having an alloy layer of

  In the present embodiment, the fourth alloy layer 2d made of the rare earth additive element, the refractory metal, and Al can of course be formed by the same method as in the first embodiment. Similar to the layered wiring structure, a heat treatment step is provided after the fifth alloy layer 2e is laminated on the first alloy layer 2a, and the Al and rare earth elements contained in the first alloy layer 2a, the fifth As a result of the interfacial interaction with the refractory metal contained in the alloy layer 2e, the fourth alloy layer 2d can be formed.

  According to the formation by the interfacial interaction, the fourth alloy layer is continuously formed in a state where the connection with the crystal grains and crystal grain boundaries in the first alloy layer is maintained in the film thickness direction. The positions of crystal grains and crystal grain boundaries in the alloy layer can also be regulated from the lower layer interface side. Thereby, the movement of Al atoms in the first alloy layer can be further restricted, and the growth of voids and hillocks can be further suppressed. However, the film thickness of the first Al alloy layer contributing to low resistance as a result of the interfacial interaction results in loss of reaction between the upper layer and the lower layer, and both interfaces need to be thickened in advance. There is.

  First, the fourth alloy layer 2d which is located on the lower side of the first alloy layer in this order from the insulating substrate 1 side on the insulating substrate 1 suitable for the glass substrate and serves as a hillock and void suppression layer. A fifth alloy layer 2e serving as a refractory metal supply layer for forming metal, a first alloy layer 2a composed of an Al alloy layer serving as a low resistance layer, and an upper layer of the first alloy layer Then, a third alloy layer 2c serving as a refractory metal supply layer for forming the second alloy layer 2b serving as a hillock / void suppressing layer was continuously formed. In the present invention, the first alloy layer 2a includes, as rare earth elements, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. The third alloy layer 2c and the fifth alloy layer 2e are made of Mo, Ti, Zr, Hf, V, Nb, Ta, Cr, W, refractory metals. At least one of these, or an alloy of these metals, and more desirably, Mo or an alloy film with Mo is formed. Any of the above alloy films can be formed by a sputtering method using an alloy target having these compositions. In this example, a binary alloy of Nd and Al was formed as an alloy layer that is the basis of the first alloy layer 2a, and a Mo film was formed as the third alloy layer 2c and the fifth alloy layer 2e. The film thickness was 450 nm, 100 nm, and 100 nm, respectively. Next, this laminated film was collectively processed into a pattern of the gate electrode wiring 2 by using a photolithography method.

  Next, heat treatment is performed in vacuum at 450 ° C., so that the first alloy layer 2a and the third alloy layer 2c and the first alloy layer 2a and the fifth alloy layer 2e are stacked at the interface. The second alloy layer 2b and the fourth alloy layer 2d of Nd, Mo, and Al were formed by utilizing the interfacial interaction. The film thicknesses of the second alloy layer 2b and the fourth alloy layer 2d are each 50 nm, and the film thicknesses of the first alloy layer 2a contributing to low resistance are the second alloy layer 2b and the fourth alloy layer 2d. The wiring resistance was ensured by forming the alloy layer 2d thick in advance by the thickness of the alloy layer 2d.

  FIG. 11 shows a depth direction AES composition analysis example of the gate electrode wiring 2 in Example 4 when Nd is used as the rare earth element and Mo is used as the refractory metal. The vertical axis represents the composition ratio of Nd, Mo, Al, and O, which are components of the laminated film and the insulating substrate, and the horizontal axis represents the sputtering time in the film thickness direction. Although the variation in the sputtering for sampling during the depth direction analysis and the influence of the charge-up of the insulating substrate 1, who is recognized in the profile in the fifth alloy layer located on the insulating substrate 1 side, In order from the insulating substrate 1 side, the third alloy layer 2c made of Mo, the fourth alloy layer 2d made of Nd, Mo, Al, the first alloy layer 2a made of an alloy layer of rare earth and Al, It can be seen that the second alloy layer 2b made of Nd, Mo, and Al and the third alloy layer 2c made of Mo are sequentially laminated. The main component of the second and fourth alloy layers is Al, and the concentration of Nd, which is a rare earth additive element in the second and fourth alloy layers, is in the first alloy layer. It can be seen that it is as high as 5 at% in the second and fourth alloy layers with respect to 0.5 at%. Thereby, it becomes easier to ensure low resistance, which is the role of the first alloy layer, and to suppress hillocks and voids, which are the roles of the second and fourth alloy layers.

  Table 1 is an example showing the hillock and void suppression effect obtained by applying the three-layer laminated structure and the five-layer laminated structure described in Example 2 and Example 4 to the lower electrode wiring structure. Nd or Ce was used as the rare earth additive element, Mo was used as the refractory metal, and the heat treatment temperature of the process was 450 ° C. The number of hillocks and voids for each size was determined by surface SEM observation at a magnification of 2000 times. In any case, the number and size of hillocks and voids can be greatly suppressed by applying the three-layer and five-layer structure of the present invention as compared with the case where the first alloy layer 2a is used as a single layer. You can see that

  In the second to fourth embodiments described above, in the configuration in which Mo is selected as the refractory metal, a mixed acid aqueous solution of phosphoric acid, acetic acid and nitric acid is used, whereby the third alloy layer 2c and the fifth The alloy layer 2e can be easily processed together with the Al alloy layers constituting the first, second, and fourth alloy layers, and an increase in the number of photolithography processes can be avoided.

  Also, when the fourth alloy layer and the fifth alloy layer are provided below the first alloy layer, batch processing can be similarly performed. Further, since Al and Mo have good epitaxial orientation alignment, crystal growth is easy to continue, and it is advantageous in terms of maintaining crystal grains and crystal grain boundaries that inhibit the movement of Al atoms.

  Although the example applied to the reverse stagger type TFT has been described above, the present invention can also be applied to a normal stagger type TFT as shown in an example described later.

  FIG. 5 is a cross-sectional view of a main part for explaining an application example to a positive stagger type TFT as a stagger type TFT constituting a pixel of a display device which is Embodiment 5 of the present invention.

  In this embodiment, in a display device having a plurality of pixels arranged in a matrix and a TFT for driving the pixels, the TFT is formed on a source substrate, a drain electrode, an insulating film, a semiconductor layer, and a gate on an insulating substrate. The TFT is a positive stagger type TFT in which electrodes are arranged in this order. The TFT has a gate wiring connected to the gate electrode, a drain wiring connected to the source electrode and the drain electrode, and the source electrode, the drain electrode, and the drain. The wiring has a structure arranged on the insulating substrate side of the TFT semiconductor layer.

  In the case of a positive stagger type TFT, the electrodes and wirings to which the present invention is applied are source electrode wirings and drain electrode wirings disposed below the channel semiconductor layer that requires high temperature formation.

  First, a first alloy layer 7a, 8a made of an Al alloy layer serving as a low resistance layer, in order from the insulating substrate 1 side, on the insulating substrate 1 suitable for a glass substrate, and a first alloy The second alloy layers 7b and 8b, which are located on the layers 7a and 8a and serve as hillock and void suppression layers, and the third alloy layer 7c made of a refractory metal or a refractory metal alloy are continuously formed. A laminated film to be the source electrode wiring 7 and the drain electrode wiring 8 of this example was formed. As in Example 2, the third alloy layer 7c is laminated on the first alloy layer 7a, and then a heat treatment step is provided, and Al and rare earth elements contained in the first alloy layer 7a, the third alloy layer 6c. As a result of the interfacial interaction with the refractory metal contained in the second alloy layer 7b, the second alloy layer 7b can also be formed.

  In the present invention, the first alloy layers 7a and 8a are composed of rare earth elements such as Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, The second alloy layers 7b and 8b are made of at least one of the rare earth elements and Mo, Ti, Zr, and refractory metals. The third alloy layer 7c is formed of an alloy film with Al containing at least one of Hf, V, Nb, Ta, Cr, and W, and the third alloy layer 7c is made of Mo, Ti, Zr, Hf, V as a refractory metal. , Nb, Ta, Cr, W, or an alloy of these metals, more preferably Mo or an alloy film with Mo. Any of the above alloy films can be formed by a sputtering method using an alloy target having these compositions.

  In this embodiment, the first alloy layers 7a and 8a are Ce and Al binary alloys, the second alloy layers 7b and 8b are Ce, Mo and Al ternary alloy films, and the third alloy layers. Mo films were formed as 2c, respectively. The film thicknesses were 300 nm, 50 nm, and 50 nm, respectively. Next, this laminated film was processed into a pattern of the source electrode wiring 7 and the drain electrode wiring 8 by using a photolithography method.

  Next, n + Si films to be doped layers 5 and 6 as contact layers were formed on the source and drain electrode wirings 7 and 8 by a plasma CVD method. The film thickness was 30 nm. Incidentally, the polarity of the doped layers 5 and 6 is not limited to the p + Si film, and it is needless to say that it can be arbitrarily changed to the p + Si film depending on the TFT configuration of the pixel circuit. Thereafter, the upper n + Si film, the source electrode wiring 7 and the drain electrode wiring 8 were collectively processed using photolithography.

Next, a polycrystalline Si film was formed as a semiconductor layer 4 on the doped layers 5 and ₆ by a thermal CVD method using a combination of GeF ₄ and Si ₂ H ₆ as a reaction gas at a substrate temperature of 450 ° C. . The film thickness was 100 nm. Thereafter, the laminated film of the n + Si film as the doped layers 5 and 6 and the semiconductor layer 4 was collectively processed into an island shape by using photolithography. As a result, the n + Si film on the source electrode wiring 7 and the drain electrode wiring 8 except for the contact portion with the semiconductor layer 4 was removed to form a contact layer.

Next, the gate insulating film 3 was formed on the semiconductor layer 4, the source electrode wiring 7, and the drain electrode wiring 8. As a material of the gate insulating film 3, it is possible to use SiO ₂ or SiN. These films can be formed by a plasma CVD method or a sputtering method. Alternatively, plasma oxidation, photooxidation, or the like may be used in combination. In this example, a SiO ₂ film formed by a plasma CVD method using TEOS was used. The film thickness was 150 nm.

  Next, the gate electrode wiring 2 was formed thereon. For these, since the upper limit temperature of the process can be lowered after the semiconductor layer 4 is formed, a low-resistance metal such as Al, Cu, Ag, or an alloy thereof, or a laminated film containing them can be used. In this example, a Mo / AlSi alloy / Mo laminated film was formed by sputtering in consideration of compatibility with contact characteristics. The film thickness was 40/400/40 nm. Next, the gate electrode wiring 2 was processed using a photolithography method.

  Next, a SiN film was formed as a protective insulating film 10 on the gate electrode wiring 2 by a plasma CVD method. The film thickness was 500 nm. Next, a through hole 11 was formed in the protective insulating film 10 using a photolithography method.

  Finally, a reflective metal film or a transparent conductive film was formed as the electrode material of the pixel electrode 12. In this embodiment, an ITO film, which is a transparent conductive film, is formed as the pixel electrode 12 by a sputtering method and processed using a photolithography method. The film thickness was 70 nm.

  Also in this embodiment, the alloy laminated structure of the present invention excellent in heat resistance of hillocks and voids is applied to the source and drain electrode wirings 7 and 8 of the positive stagger type TFT disposed below the semiconductor layer 4. Thus, it was possible to use an Al alloy wiring material whose use is limited in a normal polycrystalline Si TFT process. Further, since the wiring resistance can be significantly reduced by applying the low resistance Al, the display device can be easily enlarged without considering the signal delay due to the wiring resistance. Further, since a polycrystalline film having good characteristics can be used for the semiconductor layer 4, a staggered TFT having high characteristics with high mobility and a small threshold (Vth) shift can be obtained. A display device advantageous in terms of cost and performance can be provided.

  In the above description, the three-layer stacked structure having the third alloy layer is described as in the second embodiment. However, as in the first embodiment, the two-layer stacked structure (the source electrode, the drain electrode, and the drain wiring are A first alloy layer made of an Al alloy containing at least one rare earth element as an additive element in order from the insulating substrate side, an alloy of Al with at least one of the rare earth elements and at least one of the refractory metals A second alloy layer composed of a four-layer structure as in Example 3 (the source electrode, the drain electrode, and the drain wiring are formed with respect to the first alloy layer with respect to the second alloy layer). A structure having a fourth alloy layer formed of an alloy of Al and at least one of rare earth elements, at least one of refractory metals, and laminated on the side opposite to the side on which the layer is disposed), Example 4 Thus, a five-layer structure (the source electrode, the drain electrode, and the drain wiring are stacked on the opposite side of the fourth alloy layer from the side on which the first alloy layer is disposed, Similarly, a structure having a fifth alloy layer made of at least one of them can also be applied to a positive staggered TFT.

  FIG. 6 is a cross-sectional view of an essential part for explaining an application example to a liquid crystal display device which is Embodiment 6 of the display device of the present invention.

  The liquid crystal display device of this embodiment is an active matrix type liquid crystal display device in which a plurality of TFTs are arranged in a matrix, a counter substrate 16 disposed at a position facing the insulating substrate 1, and the insulating substrate 1. And the liquid crystal layer 22 disposed between the counter substrate 16 and a pair of alignment films (alignment films 15 and 20) sandwiching the liquid crystal layer 22. The counter electrode 19, the overcoat layer 18, and the color filter layer 17 are provided in this order from the film 20 side, and a spacer 21 is provided in the liquid crystal layer 22.

  First, an inverted staggered TFT having the gate electrode wiring 2 and the semiconductor layer 4 of the present invention was formed by the same method as in Example 2. A difference from the second embodiment is that a photosensitive organic resin is formed as an interlayer insulating film 13 on the protective insulating film 10. The film thickness of the interlayer insulating film 13 was 2 μm, and through holes 14 for connection were opened in the protective insulating film 10 and the interlayer insulating film 13 by using a photolithography method. Next, an ITO film, which is a transparent conductive film, was formed as the pixel electrode 12 by a sputtering method and processed using a photolithography method. The film thickness was 70 nm. Next, an alignment film 15 was formed on the pixel electrode 12. Next, the counter substrate 16 in which the color filter layer 17, the overcoat layer 18, the counter electrode 19 made of an ITO film, and the alignment film 20 were formed in this order was bonded to each other through a spacer 21. Liquid crystal was sealed in this to form a liquid crystal layer 22, and a liquid crystal display device was produced.

  The present embodiment is an application example to a TN type liquid crystal display device in which a counter electrode (or common electrode) 19 disposed on the counter substrate 16 side with respect to the pixel electrode 12 via the liquid crystal layer 22 is disposed. However, it goes without saying that the present invention can be similarly applied to an IPS liquid crystal display device in which a counter electrode (or a common electrode) is disposed on the TFT substrate 1 side.

As described in the first to fifth embodiments, the TFT using the gate electrode wiring 2 of the present invention having excellent heat resistance has the semiconductor layer 4 having good crystallinity while avoiding thermal damage to the electrode wiring. It can be formed at a high temperature. As a result, the off-current can be reduced to 10 ^-12 A or less, and good characteristics can be stably obtained. Therefore, even when applied to pixel driving of a liquid crystal display device, the leakage current is small and high-quality images can be obtained. I was able to. In addition, a staggered polycrystalline Si TFT structure with good characteristics and a low-resistance Al alloy wiring structure advantageous for upsizing can be compatible, and a liquid crystal display device advantageous in terms of cost and performance can be formed with high yield. . In the sixth embodiment, the application example to the liquid crystal display device using the inverted staggered TFT of the second embodiment has been described. However, the embodiment of the present invention is not limited to this. As an example, it goes without saying that the present invention can be similarly applied to the case where the positive staggered TFT of the fifth embodiment is used.

  FIG. 7 shows an application example to a TFT constituting a pixel of an organic EL display device which is composed of an organic light emitting element in which an organic light emitting layer which is a seventh embodiment of the display device of the present invention is sandwiched between an upper electrode and a lower electrode. It is principal part sectional drawing explaining these.

  First, an inverted stagger type TFT using the gate electrode wiring 2 of the present invention is formed by the same method as in the second embodiment. Next, an interlayer insulating film 13 made of a photosensitive organic resin was formed also as a planarizing layer for manufacturing the organic EL element. The film thickness was 2 μm, and through holes 14 for connection were opened in the protective insulating film 10 and the interlayer insulating film 13 using a photolithography method. Next, after forming the lower electrode 23 of the organic EL element on the interlayer insulating film 13, the charge transport layer 24, the light emitting layer 25, and the charge transport layer 26 of the organic EL element are deposited on the lower electrode 23 by vapor deposition. In addition, a transparent conductive film was formed as the upper electrode 27 by vapor deposition or sputtering, and a sealing layer 28 was formed to produce an organic EL display device.

  In addition, this pixel includes a TFT drive circuit including a TFT for driving the pixel as a peripheral circuit of the display device, and the laminated alloy layers of the first to fifth embodiments can be applied to this TFT.

As described in the first to fifth embodiments, the TFT using the gate electrode wiring 2 of the present invention having excellent heat resistance has the semiconductor layer 4 having good crystallinity while avoiding thermal damage to the electrode wiring. It can be formed at a high temperature. Thereby, a mobility of 5 cm ² / VS or more can be easily achieved. Since a staggered TFT with high mobility and low threshold (Vth) shift suitable for driving an organic EL element can be stably obtained, the produced organic EL element has high luminance and long length. The life characteristics are shown. In addition, a staggered polycrystalline Si TFT structure with good characteristics and a low-resistance Al alloy wiring structure advantageous for upsizing can be compatible, and an organic EL display device advantageous in terms of cost and performance can be formed with high yield. It was. In Example 7, the application example to the organic EL display device using the inverted staggered TFT of Example 2 has been described, but the embodiment of the present invention is not limited to this. Needless to say, the present invention can be similarly applied to the case where the positive staggered TFT of the fifth embodiment is used.

  In the first to seventh embodiments described above, the application examples to the TFT and the pixel circuit of the active drive display device such as the liquid crystal display device and the organic EL display device have been described. However, the embodiment of the present invention is limited to this. However, the present invention can be similarly applied to TFTs for driver circuits provided around these display devices.

It is sectional drawing which shows Example 1 of the display apparatus of the reverse stagger type TFT which concerns on this invention. It is sectional drawing which shows Example 2 of the display apparatus of the reverse stagger type TFT which concerns on this invention. It is sectional drawing which shows Example 3 of the display apparatus of the reverse stagger type TFT which concerns on this invention. It is sectional drawing which shows Example 4 of the display apparatus of the reverse stagger type TFT which concerns on this invention. It is sectional drawing which shows Example 5 of the display apparatus of the positive stagger type TFT which concerns on this invention. It is sectional drawing which shows Example 6 of the liquid crystal display device of the reverse stagger type TFT which concerns on this invention. It is sectional drawing which shows Example 7 of the organic electroluminescence display of the reverse stagger type TFT which concerns on this invention. It is a figure which shows the example of formation of the 2nd alloy layer 2b in Example 2 of this invention. It is a figure which shows the other example of formation of the 2nd alloy layer 2b in Example 2 of this invention. It is a figure which shows the example of AES analysis in Example 2 of this invention. It is a figure which shows the example of AES analysis in Example 4 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Gate electrode wiring 2a, 7a, 8a 1st alloy layer 2b, 7b, 8b 2nd alloy layer 2c, 7c, 8c 3rd alloy layer 2d 4th alloy layer 2e 5th alloy layer 3 Gate insulating film 4 Semiconductor layers 5 and 6 Doped layer 7 Source electrode wiring 8 Drain electrode wiring 9 Channel region 10 Protective insulating layers 11 and 14 Through-hole 12 Pixel electrode 13 Interlayer insulating films 15 and 20 Alignment film 16 Counter substrate 17 Color Filter layer 18 Overcoat layer 19 Counter electrode 21 Spacer 22 Liquid crystal layer 23 Lower electrodes 24 and 26 Charge transport layer 25 Light emitting layer 27 Upper electrode 28 Sealing layer

Claims (14)

A display device having a plurality of pixels arranged in a matrix and a TFT for driving the pixels,
The TFT is a reverse stagger type TFT in which a gate electrode, an insulating film, a semiconductor layer, a source electrode and a drain electrode are arranged in this order on an insulating substrate,
The TFT has a gate wiring connected to the gate electrode, and a drain wiring connected to the source electrode and the drain electrode,
The gate electrode and the gate wiring are disposed closer to the insulating substrate than the semiconductor layer of the TFT,
The gate electrode and the gate wiring are sequentially from the insulating substrate side.
A first metal layer comprising an alloy of at least one rare earth element and Al;
A second metal layer comprising an alloy of at least one of rare earth elements, at least one of refractory metals of Mo, Ti, Zr, Hf, V, Nb, Ta, Cr or W , and Al,
A third metal layer comprising at least one of the refractory metals ,
The concentration of the rare earth element in the second metal layer is 1 to 10 at%;
The display device in which the concentration of the rare earth element in the first metal layer is 0.01 to 3 at%. The display device according to claim 1,
The gate electrode and the gate wiring are a fourth layer made of an alloy of at least one of rare earth elements, at least one of the refractory metals , and Al between the insulating substrate and the first metal layer. A display device having a metal layer. The display device according to claim 2, wherein
The display device in which the gate electrode and the gate wiring have a fifth metal layer made of at least one of the refractory metals between the insulating substrate and the fourth metal layer. A display device having a plurality of pixels arranged in a matrix and a TFT for driving the pixels,
The TFT is a positive stagger type TFT in which a source electrode and a drain electrode, a semiconductor layer, an insulating film, and a gate electrode are arranged in this order on an insulating substrate,
The TFT has a gate wiring connected to the gate electrode, and a drain wiring connected to the source electrode and the drain electrode,
The source electrode, the drain electrode, and the drain wiring are disposed closer to the insulating substrate than the semiconductor layer of the TFT,
The source electrode, the drain electrode, and the drain wiring are sequentially from the insulating substrate side.
A first metal layer comprising an alloy of at least one rare earth element and Al;
A second metal layer comprising an alloy of at least one of rare earth elements, at least one of refractory metals of Mo, Ti, Zr, Hf, V, Nb, Ta, Cr or W , and Al,
A third metal layer comprising at least one of the refractory metals ,
The concentration of the rare earth element in the second metal layer is 1 to 10 at%;
The display device in which the concentration of the rare earth element in the first metal layer is 0.01 to 3 at%. The display device according to claim 4, wherein
The source electrode, the drain electrode, and the drain wiring are an alloy of at least one of rare earth elements, at least one of the refractory metals , and Al between the insulating substrate and the first metal layer. A display device having a fourth metal layer. The display device according to claim 5, wherein
The display device in which the source electrode, the drain electrode, and the drain wiring have a fifth metal layer made of at least one of the refractory metals between the insulating substrate and the fourth metal layer. The display device according to any one of claims 1 to 6,
The display device in which the rare earth element is Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. The display device according to claim 1,
The display device in which the refractory metal is Mo. The display device according to claim 1 or 4,
The display device wherein the second metal layer has a thickness of 5 to 200 nm. The display device according to claim 1 or 4,
The display device in which the first metal layer further includes at least one of Si, Cu, Mg, and Ni. The display device according to claim 1 or 4,
The semiconductor device includes a display device including a polycrystalline film of Si or SiGe. The display device according to claim 1 or 4,
A counter substrate disposed at a position facing the insulating substrate;
A liquid crystal layer disposed between the insulating substrate and the counter substrate;
A pair of alignment films sandwiching the liquid crystal layer;
A display device. The display device according to claim 1 or 4,
The pixel is composed of an organic light emitting element in which an organic light emitting layer is sandwiched between an upper electrode and a lower electrode,
The display device in which the pixel has a TFT drive circuit for driving the pixel. The display device according to claim 1 or 4,
The display apparatus which has the peripheral circuit which comprised the said TFT with the said pixel arrange | positioned at the said matrix form.

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