JP2013115144A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which field concentration just under an edge part of a LOCOS oxide film is easily alleviated, and which can achieve an excellent breakdown voltage and excellent resistance in a semiconductor layer just under the LOCOS oxide film.SOLUTION: A semiconductor device (1) has a profile in which at least a part (22a, 22b) of edges (22a, 22b) of a LOCOS oxide film (22), which terminate in a lateral direction with respect to a surface of a semiconductor substrate terminates by being sandwiched by a top face and an undersurface at an angle (θ) of not less than 15 degrees and not more than 30 degrees.

Description

  The present invention relates to a semiconductor device having a LOCOS (Local Oxidation of Silicon) oxide film, and more particularly to a structure for relaxing a high electric field.

  DMOS (Double Diffused MOS) transistors used as power elements in semiconductor composite devices consisting of CMOS transistors, bipolar transistors, power MOS transistors, etc. that realize integrated ICs for control that are indispensable for the construction of in-vehicle electronic systems LDMOS (Lateral Diffused MOS) transistors and IGBTs (Insulated Gate Bipolar Transistors) are required to have a low on-resistance while ensuring a high breakdown voltage. The LOCOS oxide film used for element isolation is used for the purpose of assisting the gate field plate effect in a lateral power semiconductor element such as an LDMOS transistor or a lateral IGBT. The LOCOS oxide film having this purpose is provided on the drift layer of the lateral power semiconductor element and relaxes the electric field between the gate and the drain or between the gate and the collector. Thereby, an effect of increasing the breakdown voltage of the element can be obtained.

  In Patent Document 1, as shown in FIGS. 10A and 10B, the electric field distribution near the drain of the MOS transistor is discussed. In both the structures of FIGS. 10A and 10B, the gate oxide film in the vicinity of the drain is formed to be about 1 μm thick by the LOCOS oxide film. In the structure of FIG. 10A, the gate oxide film other than the LOCOS oxide film is formed to be as thin as about 20 nm, and the electric field strength has a maximum value near the channel side end of the LOCOS oxide film. In the structure of FIG. 10B, the gate oxide film other than the LOCOS oxide film is formed to be as thick as about 200 nm, and the electric field strength also has a maximum value immediately below the channel side end of the LOCOS oxide film. It is smaller than the maximum value in the structure of FIG. Impact ions are likely to be generated at locations where the electric field is large. However, if the gate oxide film is formed as thick as about 200 nm as in the structure of FIG. 10B, the electric field near the channel side end of the LOCOS oxide film is relaxed. Therefore, impact ionization is suppressed to some extent. Therefore, the structure of FIG. 10B in which impact ionization is easily suppressed is more advantageous for increasing the breakdown voltage of the device than the structure of FIG.

  However, in Patent Document 1, based on the electric field distribution described above, in order to further alleviate the concentration of the electric field generated near the channel side end of the LOCOS oxide film, It discloses that a LOCOS oxide film for a high breakdown voltage region is formed by two selective oxidations. After completing the implantation of the source region and the drain region as shown in FIG. 11A, the gate insulating film 2c for the low breakdown voltage region is formed by the first selective oxidation as shown in FIG. 11B. A silicon nitride film 8 is formed on the gate insulating film 2c to open a window, and a high-breakdown-voltage gate insulating film 2b is formed by second selective oxidation through the window as shown in FIG. 11C. The gate insulating film 2b has an intermediate thickness between the thickness of the gate insulating film 2c and the thickness of the gate insulating film at the center of the channel region.

  Patent Document 2 discloses a technique for obtaining a flat substrate surface by forming a recess in a silicon substrate 101 and embedding it with a LOCOS oxide film 105 as shown in FIG.

Japanese Patent No. 3230184 JP-A-8-213449

  If the high electric field can be relaxed by forming a LOCOS oxide film with the purpose of assisting the gate field plate effect, the on-resistance can be reduced to some extent by lowering the resistance of the drift layer of the power element accordingly. However, as described in Patent Document 1, if the high electric field is relieved by two selective oxidations, the number of steps increases, resulting in an increase in manufacturing cost. The invention of Patent Document 1 is made in order to make it possible to apply a high voltage between the drain and the source while applying a low voltage to the gate. Therefore, an optimum withstand voltage structure is not disclosed for a normal structure of a lateral power semiconductor element to which a higher gate voltage is applied.

  Further, Patent Document 2 discloses an invention relating to a so-called recess LOCOS film, but since the electric field concentration is likely to occur immediately below the end of the LOCOS oxide film, the breakdown voltage of the element is low.

SUMMARY OF THE INVENTION The present invention solves the above-described problem, and a semiconductor in which electric field concentration immediately below the end portion of the LOCOS oxide film is easily relaxed and a good breakdown voltage and resistance of the semiconductor conductive layer immediately below the LOCOS oxide film can be realized. An object is to provide an apparatus and a method for manufacturing the same.
The purpose is to provide.

  1st aspect of this invention is a semiconductor device provided with the semiconductor substrate provided with the semiconductor conductive layer in the surface layer, and the LOCOS oxide film formed on the said semiconductor conductive layer, Comprising: The said semiconductor substrate of the said LOCOS oxide film At least a part of the edge that terminates laterally with respect to the surface of the surface has a profile that is sandwiched between the upper surface and the lower surface at an angle of 15 degrees or more and 30 degrees or less and terminates.

  According to a second aspect of the present invention, in the first aspect, the semiconductor device includes a lateral double diffusion MOS transistor having the semiconductor conductive layer and the LOCOS oxide film in part, and the semiconductor conductive layer is the lateral double diffusion MOS. It is a drift layer of a transistor, and at least a part of the edge includes an edge of the LOCOS oxide film adjacent to a channel region of the lateral double diffusion MOS transistor.

  According to a third aspect of the present invention, there is provided a lateral insulated gate bipolar transistor having the semiconductor conductive layer and the LOCOS oxide film as a part thereof in the first aspect, wherein the semiconductor conductive layer is formed of the lateral insulated gate bipolar transistor. It is a drift layer, and at least a part of the edge includes an edge of the LOCOS oxide film adjacent to the channel region of the lateral insulated gate bipolar transistor.

  According to a fourth aspect of the present invention, in any one of the first to third aspects, one or more first semiconductors using the semiconductor conductive layer and the LOCOS oxide film as a structure An element and one or more second semiconductor elements other than the first semiconductor element are formed monolithically on the semiconductor substrate.

  According to a fifth aspect of the present invention, in the fourth aspect, the first semiconductor element and the second semiconductor element have different withstand voltages.

  According to a sixth aspect of the present invention, in any one of the first to fifth aspects, an element isolation film including an edge having the profile is provided.

  7th aspect of this invention is a manufacturing method of the semiconductor device which forms a LOCOS oxide film on a semiconductor conductive layer, Comprising: The buffer thermal oxide film on the said semiconductor conductive layer of the semiconductor substrate which has the said semiconductor conductive layer in a surface layer Forming a silicon nitride film on the buffer thermal oxide film, and exposing the surface of the semiconductor conductive layer through the formed silicon nitride film and the buffer thermal oxide film A step of performing opening, a step of selectively thermally oxidizing the semiconductor conductive layer without etching through the window formed by opening the window, and the silicon nitride film and the buffer thermal oxide film after selective thermal oxidation of the semiconductor conductive layer And removing at least one edge that terminates in a lateral direction with respect to the surface of the semiconductor substrate of the LOCOS oxide film. , Sandwiched by upper and lower surfaces and a 15 degrees 30 degrees from to have a profile that end, to form the LOCOS oxide film.

  According to an eighth aspect of the present invention, in the seventh aspect, the buffer thermal oxide film is formed to a thickness of 60 nm to 100 nm, and the silicon nitride film is formed to a thickness of 150 nm to 200 nm. .

  In a ninth aspect of the present invention, in the seventh aspect or the eighth aspect, the LOCOS oxide film is formed to a thickness in the range of 250 nm to 400 nm.

  According to the first aspect, impact ionization is suppressed in the semiconductor conductive layer near the edge that terminates at an angle of 15 degrees or more and 30 degrees or less of the LOCOS oxide film. Therefore, by forming the LOCOS oxide film on the semiconductor conductive layer, the electric field concentration just below the end of the LOCOS oxide film can be easily relaxed, and the semiconductor conductive layer directly under the LOCOS oxide film can be improved without increasing the cost. Withstand voltage and resistance can be obtained.

  According to the second aspect, the electric field concentration is relaxed in the drift layer immediately below the end of the LOCOS oxide film, and a high breakdown voltage and low on-resistance LDMOS can be obtained.

  According to the third aspect, the electric field concentration is relaxed in the drift layer immediately below the end of the LOCOS oxide film, and a lateral insulated gate bipolar transistor having a high breakdown voltage and a low on-resistance can be obtained.

  According to the fourth aspect, in a semiconductor device including a plurality of types of elements, such as an IC including a power element and a logic circuit for controlling the power element, the first semiconductor element is formed while simultaneously forming a plurality of types of elements. It is possible to improve the withstand voltage and the on-resistance.

  According to the fifth aspect, there is provided a semiconductor device including a plurality of types of elements and a plurality of types of breakdown voltage elements, wherein the breakdown voltage and resistance of the first semiconductor element are selectively improved with respect to the second semiconductor element. can do.

  According to the sixth aspect, the element isolation film can be formed by the same process as the LOCOS oxide film, and the process efficiency is improved.

  According to the seventh aspect, a LOCOS oxide film having an edge that terminates at an angle of 15 degrees or greater and 30 degrees or less can be produced. Impact ionization is suppressed in the semiconductor conductive layer near the edge that terminates at an angle of 15 degrees or more and 30 degrees or less of the LOCOS oxide film. Therefore, by forming the LOCOS oxide film on the semiconductor conductive layer, the electric field concentration immediately below the end of the LOCOS oxide film can be easily relaxed, and a good breakdown voltage and resistance of the semiconductor conductive layer immediately below the LOCOS oxide film can be obtained. it can.

  According to the eighth aspect, by changing the thickness of the buffer thermal oxide film and the thickness of the silicon nitride film within the above ranges, the edge profile terminates at an angle of 15 degrees to 30 degrees. Can be adjusted as follows.

  According to the ninth aspect, by changing the thickness of the LOCOS oxide film within the above range, the edge profile can be adjusted to terminate at an angle of 15 degrees or more and 30 degrees or less.

Sectional drawing which shows embodiment of this invention and shows the structure of a semiconductor device A graph showing the relationship between the off breakdown voltage and the on resistance of the LOCOS oxide film Graph showing the relationship between the edge angle of the LOCOS oxide film and the off breakdown voltage Graph showing the relationship between the edge angle of the LOCOS oxide film and the normalized on-resistance (A) And (b) is sectional drawing explaining the difference in edge angle by the difference in the manufacturing method of a LOCOS oxide film (A) thru | or (c) are sectional drawings which show the 1st manufacturing process of the semiconductor device of FIG. (A) thru | or (c) is sectional drawing which shows the 2nd manufacturing process of the semiconductor device of FIG. (A) thru | or (c) are sectional drawings which show the 3rd manufacturing process of the semiconductor device of FIG. Sectional drawing which shows this embodiment and shows the structure of the semiconductor device which concerns on a modification The prior art is shown, (a) And (b) is sectional drawing explaining electric field distribution. FIG. 2A is a cross-sectional view showing a process of performing selective oxidation twice, showing a conventional technique. Sectional drawing which shows a prior art and shows the structure of a recess LOCOS oxide film

  The embodiment of the present invention will be described with reference to FIGS. 1 to 9 as follows.

(Configuration of semiconductor device)
FIG. 1 shows a cross-sectional configuration of a semiconductor device 1 according to this embodiment.
The semiconductor device 1 includes a silicon substrate 11, a BOX layer (Buried Oxide: buried oxide film) 12, an N ⁺ buried layer 13, an N ⁻ active layer 14, a P-type body layer 15, an LVPW (Low Voltage P-Well). Type well) 16, N ⁺ source region 17, P ⁺ back gate contact layer 18, N type drift layer 19, LVNW (Low Voltage N-well) 20, N ⁺ drain region 21, LOCOS oxide film 22, a gate insulating film 23, a gate electrode 24, and sidewalls 25 are provided. The cross-sectional view of FIG. 1 shows the configuration of the LDMOS transistor.

On the silicon substrate 11, a BOX layer 12, an N ⁺ buried layer 13, and an N ⁻ active layer 14 are arranged in this order. The silicon substrate 11, the BOX layer 12, the N ⁺ buried layer 13, and the N ⁻ active layer 14 constitute an SOI substrate as a semiconductor substrate.

P type body layer 15 and N type drift layer 19 are formed in the surface layer of the semiconductor substrate in N ⁻ active layer 14. The LVPW 16 is formed in the P-type body layer 15, and the LVNW 20 is formed in the N-type drift layer 19. The N ⁺ source region 17 is formed in the LVPW 16 in the depth direction from the surface of the semiconductor substrate. A partial region of P-type body layer 15 or a partial region of P-type body layer 15 and LVPW 16 is sandwiched in the depth direction from the substrate surface between N ⁺ source region 17 and N-type drift layer 19. The vicinity of the surface of the semiconductor substrate in the partial region is a channel region. The P ⁺ back gate contact layer 18 is formed in the depth direction from the surface of the semiconductor substrate so as to be positioned on the opposite side of the channel region with respect to the N ⁺ source region 17 in the LVPW 16. The N ⁺ drain region 21 is formed in the LVNW 20 in the depth direction from the surface of the semiconductor substrate.

The LOCOS oxide film 22 is formed on the surface of the semiconductor substrate between the gate insulating film 23 and the N ⁺ drain region 21 on the N-type drift layer 19. The gate insulating film 23 is made of, for example, a silicon oxide film, and is formed so as to cover at least the channel region and the region not covered with the LOCOS oxide film 22 of the N-type drift layer 19. The gate electrode 24 is made of polysilicon, for example, and is formed so as to cover the gate insulating film 23 and a part of the LOCOS oxide film 22 on the side adjacent to the gate insulating film 23. The sidewall 25 is formed so as to cover the side surface of the gate electrode 24.

The gate electrode 24 is connected to the gate terminal G of the semiconductor device 1. N ⁺ source region 17 and P ⁺ back gate contact layer 18 are connected to source terminal S of semiconductor device 1 through a source electrode and a source wiring. N ⁺ drain region 21 is connected to drain terminal D of semiconductor device 1 through a drain electrode and a drain wiring.

(Shape of LOCOS oxide film)
The LOCOS oxide film 22 has an edge that terminates in a lateral direction with respect to the surface of the semiconductor substrate. The edges include at least an edge 22a in which the LOCOS oxide film 22 extends in the gate width direction adjacent to the channel region, and an edge 22b in which the LOCOS oxide film 22 extends in the drain width direction adjacent to the N ⁺ drain region 21. And are included.

  The edge 22a has a profile that is sandwiched between an upper surface and a lower surface at an angle θ ranging from 15 degrees to 30 degrees and ends. That is, a cross-sectional profile obtained by cutting the LOCOS oxide film 22 along a plane perpendicular to the gate width direction in which the edge 22a extends is shaped to terminate at an angle θ. Here, the edge 22b also has the same profile as the edge 22a, but may have a different profile from the edge 22a, and may have an angle θ that is not in the range of 15 degrees to 30 degrees.

  FIG. 2 shows the relationship between the off breakdown voltage BVoff (horizontal axis) and the normalized on-resistance RonA (vertical axis) of the semiconductor device 1 using the angle θ as a parameter. A straight line C indicated by a broken line is based on a simulation result, and the vertical axis and the horizontal axis are normalized in arbitrary units so that differences in element dimensions and differences in process conditions such as carrier concentration of the drift layer can be absorbed. As described above, when the angle θ is changed, the off breakdown voltage BVoff and the normalized on resistance RonA change linearly in a direction in which the normalized on resistance RonA decreases as the off breakdown voltage BVoff increases. Actually, when the semiconductor device 1 was manufactured for each of the angles θ = 20.0 degrees, 22.5 degrees, 25.0 degrees, and 31.0 degrees, the plot shown in the figure was obtained, and the simulation result was verified. We were able to. In the graph, the performance improves as it goes to the lower right. However, for the semiconductor device 1 with the angles θ = 20.0 degrees, 22.5 degrees, and 25.0 degrees, the LOCOS oxide film 22 is formed according to the manufacturing process described later, and the semiconductor with the angle θ = 31.0 degrees. Regarding the apparatus, since the value of θ was large, a LOCOS oxide film was produced by the recess LOCOS oxidation method.

  FIG. 3 is a plot of the plot of FIG. 2, with the horizontal axis representing the angle θ and the vertical axis representing the off breakdown voltage BVoff. Further, FIG. 4 shows a plot obtained by re-plotting the horizontal axis as the angle θ and the vertical axis as the normalized on-resistance RonA. 3 and FIG. 3 in consideration of the linear relationship between the off breakdown voltage BVoff and the normalized on-resistance RonA as shown in FIG. 2, that is, if one is a preferred value, the other is also a preferred value. 4, the range θp of the angle θ that simultaneously satisfies the preferable off breakdown voltage BVoff and the normalized on-resistance RonA is found to be 15 degrees or more and 30 degrees or less.

  The range θl of the angle θ exceeding 30 degrees includes an angle generally used in a LOCOS oxide film for element isolation including a recess LOCOS oxide film and an STI (Shallow Trench Isolation) oxide film. In addition, it is a range of a steep angle with respect to the semiconductor substrate surface. FIG. 5A shows the angle θ within the range θp of the LOCOS oxide film 22 that has the effect of assisting the gate field plate effect, and FIG. 5B shows the range of the element isolation LOCOS oxide film. The difference from the angle θ within θl is shown. The recess LOCOS oxide film and the STI oxide film are very steep with an angle θ close to 90 degrees. If the angle θ of the LOCOS oxide film 22 is set to a value in the range θl, impact ionization becomes significant at the point P in the N-type drift layer 19 near the edge 22a in FIG. Element isolation LOCOS oxide films, such as recess LOCOS oxide films and STI oxide films, are conventionally used in circuit pattern processes mainly composed of logic circuits, so that the edge shape suppresses impact ionization. Is not taken into account.

Further, if a range θs of an angle θ of less than 15 degrees is adopted, the bird's beak is likely to extend from the edges 22a and 22b of the LOCOS oxide film 22. Therefore, the upper portion of the N ⁻ active layer 14, particularly the channel region, is covered with bird's beaks, which hinders the semiconductor device 1 from functioning as an LDMOS.

  If the LDMOS transistor using the N-type drift layer 19 and the LOCOS oxide film 22 in the structure is a first semiconductor element, one or more first semiconductor elements and one or more other than the first semiconductor elements are used. The second semiconductor element may be formed monolithically on the semiconductor substrate. Accordingly, in a semiconductor device including a plurality of types of elements, such as an IC including a power element and a logic circuit for controlling the power element, the breakdown voltage and on-resistance of the first semiconductor element can be reduced while simultaneously forming a plurality of types of elements. Can be improved.

  The first semiconductor element and the second semiconductor element may have different breakdown voltages. Accordingly, a semiconductor device including a plurality of types of elements (elements including a plurality of types of breakdown voltage systems) in which the breakdown voltage and on-resistance of the first semiconductor element are selectively improved with respect to the second semiconductor element is provided. be able to.

  The semiconductor device 1 may include an element isolation film having an edge having the same profile as the edge 22a of the LOCOS oxide film 22. Thereby, the element isolation film can be formed by the same process as the LOCOS oxide film 22, and the process efficiency is improved.

(Semiconductor device manufacturing process)
Next, the manufacturing process of the semiconductor device 1 will be described.
First, as shown in FIG. 6A, an SOI substrate in which a silicon substrate 11, a BOX layer 12, an N ⁺ buried layer 13, and an N ⁻ active layer 14 are arranged in this order is prepared. Here, an example of manufacturing an N channel type LDMOS of the semiconductor device 1 will be described. For example, the N ⁺ buried layer 13 is formed as a layer having a carrier concentration of about 1 × 10 ¹⁹ cm ^{−2 using} arsenic as a dopant. The N ⁻ active layer 14 is formed as a layer having a carrier concentration of about 1 × 10 ¹⁵ cm ⁻² with phosphorus as a dopant and a film thickness of about 12 μm. The film thickness of the BOX layer 12 is, for example, about 1.0 μm.

  Next, as shown in FIG. 6B, the surface of the SOI substrate is oxidized by a thermal oxidation method to form a buffer thermal oxide film 31 having a thickness of about 80 nm. A preferable film thickness range of the buffer thermal oxide film 31 is 60 nm to 100 nm. If the film thickness is smaller within this range, the LOCOS oxide film 22 has an effect of increasing the deterrence of bird's beak generation. That is, there is an effect of increasing the angle θ. In addition, the larger the film thickness within this range, there is an effect of reducing the angle θ. When the recess LOCOS oxide film is formed as in the prior art, the thickness of the buffer thermal oxide film is about 30 nm.

  Next, as shown in FIG. 6C, a silicon nitride film 32 having a thickness of about 175 nm is formed on the buffer thermal oxide film 31 by the CVD method. A preferable film thickness range of the silicon nitride film 32 is 150 nm to 200 nm. A smaller film thickness within this range has an effect of reducing the angle θ. In addition, the larger film thickness within this range has the effect of increasing the deterrence of bird's beak generation in the LOCOS oxide film 22. That is, there is an effect of increasing the angle θ.

  The angle θ can be easily adjusted to 15 degrees or more and 30 degrees or less by combining the preferable film thickness ranges of the buffer thermal oxide film 31 and the silicon nitride film 32.

Next, as shown in FIG. 7A, a photoresist 33 is patterned on the silicon nitride film 32, and the buffer thermal oxide film 31 and the silicon nitride film 32 are formed by dry etching until the surface of the N ⁻ active layer 14 is exposed. The window 34 is formed by opening the window. At this time, if there is a region for forming an element isolation film on the semiconductor device 1, the window 34 is also formed in the region. For dry etching, RIE (Reactive Ion Etching) using, for example, CHF3 / CF4 as an etchant gas is used.

Next, as shown in FIG. 7B, after removing the photoresist 33, the silicon nitride film 32 is used as a mask and the surface of the N ⁻ active layer 14 is passed through the window 34 at a temperature of about 1100 ° C. in a hydrogen / oxygen atmosphere. Thermally oxidize for about 50 minutes. Here, the surface of the N ⁻ active layer 14 is not recess-etched before thermal oxidation. Conventionally, recess etching of about 60 nm has been performed. By thermal oxidation, only the surface of the N ⁻ active layer 14 exposed from the window 34 is selectively oxidized, and the LOCOS oxide film 22 is formed. The angle θ can also be adjusted by the film thickness of the LOCOS oxide film 22, and the preferable film thickness range is 250 nm to 400 nm.

  Next, as shown in FIG. 7C, the silicon nitride film 32 and the buffer thermal oxide film 31 are removed to expose the surface of the SOI substrate. The silicon nitride film 32 can be removed by wet etching using hot phosphoric acid, and the buffer thermal oxide film 31 can be removed by using buffered hydrofluoric acid. Thereby, the LOCOS oxide film 22 is completed, and at this time, the angle θ of the edges 22a and 22b is formed within a range of 15 degrees or more and 30 degrees or less.

  Thereafter, as shown in FIG. 8A, the surface of the SOI substrate is oxidized to form a sacrificial oxide film 35, and ion implantation is performed through the sacrificial oxide film 35 to sequentially form the P-type body layer 15 and the LVPW 16. In addition, the N-type drift layer 19 and the LVNW 20 are formed. Each implantation region is individually patterned by a lithography process.

  Then, as shown in FIG. 8B, after the sacrificial oxide film 35 is removed, gate oxidation is performed to form the gate insulating film 23. Further, after the gate insulating film 23 is formed, polysilicon and WSi are formed, and the gate electrode 24 is formed by a lithography process and an etching process.

Next, as shown in FIG. 8C, after the sidewall 25 is formed, LDD (Lightly Doped Drain) implantation (not shown) is performed, and an N ⁺ source region 17, a P ⁺ back gate contact layer 18, and N ⁺ drain region 21 is formed by ion implantation. Thereafter, although not shown, the source and drain electrodes and the interlayer insulating film are formed, and further various contacts and metal wirings are formed, whereby the semiconductor device 1 of FIG. 1 is completed.

  As described above, according to the present embodiment, impact ionization is suppressed in the N-type drift layer 19 near the edge of the LOCOS oxide film 22 that terminates at an angle of 15 degrees or more and 30 degrees or less. Therefore, by forming the LOCOS oxide film 22 on the N-type drift layer 19, the electric field concentration immediately below the end of the LOCOS oxide film 22 can be easily relaxed, and the N directly below the LOCOS oxide film 22 is not accompanied by an increase in cost. Good breakdown voltage and resistance of the type drift layer 19 can be obtained. This process is equivalent to a fine CMOS process.

(Configuration of Modified Example of Semiconductor Device)
FIG. 9 shows a cross-sectional configuration of a semiconductor device 41 according to a modification of the present embodiment.
The semiconductor device 41 is configured by replacing the N ⁺ source region 17 with the N ⁺ emitter region 51 and the N ⁺ drain region 21 with the P ⁺ collector region 52 in the semiconductor device 1 of FIG. The cross-sectional configuration in FIG. 9 constitutes a lateral IGBT. This also makes it possible to obtain a good breakdown voltage and resistance of the N-type drift layer 19 immediately below the LOCOS oxide film 22 as in the semiconductor device 1.
In addition, the present invention can be applied to a P-channel element, and is not limited to an LDMOS and a lateral IGBT, but can be applied to any place where a breakdown voltage and a low resistance are desired.

  The present invention is applicable to in-vehicle and power ICs.

1, 41 Semiconductor device 19 N-type drift layer (semiconductor conductive layer)
22 LOCOS oxide film 22a, 22b Edge θ angle

Claims (9)

A semiconductor device comprising a semiconductor substrate having a semiconductor conductive layer as a surface layer, and a LOCOS oxide film formed on the semiconductor conductive layer,
The LOCOS oxide film has a profile in which at least a part of the edge terminating in the lateral direction with respect to the surface of the semiconductor substrate is sandwiched between the upper surface and the lower surface at an angle of 15 degrees or more and 30 degrees or less. A semiconductor device characterized by that. A lateral double diffusion MOS transistor having the semiconductor conductive layer and the LOCOS oxide film in part,
The semiconductor conductive layer is a drift layer of the lateral double diffusion MOS transistor;
2. The semiconductor device according to claim 1, wherein at least a part of the edge includes an edge of the LOCOS oxide film adjacent to a channel region of the lateral double diffusion MOS transistor. A lateral insulated gate bipolar transistor partially including the semiconductor conductive layer and the LOCOS oxide film;
The semiconductor conductive layer is a drift layer of the lateral insulated gate bipolar transistor;
2. The semiconductor device according to claim 1, wherein at least a part of the edge includes an edge of the LOCOS oxide film adjacent to a channel region of the lateral insulated gate bipolar transistor.   One or more first semiconductor elements using the semiconductor conductive layer and the LOCOS oxide film as a structure, and one or more second semiconductor elements other than the first semiconductor element are monolithically formed on the semiconductor substrate. The semiconductor device according to claim 1, wherein the semiconductor device is formed.   The semiconductor device according to claim 4, wherein the first semiconductor element and the second semiconductor element have different breakdown voltages.   The semiconductor device according to claim 1, further comprising an element isolation film having an edge having the profile. A method of manufacturing a semiconductor device in which a LOCOS oxide film is formed on a semiconductor conductive layer,
Forming a buffer thermal oxide film on the semiconductor conductive layer of the semiconductor substrate having the semiconductor conductive layer as a surface layer;
Forming a silicon nitride film on the buffer thermal oxide film;
Performing a window opening through the formed silicon nitride film and the buffer thermal oxide film to expose the surface of the semiconductor conductive layer;
Selective thermal oxidation without etching the semiconductor conductive layer through the window formed by opening the window;
Removing the silicon nitride film and the buffer thermal oxide film after selective thermal oxidation of the semiconductor conductive layer;
By going through
The LOCOS oxide film has a profile in which at least one edge that terminates in a lateral direction with respect to the surface of the semiconductor substrate is sandwiched between an upper surface and a lower surface at an angle of 15 degrees or more and 30 degrees or less and terminates. A method of manufacturing a semiconductor device, comprising forming a LOCOS oxide film.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the buffer thermal oxide film is formed to a thickness of 60 nm to 100 nm, and the silicon nitride film is formed to a thickness of 150 nm to 200 nm. .   9. The method of manufacturing a semiconductor device according to claim 7, wherein the LOCOS oxide film is formed to a thickness in a range of 250 nm to 400 nm.

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