JPH0992788A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the alignment accuracy in mark aligning and ESD resis tance by forming an element isolation region from two types of insulating films of the flattened first instating film and not flattened second insulating film having a protruding sectional shape, and particularly isolating the ESD protective element by the second insulating film. SOLUTION: The region undesired to flatten the insulating film of an element isolation region such as, for example, an ESD protective element forming region 10 desired to reduce the breakdown voltage of the parasitic transistor of the part used as a mark alignment detecting mark or a peripheral circuit region is covered with a photoresist film 4A. Then, the region desired to flatten the element isolation insulating film such as, for example, the element forming region 11 of the internal circuit, a thermally oxide film 2 of the region for enhancing the breakdown voltage of the transistor and the silicon substrate 1 are etched. Then, after the films 4, 4A are removed, oxidized, and element isolation oxide films 5A, 5B are formed. Then, a nitride film 3 and a thermally oxide film 2 are removed to form a silicon substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to the structure of an element isolation region.

[0002]

2. Description of the Related Art The element isolation region of a conventional semiconductor integrated circuit has been formed to be substantially flat in order to prevent adverse effects on the subsequent lithography process. This will be described below with reference to FIG.

First, as shown in FIG. 2A, a thermal oxide film 2 is grown to 20 to 60 nm on a silicon substrate 1, and a nitride film 3 is grown to 100 to 300 nm on it by a CVD method. Next, a photoresist film 4 is formed and then patterned to remove the photoresist film in the element isolation region. Next, the photoresist film 4 is used as a mask to etch the nitride film 4, and then the thermal oxide film 2 in the opening and the surface of the silicon substrate 1 are etched to a depth of 40 to 150 nm. Next, as shown in FIG. 2B, after the photoresist film 4 is removed, selective oxidation is performed to form an element isolation oxide film 5A in the opening with a length of 300 to 1000 nm. After that, as shown in FIG. 2C, the nitride film 3 and the thermal oxide film 2 are removed to form a flattened element isolation region made of the oxide film 5A.

[0004]

Since the conventional element isolation region is composed of a flattened oxide film, it is difficult to optically detect (detect) the isolation region at the time of alignment in the next process. Therefore, there is a problem that the alignment accuracy is lowered.

Further, in a semiconductor integrated circuit, a protection circuit is generally inserted between an input terminal and an internal circuit to absorb an overvoltage in order to prevent electrostatic breakdown. This protection circuit has a MOS
An ESD (electrostatic breakdown) protection element using a transistor is used, and a parasitic transistor formed in a peripheral circuit portion is generally used as this transistor. However, since the element isolation oxide film in the conventional semiconductor integrated circuit has one type of structure, the withstand voltage of the parasitic transistor used as the ESD protection element is the same as the withstand voltage of the parasitic transistor formed in the other circuit area, and thus the ESD protection is performed. There has been a problem that the protection capability of the element becomes insufficient and the ESD resistance of the integrated circuit decreases.

An object of the present invention is to provide a semiconductor integrated circuit having improved alignment accuracy and ESD resistance at the time of alignment.

[0007]

A semiconductor integrated circuit according to the present invention is a device including two kinds of insulating films, a first insulating film which is flattened and a second insulating film which has a convex cross-sectional shape and is not flattened. The isolation region is formed, and in particular, the ESD protection element portion is isolated by the second insulating film.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A to 1C are cross-sectional views of a semiconductor chip for explaining an embodiment of the present invention. Hereinafter, description will be made in the order of the manufacturing process.

First, as shown in FIG. 1A, a thermal oxide film 2 having a thickness of 20 to 60 nm is formed on a silicon substrate 1, and then a nitride film 3 having a thickness of 100 to 300 nm is formed by a CVD method. . Next, a photoresist film 4 is formed on the entire surface and then patterned to form an opening in the element isolation region. Next, using the photoresist film 4 as a mask, the exposed nitride film 3 is etched by a dry etching method.
Next, it is desired to lower the breakdown voltage of the parasitic transistor in a region where the insulating film forming the element isolation region is not desired to be flattened, for example, a portion used as a registration detection mark or the peripheral circuit region.
The SD protection element formation region 10 is covered with the photoresist film 4A. Next, the thermal oxide film 2 and the silicon substrate 1 in the region where the element isolation insulating film is to be flattened, for example, the element forming region 11 of the internal circuit or the region where the withstand voltage of the parasitic transistor is desired to be increased from 40 to 40.
Etch to a depth of 150 nm.

Next, as shown in FIG. 1B, the photoresist films 4 and 4A are removed and then oxidized to form element isolation oxide films 5A and 5B. At this time, the element isolation oxide film 5A in the portion where the surface of the silicon substrate 1 is etched is substantially flattened, whereas the cross-sectional shape of the element isolation oxide film 5B in the portion where the silicon substrate 1 is not etched is convex. Becomes

Next, as shown in FIG. 1C, the nitride film 3 and the thermal oxide film 2 are removed to form a silicon substrate having two types of element isolation oxide films. Thereafter, elements and the like are formed in the regions separated by the element isolation oxide films 5A and 5B to complete the semiconductor integrated circuit.

According to the present embodiment having such a configuration, the element isolation oxide film is used for alignment, and the ESD is used.
When it is used as a means for lowering the withstand voltage of a protection element, its cross-sectional shape is formed to be convex to shorten the current path, and the element isolation oxide film is flattened in other areas. Alignment accuracy at the time of alignment is improved without adversely affecting the process.
The breakdown voltage of the SD protection circuit element can be lowered.

[0013]

As described above, according to the present invention, two types of oxide films, that is, a flat oxide film and a convex oxide film, are provided as the element isolation insulating film, so that the element isolation oxide film which is not planarized is provided. Has an effect that the ESD resistance can be improved by improving the alignment accuracy at the time of meshing and by using it in the ESD protection element section in which the withstand voltage of the parasitic transistor is lowered. On the other hand, in the portion having the flattened element isolation oxide film, the margin such as the depth of focus at the time of alignment can be maintained and the withstand voltage of the parasitic transistor can be kept high as in the conventional case.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the invention.

FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a conventional method for manufacturing an element isolation oxide film.

[Explanation of symbols]

 1 Silicon substrate 2 Thermal oxide film 3 Nitride film 4, 4A Photoresist film 5A, 5B Element isolation oxide film 10 ESD element formation area 11 Circuit element formation area

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Reference number in the agency FI Technical display location H01L 27/092 29/78

Claims (2)

[Claims] 1. A semiconductor integrated circuit having an internal circuit region formed on a semiconductor substrate, a peripheral circuit region including an ESD protection element, and an element isolation region for element isolation,
2. The semiconductor integrated circuit according to claim 1, wherein the element isolation region is composed of a flattened first insulating film and a second insulating film having a convex cross section. 2. The semiconductor integrated circuit according to claim 1, wherein the ESD protection element section is separated by a second insulating film.