JP2002050746A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, using an SOI for preventing nonuniformity in coating of a photoresist and disconnection in the step part of metal wiring caused by a sharp step formation, when the step of a silicon active layer and a semiconductor supporting substrate is increased, when forming the opening part of the semiconductor support substrate for forming a protecting element on the semiconductor supporting substrate. SOLUTION: By forming a side spacer, composed of a polycrystal silicon on the sidewall of the step between the silicon active layer and the semiconductor supporting substrate, the form of the step is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to SOI (Silico)
The present invention relates to a semiconductor device using an n On Insulator substrate and having input protection or output protection against excessive current.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, a diode or the like is generally provided between an internal circuit and an external connection terminal to prevent destruction of the internal circuit when an excessive current exceeding a standard such as static electricity is input from the outside. An input protection element or an output protection element using a MOS transistor is provided.
FIG. 2 shows an embodiment of a configuration of an input circuit section of a semiconductor device having an input protection circuit. In FIG.
N-type MOS transistor 9 and P-type MOS as internal circuits
An inverter including the transistor 10 is used. A protection N-type MOS transistor 11 as an input protection element is provided between the inverter and the external input pad 8. With the above configuration, when a negative overvoltage is applied to the external input pad 8, the protection NMOS transistor 11
Becomes a forward direction, and a current flows through the protection transistor 11 to protect the internal circuit. On the other hand, when a positive overvoltage is applied, current flows to the protection MOS transistor by avalanche breakdown of the PN junction of the protection NMOS transistor 11. In this way, the excessive current is directly released to the grounded substrate via the input protection element, so that the excessive current does not flow to the internal circuit.

[0003]

However, in the case of an SO1 substrate, when a protection element is formed on a silicon active layer, an excessive current is directly discharged to a semiconductor supporting substrate by a buried oxide film and a field oxide film as an element isolation. And the surroundings are surrounded by an insulating layer having poor heat dissipation, so that the electrostatic discharge protection element is easily broken by heat generated by an excessive current. Therefore, sufficient electrostatic damage resistance cannot be obtained.

A semiconductor integrated circuit device in which an internal circuit is formed on a silicon active layer and an input protection element or an output protection element is formed on a semiconductor support substrate is disclosed in, for example, JP-A-4-34.
There is one disclosed in Japanese Patent No. 5064. However, when the silicon active layer and the buried oxide film are removed by etching to form a protection element formation region on the semiconductor support substrate, the buried oxide film is removed by RIE.
When the protective element is removed by anisotropic dry etching, damage is caused in the protective element forming region by etching, and the reliability of the protective element is reduced. In addition, when the buried oxide film is removed by isotropic wet etching, since not only the depth direction but also the lateral direction is etched, problems such as peeling of the silicon active layer due to lateral etching of the buried oxide film, An eaves shape is formed below the silicon active layer, and a problem such as a film residue occurs in the eaves-shaped portion in a later step.

Further, in the case of a fully depleted SOIMOS transistor in which the silicon active layer is completely depleted when forming the channel, the silicon active layer and the buried oxide film are etched because the silicon active layer becomes thin.
Even if the photoresist for patterning is coated after forming the opening of the semiconductor support substrate, the influence of steps such as coating unevenness does not appear, but the silicon active layer is not completely depleted at the time of channel formation, and is partially neutralized. In the case of the partially depleted SOIMOS transistor in which the silicon active layer and the buried oxide film become thicker,
When the surface of the semiconductor support substrate is exposed to form the protection element formation region, the step between the silicon active layer and the semiconductor support substrate becomes large. For example, when the silicon active layer thickness is 0.4 μm and the buried oxide film thickness is 0.4 μm, a step close to about 1.0 μm occurs between the silicon active layer after etching and the semiconductor supporting substrate, and the resist coating In such a case, a coating unevenness occurs and a problem that stable production cannot be performed occurs. In addition, since the step is steep, the metal wiring is apt to be cut at the step, thereby lowering the yield.

[0006]

In order to solve the above-mentioned problems, the present invention uses the following means. In a semiconductor device having a semiconductor supporting substrate, a buried oxide film as an insulating film formed on the semiconductor supporting substrate, and an SOI (sicon on insulator) substrate including a silicon active layer formed on the buried oxide film, The silicon active layer and the buried oxide film are removed in a portion on the SO1 substrate, an opening is formed to expose the surface of the semiconductor support substrate, a semiconductor integrated circuit is formed in the silicon active layer, and the input protection element is formed in the semiconductor support substrate. Alternatively, a semiconductor device is provided in which an output protection element is formed and an input protection element or an output protection element is electrically connected between an external connection terminal and the semiconductor integrated circuit.

A semiconductor device is characterized in that the thickness of the silicon active layer forming the semiconductor integrated circuit is 0.2 μm to 0.5 μm.

Further, the buried oxide film thickness is from 0.2 μm to 0.1 μm.
The semiconductor device had a thickness of 5 μm.

Further, a semiconductor device is characterized in that a side spacer made of polycrystalline silicon is formed on a side wall of a step between a silicon active layer and a semiconductor supporting substrate. Further, the semiconductor device is characterized in that the side spacer formed on the side wall of the step portion between the silicon active layer and the semiconductor support substrate has an electrical connection with a ground potential by a metal wiring. The input protection element or output protection element is MO
An S transistor, wherein a drain diffusion layer region of the MOS transistor is electrically connected to an external connection terminal;
A semiconductor device is characterized in that the gate electrode and the source diffusion region of the transistor are grounded on the substrate.

The input protection element or the output protection element is a diode constituted by a PN junction formed by an impurity diffusion layer of the same conductivity type and the opposite conductivity type as the semiconductor support substrate. Electrically connected to the connection terminal,
A semiconductor device is characterized in that the same conductivity type diffusion layer of the PN junction is grounded to the substrate.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device having an input protection element according to one embodiment of the present invention. The same applies to a semiconductor device having an output protection element. In this embodiment, a CMOS comprising an N-type MOS transistor 9 and a P-type MOS transistor 10 on a silicon active layer 3
An inverter is formed, and a protection N-type MOS transistor 11 formed on the semiconductor support substrate 1 is connected between the CMOS inverter and the external input pad 8. For example, when a protection element is formed on a silicon active layer, the periphery is surrounded by an insulator layer, so that the heat capacity is small, and the protection element is easily broken by heat generated by an excessive current. Therefore, a very large protection element is required to secure sufficient heat capacity,
By forming the protection element on the semiconductor support substrate 1 as in the present embodiment, it is possible to form a protection element having a sufficient resistance to electrostatic breakdown at a size equivalent to that of conventional bulk silicon. Further, this embodiment has a structure in which a side spacer 7 made of polycrystalline silicon is formed at a step formed between the silicon active layer 3 and the semiconductor support substrate 1. With this structure, coating unevenness can be prevented when coating the photoresist, and stable production can be achieved.

Next, an example of a manufacturing process of the semiconductor device shown in FIG. 1 will be described with reference to FIG. A buried oxide film 2 having a thickness of 0.2 μm to 0.5 μm is formed on a semiconductor support substrate 1 of a P-type conductivity, and a buried oxide film 2 having a thickness of 0.2 μm to A bonded SO1 substrate having a 0.5 μm P-type silicon active layer 3 is prepared. The thickness of the buried oxide film 2 is determined by the required withstand voltage of the insulating film, and the thickness of the silicon active layer 3 is determined by the required withstand voltage between the source and the drain. Also, a semiconductor support substrate 1 and a silicon active layer 3
May use substrates having different concentrations according to the characteristics of the input protection element and the internal circuit. The conductivity type of the silicon active layer 3 may be N-type. Further, when the silicon active layer 3 and the semiconductor supporting substrate 1 are of the same conductivity type and have the same substrate concentration, a SIMOX substrate may be used.

A photoresist 12 is coated on the SO1 substrate, and a region for forming an input protection element is patterned on the semiconductor support substrate 1 later (FIG. 3A). Using the resist pattern 12 as a mask material, the silicon active layer 3 is etched by RIE anisotropic dry etching until the buried oxide film 2 is exposed (FIG. 3B). Further, using the photoresist 12 as a mask material, the buried oxide film 2 is etched by RIE anisotropic dry etching. At this time, the etching is stopped halfway so that a part remains in the buried oxide film 12 (FIG. 3C). It is preferable to perform etching so that the buried oxide film remaining after the etching has a thickness of 0.05 μm to 0.1 μm. Then, photoresist 1
2 is removed, isotropic wet etching is performed using, for example, buffered hydrofluoric acid to remove the remaining buried oxide film and expose the surface of the semiconductor supporting substrate 1 (FIG. 3).
(D)). By using anisotropic dry etching and isotropic wet etching for removing the buried oxide film in this manner, a region for forming a protection element can be formed without damaging the semiconductor support substrate 1, and By minimizing the lateral etching of the buried oxide film 2, peeling of the silicon active layer 3 can be prevented.

Next, thermal oxidation is performed to form a thermal oxide film 13 on the silicon active layer 3 and the semiconductor support substrate 1. This thermal oxide film thickness is approximately 0.01 μm to 0.04 μm.
Polycrystalline silicon 7 is formed on this thermal oxide film by a low pressure CVD method.
Is deposited (FIG. 3E). At this time, the polycrystalline silicon goes around and deposits under the eaves-shaped portion formed by the lateral etching of the buried oxide film 2 by wet etching. Here, the thickness of the polycrystalline silicon 7 is equal to the depth from the silicon active layer 1 to the semiconductor support substrate 3. Thereafter, the polycrystalline silicon film is etched by RIE anisotropic dry etching until the underlying thermal oxide film is exposed, thereby forming a polycrystalline silicon side spacer on the step side wall of the silicon active layer and the semiconductor supporting substrate ( Fig. 3D: At this time, SF6 is desirable as a reaction gas for anisotropic etching.
Through these steps, it is possible to improve the step shape generated in the formation of the semiconductor support substrate opening. After the above-described steps, the step of forming a MOS transistor on a conventional bulk silicon substrate is performed on the silicon active layer 3 and the semiconductor supporting substrate 1, whereby the configuration shown in FIG. 1 is completed. Although the input protection element is an N-type MOS transistor 11 in FIG. 1, a diode may be used as the protection element.

FIG. 4 is a sectional view showing an embodiment of the input protection element region in FIG. As shown in FIG. 4, the side spacers made of polycrystalline silicon formed on the side wall of the step portion are grounded by the metal wiring through the connection holes so that the side spacers made of polycrystalline silicon become electrically floating. The formation of a parasitic channel can be prevented.

[0016]

According to the present invention, an excessive current can be discharged to the semiconductor supporting substrate, and the electrostatic breakdown resistance is improved.
By improving the shape of the side wall of the step between the silicon active layer and the semiconductor support substrate, stable production can be performed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment of a semiconductor device of the present invention.

FIG. 2 shows an embodiment of an electric connection section showing a configuration of an input circuit section of a semiconductor device having an input protection circuit.

FIG. 3 is a process sectional view showing one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a sectional view showing one embodiment of a protection element region in the semiconductor device of the present invention.

[Explanation of symbols]

 1 P-type semiconductor support substrate 2 buried oxide film 3 P-type silicon active layer 4 gate electrode 5 gate oxide film 6 field oxide film 7 polycrystalline silicon 8 external input pad 9 N-type MOS transistor 10 P-type MOS transistor 11 protection N-type MOS transistor 12 Photoresist 13 Thermal oxide film 14 Metal wiring 15 Interlayer insulating film

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[Procedure amendment]

[Submission date] October 3, 2000 (2000.10.
3)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 1

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0003

[Correction method] Change

[Correction contents]

[0003]

However, in the case of an SOI substrate, when a protection element is formed on a silicon active layer, an excessive current is directly discharged to a semiconductor supporting substrate by a buried oxide film and a field oxide film which is an element isolation. And the surroundings are surrounded by an insulating layer having poor heat dissipation, so that the electrostatic discharge protection element is easily broken by heat generated by an excessive current. Therefore, sufficient electrostatic breakdown resistance cannot be obtained.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

Next, an example of a manufacturing process of the semiconductor device shown in FIG. 1 will be described with reference to FIG. A buried oxide film 2 having a thickness of 0.2 μm to 0.5 μm is formed on a semiconductor support substrate 1 of a P-type conductivity, and a buried oxide film 2 having a thickness of 0.2 μm to A bonded SOI substrate having a 0.5 μm P-type silicon active layer 3 is prepared. The thickness of the buried oxide film 2 is determined by the required withstand voltage of the insulating film, and the thickness of the silicon active layer 3 is determined by the required withstand voltage between the source and the drain. Also, a semiconductor support substrate 1 and a silicon active layer 3
May use substrates having different concentrations according to the characteristics of the input protection element and the internal circuit. Further, the conductivity type of the silicon active layer 3 may be N-type. Further silicon active layer 3
When the semiconductor support substrate 1 and the semiconductor support substrate 1 are of the same conductivity type and have the same substrate concentration, a SIMOX substrate may be used.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction contents]

A photoresist 12 is coated on the SOI substrate, and a region for forming an input protection element is patterned on the semiconductor support substrate 1 later (FIG. 3A). Using the resist pattern 12 as a mask material, the silicon active layer 3 is etched by RIE anisotropic dry etching until the buried oxide film 2 is exposed (FIG. 3B). Further, using the photoresist 12 as a mask material, the buried oxide film 2 is etched by RIE anisotropic dry etching. At this time, the etching is stopped halfway so that a part of the buried oxide film 2 remains (FIG. 3C). It is preferable to perform etching so that the buried oxide film remaining after the etching has a thickness of 0.05 μm to 0.1 μm. Then, the photoresist 12
Is removed, anisotropic wet etching is performed using, for example, buffered hydrofluoric acid to remove the remaining buried oxide film and expose the surface of the semiconductor support substrate 1 (FIG. 3).
(D)). By using the anisotropic dry etch and the isotropic wet etch for removing the buried oxide film as described above, it is possible to form a region for forming a protection element without damaging the semiconductor support substrate 1 and By minimizing the lateral etching of the buried oxide film 2, peeling of the silicon active layer 3 can be prevented.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction contents]

Next, thermal oxidation is performed to form a thermal oxide film 13 on the silicon active layer 3 and the semiconductor support substrate 1. This thermal oxide film thickness is approximately 0.01 μm to 0.04 μm.
Polycrystalline silicon 7 is formed on this thermal oxide film by a low pressure CVD method.
Is deposited (FIG. 3E). At this time, the polycrystalline silicon goes around and deposits under the eaves-shaped portion formed by the lateral etching of the buried oxide film 2 by wet etching. Here, the thickness of the polycrystalline silicon 7 is equal to the depth from the silicon active layer 1 to the semiconductor support substrate 3. Thereafter, the polycrystalline silicon film is etched by RIE anisotropic dry etching until the underlying thermal oxide film is exposed, thereby forming a polycrystalline silicon side spacer on the step side wall of the silicon active layer and the semiconductor supporting substrate ( 3D, at this time, SF ₆ is desirably used as a reaction gas for the anisotropic etching.
Through these steps, it is possible to improve the step shape generated in the formation of the semiconductor support substrate opening. After the above-described steps, the step of forming a MOS transistor on a conventional bulk silicon substrate is performed on the silicon active layer 3 and the semiconductor supporting substrate 1, whereby the configuration shown in FIG. 1 is completed. Although the input protection element is an N-type MOS transistor 11 in FIG. 1, a diode may be used as the protection element.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] Figure 3

[Correction method] Change

[Correction contents]

FIG. 3

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 27/092 H01L 29/78 623A 29/786 F term (Reference) 5F032 AA06 AA09 AA12 BA08 CA07 CA15 CA17 DA03 DA23 DA24 DA25 DA26 DA53 5F038 AV06 BH04 BH07 BH13 EZ06 5F048 AA02 AB06 AC01 AC04 BA01 BA09 BA16 BA19 CC08 CC15 CC19 5F110 AA22 BB04 CC02 DD05 DD13 DD22 GG02 GG12 GG24 NN62 NN66 NN71 NN74 QQ03 QQ17

Claims (7)

[Claims] An SOI (Si) comprising a semiconductor supporting substrate, a buried oxide film as an insulating film formed on the semiconductor supporting substrate, and a silicon active layer formed on the buried oxide film.
a silicon on insulator (IC) substrate, wherein the silicon active layer and the buried oxide film are removed in a part of the SO1 substrate to form an opening exposing a surface of the semiconductor support substrate; A semiconductor integrated circuit is formed in a layer, an input protection element or an output protection element is formed on the semiconductor support substrate, and the input protection element or the output protection element is electrically connected between an external connection terminal and the semiconductor integrated circuit. A semiconductor device characterized in that: 2. The semiconductor device according to claim 1, wherein said silicon active layer forming said semiconductor integrated circuit has a thickness of 0.2 μm to 0.5 μm. 3. The method according to claim 1, wherein said buried oxide film has a thickness of 0.2 μm to 0.1 μm.
The semiconductor device according to claim 1, wherein the thickness is 5 μm. 4. The semiconductor device according to claim 1, wherein a side spacer made of polycrystalline silicon is formed on a side wall of a step between said silicon active layer and said semiconductor support substrate. 5. The semiconductor device according to claim 1, wherein said side spacer formed on a side wall of a step between said silicon active layer and said semiconductor supporting substrate is grounded by a metal wiring. 6. The input protection element or the output protection element is a MOS transistor, a drain diffusion layer region of the MOS transistor is electrically connected to the external connection terminal, and a gate electrode and a source diffusion region of the MOS transistor. 2. The semiconductor device according to claim 1, wherein the substrate is grounded to a substrate. 7. The semiconductor device according to claim 6, wherein the input protection element or the output protection element is a diode formed of a PN junction formed by an impurity diffusion layer of the same conductivity type and the opposite conductivity type as the semiconductor support substrate, and is a reverse conductivity type of the PN junction. 2. The semiconductor device according to claim 1, wherein a diffusion layer is electrically connected to the external connection terminal, and the same conductivity type diffusion layer of the PN junction is grounded to a substrate.