TWI397151B - Fabrication methods for high voltage semiconductor devices - Google Patents

Description

Manufacturing method of high voltage semiconductor device

The present invention relates to a method of fabricating a high voltage semiconductor device, and more particularly to a method of fabricating a high voltage semiconductor device having low leakage current characteristics.

High-voltage component technology is suitable for high-voltage and high-power integrated circuits. One of the conventional high voltage semiconductor devices is a double diffused drain (DDD) CMOS structure, and the other is a laterally diffused MOS (LDMOS) structure. Conventional high voltage semiconductor components are mainly used in component applications above or substantially 18V. The advantages of high-voltage component technology are cost-effective and easily compatible with other processes, and have been widely used in display driver IC components, power supplies, power management, communications, automotive electronics or industrial control.

The 1A-1F diagram is a schematic cross-sectional view showing the steps of the manufacturing method of the conventional high voltage semiconductor device. Referring to FIG. 1A, a semiconductor substrate 10, such as a single crystal germanium substrate, is provided, with a shallow trench isolation region 13 defining a first region 10I and a second region 10II. A high voltage P-type doped well region (HVPW) 12 is formed in the second region 10II and a high voltage N-type doped well region (HVNW) 11 in the first region 10I. Next, a P-type double diffusion drain (PDDD) 15 is formed in the high voltage N-doped well region 11 and forms an N-type double diffusion drain (NDDD) 16 in the high voltage P-type well region 12.

Referring to FIG. 1B, a gate dielectric layer 17 and a polysilicon layer 18 are formed on the semiconductor substrate 10 in a blanket manner. By performing a yellow lithography process, the first gate stack 20a is defined on the first region 10I and the second gate stack 20b on the second region 10II by using a photomask, as shown in FIG. 1C.

Next, referring to FIG. 1D, a gate spacer 23 is formed on the sidewalls of the gate stacks 20a and 20b. For example, the gate spacer 23 may be a tantalum oxide-tantalum nitride-anthracene oxide (ONO) structure, and the thickness of the gate spacer 23 is substantially 0.08 μm. Next, an ion implantation step is performed to implant P-type ions into the P-type double diffusion drain 15 on both sides of the gate stack 20a to form a corresponding P-type heavily doped source/drain Region 25, and N-type ions are implanted in N-type double diffused drains 16 on either side of gate stack 20b, respectively, to form corresponding N-type heavily doped source/drain regions 26.

Next, referring to FIG. 1E, an oxide layer 27 is conformally formed on the semiconductor substrate based on the integration of other high voltage components, and then an etching step E is applied to remove the oxide layer 27 to expose the P-type thick blend. The source/drain region 25 and the N-type heavily doped source/drain region 26. Referring to FIG. 1F, an interlayer dielectric layer (ILD) 30 and a source/drain contact 35 are formed, and other back-end processes are performed to complete the high voltage semiconductor device.

The high-voltage semiconductor device manufactured by the above process steps has a large leakage current under high-voltage driving. For example, when driving at 16.5V, the leakage current I _off is higher than 10E-9A.

An embodiment of the present invention provides a method of fabricating a high voltage semiconductor device, including: providing a semiconductor substrate having a shallow trench isolation region defining a first region and a second region; forming a first doped well region a first doped well region and a second doped well region in the second region; a first type of double diffused drain in the second doped well region and a second type double diffused drain in the first region Doping a well region; forming a gate dielectric layer and a polysilicon layer Forming a polysilicon gate on the first region and the second region; forming a gate spacer on sidewalls of the polysilicon gates; applying an ion implantation step to pass ions through the gate The pole dielectric layers are respectively implanted in the first type double diffusion drain and the second type double diffusion drain to form a corresponding first type dense doped source/drain region and a second type thick Doping a source/drain region; forming an oxide layer on the semiconductor substrate; and removing the oxide layer and the gate dielectric layer underneath to expose the first type of heavily doped source/drain regions And the second type of heavily doped source/drain regions.

Another embodiment of the present invention provides a method of fabricating a high voltage semiconductor device, comprising: providing a semiconductor substrate having a shallow trench isolation region defining a first region and a second region; forming an N-type doped well region The first region and a P-type doped well region are in the second region; forming an N-type double diffusion drain in the P-doped well region and a P-type double diffusion gate N-doping the well region; forming a gate dielectric layer and a polysilicon layer on the semiconductor substrate; forming a polysilicon gate on the first region and the second region; forming a gate spacer on the polysilicon On the sidewall of the gate; an ion implantation step is performed to implant ions through the gate dielectric layer in the N-type double diffusion drain and the P-type double diffusion drain to form corresponding An N-type heavily doped source/drain region and a P-type heavily doped source/drain region; forming an oxide layer on the semiconductor substrate; and removing the oxide layer and the gate thereunder The pole dielectric layer exposes the N-type heavily doped source/drain region and the P-type heavily doped source/drain region.

In order to make the invention more apparent, the following detailed description of the embodiments and the accompanying drawings are as follows:

The following is a detailed description of the embodiments and examples accompanying the drawings, which are the basis of the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and in particular, The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention.

In view of this, the main features and aspects of the present invention are to delay the patterning step of the gate dielectric layer and simultaneously with the step of removing the resistive oxide layer (RPO), thus omitting a mask (HVOR for short) The mask process can effectively reduce manufacturing costs. Furthermore, since the heavily doped source/drain regions are formed in the presence of a gate dielectric layer, the resulting high voltage semiconductor device has a lower leakage current.

2A-2F is a schematic cross-sectional view showing the steps of a method of manufacturing a high voltage semiconductor device according to an embodiment of the present invention. Referring to FIG. 2A, a semiconductor substrate 100, such as a single crystal germanium substrate, a germanium (SOI) substrate or an epitaxial germanium substrate on the insulating layer, having a shallow trench isolation region 130 defining a first region 100I and A second area 100II. Next, a high voltage P-type doping well region (HVPW) 120 is formed in the second region 100II and a high voltage N-type doping well region (HVNW) 110 in the first region 100I. Next, a P-type double diffusion drain (PDDD) 150 is formed in the high voltage N-type well region 110 and an N-type double diffusion drain (NDDD) 160 is formed in the high voltage P-type well region 120. .

Referring to FIG. 2B, a gate dielectric layer 170 and a polysilicon layer 180 are formed on the semiconductor substrate 100 in a blanket manner. By performing a yellow lithography process, a first polysilicon gate 180a is defined on the first region 100I and a second polysilicon gate 180b on the second region 100II by using a mask, such as 2C. As shown, at this stage, the gate dielectric layer 170 still covers the semiconductor substrate 100.

Next, referring to FIG. 2D, a gate spacer 230 is formed on the sidewalls of the polysilicon gates 180a and 180b. For example, the material of the gate spacer 230 may be a tantalum nitride (SiN) structure, and the thickness of the gate spacer 230 is substantially 0.11 μm. Next, ion implantation steps Ia and Ib are applied, and P-type ions are penetrated into the gate dielectric layer 170 and implanted in the P-type double diffusion drain 150 on both sides of the polysilicon gate 180a, respectively. To form a corresponding P-type source/drain region 250, and implant an N-type ion penetrating gate dielectric layer 170 into the N-type double diffusion drain 160 on both sides of the polysilicon gate 180b. To form a corresponding N-type source/drain region 260. It should be noted that the energy and concentration of P-type and N-type ion implantation should be dependent on the thickness of the gate dielectric layer 170 and the design requirements of the heavily doped source/drain regions.

Next, referring to FIG. 2E, a resistive protective oxide layer (RPO) 270 is conformally formed on the semiconductor substrate based on the need to integrate other high voltage components, and then an etching step E is applied to remove the resistive protective oxide layer. 270 and the gate dielectric layer 170 thereunder, and exposing the P-type heavily doped source/drain region 250 and the N-type heavily doped source/drain region 260. Referring to FIG. 2F, an interlevel dielectric (ILD) 300 and source/drain contacts 350 are formed, and other back-end processes are performed to complete the high voltage semiconductor device.

According to the embodiment of the present invention, the high voltage semiconductor device manufactured by the process steps shown in FIG. 2A-2F has a small leakage current under high voltage driving. For example, when driving at 16.5V, the leakage current I _off is smaller than 10E-12A. Moreover, since the patterning step of the gate dielectric layer 170 and the step of removing the resistance protective oxide layer (RPO) 270 are performed simultaneously, a photomask (referred to as HVOR mask) process is omitted, which can effectively reduce The manufacturing cost and the electrical performance of the high voltage semiconductor device are improved by effectively reducing the leakage current.

The present invention has been disclosed in the above various embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10‧‧‧Semiconductor substrate

10I‧‧‧First Area

10II‧‧‧Second area

11‧‧‧High-pressure N-type doping well area (HVNW)

12‧‧‧High-pressure P-type doping well area (HVPW)

13‧‧‧Shallow trench isolation zone

15‧‧‧P-type double diffused bungee (PDDD)

16‧‧‧N-type double diffusion bungee (NDDD)

17‧‧‧ gate dielectric layer

18‧‧‧Polysilicon layer

20a, 20b‧‧‧ first and second gate stacks

23‧‧‧ gate gap

25‧‧‧P-type concentrated doped source/drain region

26‧‧‧N-type concentrated doped source/drain region

27‧‧‧Resist Protective Oxide Layer (RPO)

30‧‧‧Interlayer dielectric layer (ILD)

35‧‧‧Source/bungee contact

100‧‧‧Semiconductor substrate

100I‧‧‧First Area

100II‧‧‧Second area

110‧‧‧High-pressure N-type doping well area (HVNW)

120‧‧‧High-pressure P-type doping well area (HVPW)

130‧‧‧Shallow trench isolation zone

150‧‧‧P-type double diffused bungee (PDDD)

160‧‧‧N-type double diffusion bungee (NDDD)

170‧‧‧ gate dielectric layer

180‧‧‧Polysilicon layer

180a, 180b‧‧‧ first and second polysilicon gates

230‧‧ ‧ gate gap

250‧‧‧P-type concentrated doped source/drain region

260‧‧‧N-type concentrated doped source/drain region

270‧‧‧Resist Protective Oxide Layer (RPO)

300‧‧‧Interlayer dielectric layer (ILD)

350‧‧‧Source/bungee contact

E‧‧‧ etching step

Ia, Ib‧‧‧ ion implantation steps

1A-1F is a schematic cross-sectional view showing steps of a method of manufacturing a conventional high-voltage semiconductor device; and 2A-2F is a schematic cross-sectional view showing steps of a method of manufacturing a high-voltage semiconductor device according to an embodiment of the present invention.

100‧‧‧Semiconductor substrate

100I‧‧‧First Area

100II‧‧‧Second area

110‧‧‧High-pressure N-type doping well area (HVNW)

120‧‧‧High-pressure P-type doping well area (HVPW)

130‧‧‧Shallow trench isolation zone

150‧‧‧P-type double diffused bungee (PDDD)

160‧‧‧N-type double diffusion bungee (NDDD)

170‧‧‧ gate dielectric layer

180a, 180b‧‧‧ first and second polysilicon gates

230‧‧ ‧ gate gap

250‧‧‧P-type concentrated doped source/drain region

260‧‧‧N-type concentrated doped source/drain region

Ia, Ib‧‧‧ ion implantation steps

Claims (8)

A method of fabricating a high voltage semiconductor device, comprising: providing a semiconductor substrate having a shallow trench isolation region defining a first region and a second region; forming a first doped well region in the first region and a first a second doped well region is formed in the second region; forming a first type double diffusion drain in the second doped well region and a second type double diffusion drain in the first doped well region; forming a gate dielectric layer and a polysilicon layer are formed on the semiconductor substrate; a polysilicon gate is formed on the first region and the second region; and a gate gap is formed on sidewalls of the polysilicon gates; And implanting ions through the gate dielectric layer in the first type double diffusion drain and the second type double diffusion drain in an ion implantation step to form a corresponding first type concentrated doping a source/drain region and a second type of heavily doped source/drain region; forming an oxide layer on the semiconductor substrate; and simultaneously removing the oxide layer and the gate dielectric layer a polysilicon gate and a portion covered by the gate spacer to expose the first type of doped The source / drain region and the second type heavily doped source / drain regions. The method of manufacturing a high voltage semiconductor device according to claim 1, wherein the semiconductor substrate comprises a single crystal germanium substrate or a germanium (SOI) substrate on the insulating layer. The method of manufacturing a high voltage semiconductor device according to claim 1, wherein the first doped well region is a high voltage N-type doping well region, and The second doped well region is a high pressure P-type doped well region. The method for manufacturing a high voltage semiconductor device according to claim 1, wherein the first type double diffused germanium is an N-type double diffused drain and the second type double diffused germanium is a P-type double diffused germanium. pole. The method of manufacturing a high voltage semiconductor device according to claim 1, wherein the material of the gate spacer comprises tantalum nitride, and the thickness thereof is substantially equal to or less than 0.11 μm. The method of manufacturing a high voltage semiconductor device according to claim 1, wherein the first source/drain region is an N-type heavily doped source/drain region, and the second source The / drain region is a P-type heavily doped source/drain region. The method of manufacturing a high voltage semiconductor device according to claim 1, wherein the oxide layer comprises a resistance protective oxide layer. A method of fabricating a high voltage semiconductor device, comprising: providing a semiconductor substrate having a shallow trench isolation region defining a first region and a second region; forming an N-type doped well region in the first region and a P-type doped well region is in the second region; forming an N-type double-diffused drain in the P-doped well region and a P-type double-diffused drain in the N-doped well region Forming a gate dielectric layer and a polysilicon layer on the semiconductor substrate; forming a polysilicon gate on the first region and the second region; forming a gate spacer on the sidewall of the polysilicon gate Applying an ion implantation step to ionize the gate dielectric layer separately Entering the N-type double-diffused drain and the P-type double-diffused drain to form a corresponding N-type heavily doped source/drain region and a P-type heavily doped source/汲Forming a resistive protective oxide layer on the semiconductor substrate; and simultaneously removing the resistive protective oxide layer and the portion of the gate dielectric layer that is not covered by the polysilicon gate and the gate spacer The N-type heavily doped source/drain region and the P-type heavily doped source/drain region are exposed.