JPH11274330A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve voltage required for erasing(FTV) of a nonvolatile semiconductor storage device. SOLUTION: When a mini local oxidation of silicon(LOCOS) film 54 is formed on a semiconductor substrate 51, its surface rises, resulting in for example, the formation of first and second slope 2 and 3 and a surface 4. The lower end part of the floating gate 63 is allocated on the surface 4, so that it becomes less acute angle for better voltage for errorless writing(RTV).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to an improvement in the number of times of rewriting information and an improvement in information erasing characteristics of a split gate type flash memory.

[0002]

2. Description of the Related Art In recent years, with the expansion of application fields such as portable telephones and digital still cameras, nonvolatile semiconductor memory devices (EEPROMs;
lly Erasable and Programmable Read Only Memory) is drawing attention. EEPROM records binary or more information depending on whether or not electric charge is accumulated in the floating gate, and reads information by changing the conduction between the source and drain regions depending on the presence or absence of electric charge in the floating gate. A semiconductor memory device, which is roughly classified into a stack gate type and a split gate type.
Among them, the split gate type flash EEPROM is disclosed in, for example, US Pat. Nos. 5,029,130, 5,045,488 and 50.
No. 67108. As shown in FIG. 11, the split gate type flash EEPROM has a semiconductor substrate 1
01 formed at a predetermined interval on drain region 11
A channel region 115 is formed between the source region 3 and the source region 114. A floating gate 109 extending from a part of the channel region 115 to a part of the source region 114 via the gate insulating film 105 is formed, and the upper part and the side part of the floating gate 109 are connected via the tunnel insulating film 110. A control gate 112 that covers and extends over part of the drain region 113 is formed.

[0003] A split gate type flash EEPROM will be described below.
The operation of the OM cell will be described. First, when writing data, a voltage is applied to the control gate 112 and the source region 114 (for example, 2 V to the control gate 112 and 12 V to the source region 114), and a current is caused to flow through the channel region 115 so that thermal electrons are applied to the floating gate 109. Inject and allow to accumulate. When erasing data, no voltage is applied to the drain region 113 and the source region 114, and a voltage (for example, 15
V), the floating gate 10
The electrons stored in 9 are converted to Fowler-Nordheim tunneling current (hereinafter, Fowler-Nordheim tunneling current).
Control gate 11 as FN tunnel current)
Pull out to 2. At this time, since the projection 109a is formed in the peripheral portion above the floating gate 109, the electric field is concentrated here, so that the FN tunnel current can flow at a lower voltage.

The upper left part of FIG. 12 shows a plan view of the above-described split gate flash EEPROM. The split gate flash EEPROM has a plurality of cells described above arranged in a matrix to store a large amount of information. Can be accumulated. FIG. 11 is a cross-sectional view corresponding to line AA. A rectangular element isolation film 10 made of a LOCOS oxide film, which is indicated by a one-dot chain line vertically elongated in one direction on a semiconductor substrate.
4 is formed, and an elliptical floating gate 109 extending from a portion of the element isolation film 104 to a portion of an adjacent element isolation film 104 is formed. A line shown by a solid line extending right and left is the control gate 112. The upper right part and the lower part of FIG. 12 are cross-sectional views in the plan view of the upper left part of FIG. 10, respectively.

A method of manufacturing a conventional split gate type flash EEPROM cell will be described below with reference to FIGS. In each figure, the right side shows a cross-sectional view corresponding to the AA section in FIG. 12, and the left side shows a cross-sectional view corresponding to the BB section in FIG. First, as shown in FIG. 14, a thermal oxidation method or a CVD (Chemical Vapor
A pad oxide film 102 made of a SiO2 film is formed to a thickness of 250 mm by using the r Deposition method.
silicon nitride film 10 which is an oxidation-resistant film using a re-CVD method
3 is formed at 1500 °. The pad oxide film 102 is a thin oxide film formed for the purpose of protecting the substrate surface.

Subsequently, as shown in FIG. 15, the silicon nitride film 103 is etched to form an opening, and a LOCOS (Local Oxidation) is formed using the silicon nitride film 103 as a mask.
The semiconductor substrate 101 is oxidized by the
An element isolation film (LOCOS film) 104 made of an O2 film is formed. At this time, the oxidized region penetrates between the semiconductor substrate 101 and the silicon nitride film 103 to form a bird's beak 104a.
Is formed.

Subsequently, as shown in FIG. 16, the silicon nitride film 103 and the pad oxide film 102 are removed, and the gate insulating film 105 is formed to a thickness of 10 using a thermal oxidation method.
Form at 0 °. Next, a polysilicon film is formed using the LPCVD method.
A first conductive film 106 is formed by implanting P ions over the entire surface. Next, a second silicon nitride film 107, which is an oxidation-resistant film, is formed at 1500 ° by LPCVD.

Next, as shown in FIG. 17, an opening is formed by etching the second silicon nitride film 107, and as shown in FIG. 18, the first silicon nitride film 107 is The conductive film 106 is oxidized and SiO2
A mini LOCOS oxide film 108 made of a film is formed. At this time, the oxidized region is formed between the first conductive film 106 and the silicon nitride film 1.
07, a bird's beak 108 a is formed below the end of the silicon nitride film 107.

Subsequently, as shown in FIG. 19, the silicon nitride film 107 is removed with hot phosphoric acid, and then anisotropic etching is performed using the mini-LOCOS oxide film 108 as a mask to form a floating gate 109. At this time, mini L
Since the bird's beak 108a of OCOS is formed, the upper edge of the floating gate 109 is sharpened along the bird's beak 108a, and the projection 109a is formed.

Further, as shown in FIG. 20, a tunnel insulating film 110 made of a SiO2 film is formed on the entire surface by using a CVD method or a thermal oxidation method to a thickness of 250 to 330 degrees. Next, a polysilicon film is formed on the entire surface to a thickness of 1000 LP using the LPCVD method, and P ions are implanted on the entire surface to form a second conductive film 111. Finally, as shown in FIG. 21, the second conductive film 111
Is etched so as to remain on the floating gate 109 and on the side and a part of the channel region 115 to form the control gate 112. Next, the floating gate 109 and the control gate 112
Is used as a mask, ions of an n-type impurity (arsenic, phosphorus, etc.) are implanted into the semiconductor substrate 101 to form an n-type drain region 11.
3 and an n-type source region 114 are formed. Next, an annealing process is performed to activate the ions implanted into each layer.

As described above, a split gate type flash EEPROM cell is formed.

[0012]

As described above, the protrusion 109a of the floating gate 109 is formed mainly by the mini LOCOS oxide film. In other words, mini LO
Since the bottom surface of the bird's beak 108a of COS has a slope that becomes higher toward the periphery, a sharp protrusion 109a is formed over the entire circumference of the floating gate 109.

As described above, since the protrusion is sharp, an electric field generated between the protrusion and the control gate 112 is concentrated on the sharp portion 118. Thereby, the sharp portion 118 has a function of reducing the applied voltage required when erasing information. However, the voltage required for erasing (hereinafter referred to as FTV)
) Was lower and the highest voltage without erroneous writing needed to be higher, but it was not satisfactory.

[0014]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and, first, is to solve the problem by disposing a lower end of a floating gate on a surface. The lower end of the floating gate affects the voltage at which no erroneous writing occurs, that is, the RTV characteristic. In other words, since the control electrode is covered here with the angle S in FIG. 7, the RTV decreases as the portion corresponding to this angle S (the lower right end of the control gate) becomes sharper,
Getting worse. That is, erroneous writing is easier in S1 and erroneous writing is not in S2. Therefore, in consideration of the RTV characteristics, it is preferable that the lower end of the floating gate be disposed on the uppermost layer 14 or the surface 4.

Second, the problem is solved by arranging the upper end of the floating gate on the slope of the floating gate, which represents the slope of the LOCOS film, and arranging the lower end of the floating gate on the surface. .

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A nonvolatile semiconductor memory device according to an embodiment of the present invention will be described below. However, the position of the end of the floating gate is different from that of the conventional structure.
FIG. 7 illustrates this. In this figure, the dotted line indicates the poly-Si of the floating gate material to be covered in the steps shown in FIGS. As will be described later, the LOCOS film 1 has at least two steps of slopes 2 and 3 depending on the manufacturing method, and where to place the end of the floating gate on the slope will be described below.

Here, the slope has a first slope 2 and a second slope 3 between the periphery V of the LOCOS film 1 and the uppermost surface W of the LOCOS film. It is assumed that there is a surface 4 which is gentler than these slopes (here, a horizontal plane is included as shown in the drawing, so a slope meaning a slope is not intentionally used). In an actual structure, if there are three or more slopes, it can be considered that there is the gentle surface between them. Reference numeral 5 denotes a gate insulating film.

Reference numerals 6 to 11 indicate shapes when the thickness of the poly-Si is changed, and in the drawings, it is shown as if six layers of the same thickness are stacked. For example, if a certain thickness of poly-Si 6 is applied, the slope 12 on this surface moves to the right, though slightly, than the second slope 3. If the film thickness is changed to 7, 8, 9, 10, and 11, the second slope 3 of the LOCOS film is shown as the slope of 13. The floating gate slope 13 that has been projected so far is located above the surface 4.

Here, the floating gate is formed of poly-Si6, the angle of the upper protrusion of the floating gate is T1, and the angle formed between the lower part of the floating gate and the LOCOS film is S1. Further, the angle of the upper protrusion formed by the slope 13 is T2, and the angle formed by the corresponding lower portion of the floating gate and the LOCOS film is S2. As for the voltage required for erasing, that is, the FTV characteristic, it is naturally preferable that the angle T of the protrusion is more acute. Therefore, when the film thickness is small,
Regardless of which slope of the LOCOS film is formed, the angle becomes sharper than that formed on the surface 4 or the uppermost surface 14, so that the erase voltage can be reduced and the FTV characteristics can be improved.

When looking at the upper surface of the floating gate, for example, the uppermost surface 15 of the film 6, this surface shows the slopes 2, 3 and 4 of the LOCOS film 1, so that the slope of the floating gate which shows the slopes 2 and 3 of the LOCOS film. Even if the ends of the floating gates are arranged at 12 and 16, the FTV characteristics can be improved. On the other hand, the lower end of the floating gate affects the voltage at which erroneous writing is not performed, that is, the RTV characteristic. That is, since the control electrode is covered with the angle S, the RTV decreases and deteriorates as the portion corresponding to the angle S (the lower right end of the control gate) becomes sharper.
That is, erroneous writing is easier in S1 and erroneous writing is not in S2. Therefore, in consideration of the RTV characteristics, it is preferable that the lower end of the floating gate be disposed on the uppermost layer 14 or the surface 4.

That is, depending on the element, it is necessary to satisfy both of them. In this case, the upper end of the floating gate focuses on the slope of the upper layer of the floating gate, which reflects the slope of the floating gate, and the lower end of the floating gate It is necessary to pay attention to the flatter surface 4 of the LOCOS film. That is, if the end of the floating gate is arranged at reference numeral 17, the upper end can be located on the slope 13 and the lower end can be located on the surface 14.
Can be arranged.

Of course, the slope angle of the LOCOS film is
Depending on the manufacturing method, the steeper the slope, the thinner the film thickness that satisfies both (here, the film thickness of the films 6 to 11) can be reduced. Further, in principle, the end of the floating gate may be located at any slope of the LOCOS film. However, considering the slope of the surface of the floating gate, not all slopes are acceptable. In other words, here, when the end of the floating gate is located on the slope 18 of the floating gate on which the first slope 2 is projected as shown by the two-dot chain line 19, the lower end of the floating gate is It will be a place. That is, separation by the LOCOS film becomes impossible, and the function as a transistor is lost. Therefore, it is necessary to be located on the slope of the floating gate excluding the slope 18. It is also possible to position the end of the floating gate on the first slope of the LOCOS film. However, referring to FIG. 4, the mini-LOCOS film 59
Must be arranged on the first slope 2. However, the position shift of the oxidation-resistant film 60, the position shift of the mini-LOCOS film, and the etching of poly-Si using the mini-LOCOS film as a mask (over-etching if necessary) In such a case, it is also disposed on the gate insulating film, and the like.
It is considered that the transistor does not function as a transistor.
Therefore, also in this case, the LOCO except for the first slope 2 is used.
It is preferable to be located on the slope of the S film 54.

When the end of the floating gate is disposed on the second slope 3, the RTV characteristic is deteriorated as described above. However, an insulating material such as a spacer is provided at the left end of the floating gate corresponding to the angle S. By providing a film, the lower end of the control gate can be prevented from being sharpened,
Both FTV and RTV can be improved. Now, the manufacturing method will be described with reference to FIGS. This drawing describes the left part of FIGS. 14 to described in the conventional example, and corresponds to a cross-sectional view taken along line BB of FIG.

First, as shown in FIG. 1, a pad oxide film 52 made of SiO 2 is formed on a p-type single crystal semiconductor substrate 51 to a thickness of 250 ° by thermal oxidation. Next, the first oxidation-resistant film
Of silicon nitride film 53 is formed to a thickness of 1500. continue,
The first silicon nitride film 53 is etched using a photoresist (not shown) as a mask to form an opening, and the LOCOS at a temperature of 1000 ° C. is formed using the silicon nitride film 53 as a mask.
An element isolation film (L
An OCOS film 54 is formed to a thickness of 6500 °. At this time, the oxidized region enters between the semiconductor substrate 51 and the silicon nitride film 53, and a bird's beak 55 is formed. The length of the bird's beak varies depending on the oxidation conditions and the quality of the upper and lower films.

Alternatively, poly Si may be stacked on the pad oxide film 52 at about 700 °, a silicon nitride film may be formed thereon, and LOCOS oxidation may be performed. In this case, the bird's beak 55 can be suppressed short by the polysilicon film, and the swelling of the LOCOS film 54 in the opening can be increased. Since the polysilicon film is formed for adjusting the length of the bird's beak as described above, it can be omitted for simplification of the process.

Subsequently, as shown in FIG. 2, the silicon nitride film 53 is removed using hot phosphoric acid, and the pad oxide film 52 is removed. When the poly-Si is formed, the poly-Si is naturally etched. Here, during LOCOS oxidation,
Regardless of the presence or absence of poly-Si, the opening of the oxidation-resistant film 53 rises, so that the first slope 2 and the second slope
Slope 3 and surface 4 are formed. In addition to this method, more slopes may be formed.
Further, depending on the etching, the portion indicated by reference numeral 4 may be deeply etched.

Next, as shown in FIG. 3, a gate insulating film 56 is formed to a thickness of 100 ° by LPCVD. And LPC
A polysilicon film is formed to a thickness of 1500 Å using a VD method, P ions are implanted into the entire surface to form a first conductive film 57, and a second silicon film which is an oxidation-resistant film is formed using a LPCVD method. A nitride film 58 is formed to a thickness of 1000 °. Subsequently, as shown in FIG. 4, using a photoresist (not shown) as a mask, the silicon nitride film 58 is etched to open a region where the mini-LOCOS film 59 is formed. Then, a temperature of 900 ° C. is applied by the mask 60 using the silicon nitride film 58 as an oxidation resistant film.
The first conductive film 57 is oxidized by the LOCOS method to form a mini LOCOS oxide film 59 made of SiO2. At this time, the oxidized region penetrates between the conductive film 57 and the silicon nitride film 60, and a bird's beak 61 is formed below the end of the silicon nitride film 60.

The surface of the coated poly-Si 57 is L
First slope 2 and second slope 3 of OCOS film 54
And the plane 4 are projected, and slopes indicated by points A to E are drawn. Subsequently, as shown in FIG. 5, the silicon nitride film 60 is removed with hot phosphoric acid, and anisotropic etching is performed using the mini-LOCOS oxide film 59 as a mask to form a floating gate 63. At this time, since the bird's beak 61 is formed, the upper end of the floating gate 63 is sharpened along the bird's beak 62, and the projection 62 is formed.

Subsequently, as shown in FIG.
Alternatively, a tunnel insulating film 6 made of SiO2 by a CVD method.
4 is formed, a polysilicon film is formed by LPCVD, and P is doped to form a second conductive film 65 to a thickness of 1000 °. Here, the second conductive film 65 is etched so as to remain on the floating gate 63 and on the side portions and a part of the channel region, thereby forming the control gate 65.
To form Next, using the floating gate 63 and the control gate 65 as a mask,
N-type impurities (arsenic, phosphorus, etc.) are ion-implanted, and an n-type drain region (113 in FIG. 11) and an n-type source region (FIG.
114) is formed. Then, an annealing process is performed to activate the ions implanted into each layer.

In all of the embodiments, the material of each conductive film is described using polysilicon. However, the present invention is not limited to this, and may be amorphous silicon, for example, metal silicide or polycide. The conductivity types of the p-type semiconductor substrate and the n-type source / drain regions may be reversed. Subsequently, the experimental results of FIGS. 9 and 10 will be described. This is obtained by moving the upper end of the floating gate 63 shown in FIG. 8 from the point A to the point E (FIG. 4) at very small intervals (0.1 μm) and measuring the characteristics at that time. That is, the valley on the right side in FIG. 9 corresponds to the arrow D in FIG. 4, and the valley on the left side corresponds to the arrow B in FIG. A portion corresponding to a mountain between valleys corresponds to an arrow C in FIG. On the other hand, the portion corresponding to the mountain in FIG. 10 corresponds to the arrow F in FIG. Therefore, it can be seen from an experiment that the characteristics change depending on the position.

[0031]

As described above, first, by arranging the lower end of the floating gate on the surface, the RTV characteristics can be improved, and erroneous writing can be further prevented. Second, by arranging the upper end of the floating gate on the slope of the floating gate on which the slope of the LOCOS film is photographed, and arranging the lower end of the floating gate on the surface, the FTV characteristic and RT
Both of the V characteristics can be satisfied.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method for manufacturing a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a method for manufacturing a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a method for manufacturing a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 5 is a diagram illustrating a method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 6 is a diagram illustrating a method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating a relationship between a slope of a LOCOS film and a slope of a floating gate.

FIG. 8 is a schematic diagram illustrating the experimental method of FIGS. 9 and 10.

FIG. 9 is a diagram for explaining an FTV characteristic result according to FIG. 8;

FIG. 10 is a diagram for explaining an RTV characteristic result according to FIG. 8;

FIG. 11 illustrates a nonvolatile semiconductor memory device.

FIG. 12 illustrates a nonvolatile semiconductor memory device.

FIG. 13 illustrates a nonvolatile semiconductor memory device.

FIG. 14 is a diagram illustrating a method for manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 15 is a diagram illustrating a method for manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 16 is a diagram illustrating a method for manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 17 is a diagram illustrating a method for manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 18 is a diagram illustrating a method for manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 19 is a diagram illustrating a method for manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 20 is a diagram illustrating a method for manufacturing a conventional nonvolatile semiconductor memory device.

FIG. 21 is a diagram illustrating a method for manufacturing a conventional nonvolatile semiconductor memory device.

Claims (2)

[Claims] 1. A plurality of LOCOS films provided at a predetermined interval on a semiconductor substrate of one conductivity type, and a plurality of LOCOS films are overlapped from a part of the first LOCOS film to a part of an adjacent second LOCOS film. A floating gate, an insulating film covering the floating gate, a control gate disposed on one end of the floating gate through the insulating film, and one of the floating gate and the control gate. In a nonvolatile semiconductor memory device having a source region and a drain region of a reverse conductivity type in which parts are overlapped and formed on the semiconductor substrate, the first LOCOS film and the second LOCOS film are arranged from the periphery. It has a number of consecutive slopes with a gentler or more substantial slope between these slopes Has a surface beveled zero, the lower end portion of the floating gate, the nonvolatile semiconductor memory device characterized in that disposed on the surface. 2. A plurality of LOCOS films provided at predetermined intervals on a semiconductor substrate of one conductivity type, and a plurality of LOCOS films are overlapped from a part of the first LOCOS film to a part of an adjacent second LOCOS film. A floating gate, an insulating film covering the floating gate, a control gate disposed on one end of the floating gate through the insulating film, and one of the floating gate and the control gate. In a nonvolatile semiconductor memory device having a source region and a drain region of a reverse conductivity type in which parts are overlapped and formed on the semiconductor substrate, the first LOCOS film and the second LOCOS film are arranged from the periphery. It has a number of consecutive slopes with a gentler or more substantial slope between these slopes The floating gate formed on the surface has a slope of zero angle, and the floating gate formed thereon has a slope that reflects the slope of the LOCOS film, and the upper end of the floating gate has a slope of the floating gate that captures the slope of the LOCOS film. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is disposed on a slope, and a lower end of the floating gate is disposed on the surface.