JPH11274329A - Manufacture of nonvolatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the erasability of a split gate type flash memory, to increase the number of information rewritable times of the memory, and to reduce the reverse tunneling voltage of the memory. SOLUTION: In a method for manufacturing nonvolatile semiconductor storage device, the projection of a floating gate is made sharper by producing a slope 4', by forming a lower projection 2 composed of a gate insulating film 3 and another film having etching selectivity on a semiconductor substrate and a polysilicon film 4, which becomes the floating gate on the lower projection 2 and putting the end section of a mini-LOCOS(local oxidation silicon) film on the slope 4'. Since, as a result, electric fields are more concentrated, the information written in the storage device can be erased with a lower voltage. Therefore, the erasability of the storage device is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to a method of reducing the erase voltage of a split gate flash memory.
The purpose is to improve the erase characteristics and reduce the reverse tunneling voltage.

[0002]

2. Description of the Related Art In recent years, with the expansion of application fields such as portable telephones and digital still cameras, nonvolatile semiconductor memory devices (EEPROMs;
lly Erasable and Programmable Read Only Memory) is attracting attention. EEPROM records binary or more information depending on whether or not electric charge is accumulated in the floating gate, and reads information by changing the conduction between the source and drain regions depending on the presence or absence of electric charge in the floating gate. A semiconductor memory device, which is roughly classified into a stack gate type and a split gate type. Of these, split gate type flash EEPROM is disclosed in, for example, US Pat. Nos. 5,029,130 and 5,045,488.
No. 5067108. As shown in FIG. 12, the split gate type flash EEPROM has a channel region 11 between a drain region 113 and a source region 114 formed on a semiconductor substrate 101 at predetermined intervals.
5 are formed. A floating gate 109 extending from a part of the channel region 115 to a part of the source region 114 via the gate insulating film 105 is formed, and the upper part and the side part of the floating gate 109 are connected via the tunnel insulating film 110. Cover and drain region 113
The control gate 112 is formed to extend over a part of the gate.

[0003] A split gate type flash EEPROM will be described below.
The operation of the OM cell will be described. First, when writing data, a voltage (for example, 2 V to the control gate 112 and 12 V to the source region 114) is applied to the control gate 112 and the source region 114, and a current is caused to flow through the channel region 115, so that thermal electrons are applied to the floating gate 109. Inject and allow to accumulate. When erasing data, no voltage is applied to the drain region 113 and the source region 114, and a voltage (for example, 15
V), the floating gate 10
The electrons stored in 9 are converted to Fowler-Nordheim tunneling current (hereinafter, Fowler-Nordheim tunneling current).
Control gate 11 as FN tunnel current)
Pull out to 2. Since the projection 109a is formed above the floating gate 109, the electric field is concentrated here, and the FN tunnel current can flow at a lower voltage.

FIG. 13A is a plan view of the above-mentioned split-gate flash EEPROM. In the split-gate flash EEPROM, a plurality of cells described above are arranged in a matrix to store a large amount of information. Can be accumulated. FIG. 12 is a sectional view corresponding to line AA. A rectangle indicated by a vertically long dashed line is an element isolation film 104 formed by the LOCOS method. The elliptical shape shown by the solid line and the dotted line is the floating gate 109. A line shown by a solid line extending right and left is the control gate 112. FIGS. 13B and 13C are cross-sectional views taken along lines AA and BB of FIG. 13A, respectively.

A method of manufacturing a conventional split gate type flash EEPROM cell will be described below with reference to FIGS. In each figure, the right side shows a cross-sectional view corresponding to the AA section in FIG. 13, and the left side shows a cross-sectional view corresponding to the BB section in FIG. First, as shown in FIG. 14A, a pad oxide film 102 made of a SiO2 film is formed on a p-type single-crystal semiconductor substrate 101 by using a thermal oxidation method, and then a LPCVD (Low Pre-
A first silicon nitride film 103, which is an oxidation-resistant film, is formed by using a ssure chemical vapor deposition method.

Next, as shown in FIG. 14B, the silicon nitride film 103 is etched to form an opening, and a LOCOS (Local Oxidat) is formed using the silicon nitride film 103 as a mask.
The semiconductor substrate 101 is oxidized by an ion of silicon method to form an element isolation film 104 made of a SiO2 film. At this time, the oxidized region is formed between the semiconductor substrate 101 and the silicon nitride film 10.
3 and a bird's beak 104a is formed.

Next, as shown in FIG. 14C, the silicon nitride film 103 and the pad oxide film 102 are removed, and the gate insulating film 1 made of SiO 2 is formed by using a thermal oxidation method or a CVD method.
05 is formed. Next, a polysilicon film is formed by using the LPCVD method, and P ions are implanted into the entire surface to form a first conductive film 10.
6, and a second silicon nitride film 107, which is an oxidation-resistant film, is formed by LPCVD.

Next, as shown in FIG. 14D, the silicon nitride film 107 is etched to form an opening. Next, as shown in FIG.
Is used as a mask to oxidize the first conductive film 106 by the LOCOS method to form a mini LOCOS oxide film 108 made of a SiO2 film. At this time, the oxidized region penetrates between the first conductive film 106 and the silicon nitride film 107 to form the silicon nitride film 10.
A bird's beak 108a is formed below the end of the seventh.

Next, as shown in FIG. 15B, the silicon nitride film 107 is removed by hot phosphoric acid,
The floating gate 109 is formed by performing anisotropic etching using the S oxide film 108 as a mask. At this time,
Since the bird's beak 108a is formed, the upper edge of the floating gate 109 is sharpened along the bird's beak 108a, and the projection 109a is formed.

Next, as shown in FIG.
A tunnel insulating film 110 made of a SiO2 film is formed by using a method and a thermal oxidation method. Next, a second conductive film 111 made of a doped polysilicon film is formed by using the LPCVD method. Next, as shown in FIG.
11 is etched so as to remain on the floating gate 109 and on the side and a part of the channel region 115 to form the control gate 112. Next, the floating gate 109 and the control gate 11
2 is used as a mask, ions of an n-type impurity (arsenic, phosphorus, etc.) are implanted into the semiconductor substrate 101 to form an n-type drain region 11.
3 and an n-type source region 114 are formed. Next, an annealing process is performed to activate the ions implanted into each layer. Thus, a split gate flash EEPROM is formed.

[0011]

The conventional split gate type flash EEPROM erases information by utilizing the fact that an electric field is concentrated on the projection 109a of the floating gate 109. In recent years, in order to satisfy the demands such as extension of the use time of portable devices, further lowering of information erasing voltage is required, and it is necessary to emit electrons to the control gate at lower voltage. However, for this purpose, the sharpness of the protrusion 109a cannot be said to be sufficient, and it is necessary to sharpen it further.

[0012]

According to the present invention, there is provided a semiconductor device on a semiconductor substrate.
A lower protrusion made of SiO2 is formed, and a polysilicon film serving as a floating gate is formed thereon to form a polysilicon film having a slope.
This is a method for manufacturing a nonvolatile semiconductor memory device in which an end portion of a COS film is arranged and a polysilicon film is etched using a mini LOCOS film as a mask.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a split gate type flash EEPROM according to a first embodiment of the present invention will be described below. The manufacturing process diagram of this embodiment is a cross-sectional view corresponding to one memory cell transistor portion in the cross section AA in FIG. Step 1: As shown in FIG. 1A, a p-type single crystal semiconductor substrate 1 is thermally oxidized or CVD (Chemical Vapor Deposited).
On), a silicon oxide film (SiO2) film is formed to a thickness of 1000.degree., and a predetermined area is etched back to form the lower protrusion 2. FIG. Step 2: As shown in FIG. 1B, a gate insulating film 3 is formed on the entire surface by using a thermal oxidation method or CVD. Next, the first conductive film 4 made of polysilicon and having a thickness of 4000 .ANG. Is formed on the entire surface by LP (Low Pressure) CVD. An inclined portion 4 ′ is formed on the first conductive film 4 by the lower protrusion 2. The inclination of the inclined portion 4 ′ depends on the height of the lower protrusion 2. Step 3: As shown in FIG. 1C, a silicon nitride film (SiN film) 5 is formed on the entire surface by using LPCVD, and an opening 5 'is formed in a predetermined region. At this time, the lower protrusion 2 of the opening 5 '
Is disposed in the middle or at the lower end of the inclined portion 4 'of the first conductive film. Step 4: As shown in FIG. 1D, a mini-LOCOS film 6 is formed by thermal oxidation using the SiN film 5 as a mask.
An end of the mini LOCOS film 6 enters between the first conductive film 4 and the SiN film 5, and a bird's beak 6 'is formed. The end of the bird's beak 6 ′ facing the lower protrusion 2 is located on the inclined portion 4 ′ of the first conductive film 4. Accordingly, the inclination of the lower surface of the bird's beak 6 'becomes the sum of the inclination of the bird's beak 6' itself and the inclination of the inclined portion 4 ', and thus becomes steeper. Step 5: As shown in FIG. 2A, the SiN film 5 is removed by hot phosphoric acid, and then the first conductive film 4 is etched by anisotropic etching using the mini LOCOS film 6 as a mask. The floating gate 7 is formed. Step 6: As shown in FIG. 2B, the lower protrusion 2 is etched by using a photoresist (not shown) as a mask.
Is removed. At this time, a part of the gate insulating film 3 is removed at the same time as the lower protrusions 2. However, since the tunnel insulating film 8 formed later functions instead, no problem occurs. Next, a tunnel insulating film 8 is formed to a thickness of 300 ° over the entire surface by CVD. Next, a second conductive film 9 is formed on the entire surface by LPCVD to a thickness of 3000 °. Step 7: As shown in FIG. 2C, a predetermined region of the second conductive film 9 is etched to form a control gate 10. Next, ion implantation is performed using the floating gate 7 and the control gate 10 as a mask to form a drain region 11 and a source region 12. Thus, a split gate flash EEPROM is formed.

According to the method for manufacturing a semiconductor memory device of the present invention, the protrusion 7 ′ of the floating gate 7 below the control gate 10 is formed such that the end of the bird's beak 6 ′ is formed by the inclined portion 4 ′ of the first conductive film 4. , The inclination of the lower surface of the bird's beak 6 ′ and the inclination of the inclined portion 4 ′ of the first conductive film 4 are totaled, and compared with the projection 7 ″ on the opposite side of the floating gate 7. And has a steeper slope.

Since the lower protrusion 2 is formed of SiO 2, the material of the lower protrusion 2 and the material of the gate insulating film 3 are the same.
After the lower protrusion 2 is formed, the gate insulating film 3 can be formed immediately before the first conductive film 4 is formed, so that the gate insulating film 3 with good film quality can be obtained. In this embodiment, the lower protrusion 2 is formed of SiO2, but may be formed of a film having etching selectivity with SiO2, for example, SiN. When the lower protrusion 2 is removed in step 6 by forming the lower protrusion 2
Only the gate insulating film 3 can be left selectively. FIG. 3 shows a process chart in the case where the lower protrusion 2 is formed of a SiN film. FIG. 3A: A gate insulating film 3 made of SiO2 is formed on a semiconductor substrate 1, and a lower projection 2 made of SiN is formed. Further, thereafter, the SiO2 exposed by the HF may be removed, and the gate insulating film 3 may be formed again. Thereby, a higher quality gate insulating film 3 can be formed. Incidentally, even in this case, almost no SiO2 is formed on the lower protrusion 2 made of SiN. FIG. 3B: The first conductive film 4 is formed and S having an opening is formed.
An iN film 5 is formed and thermally oxidized to form a mini LOCOS film 6. FIG. 3C: The SiN film 5 is removed, the first conductive film 4 is etched using the mini LOCOS film 6 as a mask to form a floating gate 7, and then the lower protrusion 2 is removed. At this time, since the material of the lower protrusion 2 has an etching selectivity with respect to SiO2, the gate insulating film 3 is not removed. When the gate insulating film 3 is formed again after the formation of the lower projections 2, it is more preferable to remove a slight amount of SiO2 by interposing a light HF treatment before removing the lower projections 2. FIG. 3D: Tunnel insulating film 8 and control gate 1
0 is formed, and source and drain regions 11 and 12 are formed. Thus, a split gate flash EEPROM is formed.

In this embodiment, the lower protrusion 2 may be formed of a film having no etching selectivity with the first conductive film 4, for example, polysilicon or amorphous silicon. By forming with polysilicon etc.
Since the lower protrusion 2 and the first conductive film 4 are integrated, the process 6
Thus, the floating gate 7 can be formed without using a separate removal step. In this case, it is necessary to form the gate insulating film 3 before forming the lower protrusion 2. FIG. 4 shows a process chart in the case where the lower protrusion 2 is formed of a polysilicon film. FIG. 4A: A gate insulating film 3 is formed on a semiconductor substrate 1, and a lower protrusion 2 made of polysilicon is formed. FIG. 4B: The first conductive film 4 is formed and S having an opening is formed.
An iN film 5 is formed and thermally oxidized to form a mini LOCOS film 6. At this time, the lower protrusion 2 and the first conductive film 4 are integrated. FIG. 4C: The floating gate 7 is formed by removing the SiN film 5 and etching the first conductive film 4 using the mini LOCOS film 6 as a mask. FIG. 4D: Tunnel insulating film 8 and control gate 1
0 is formed, and source and drain regions 11 and 12 are formed. Thus, a split gate flash EEPROM is formed.

Next, a second embodiment of the present invention will be described. Normal split gate flash EEPROM is
As shown in FIG. 13B, since the memory cells adjacent to each other in the direction of the element isolation film are formed to be line-symmetric with each other, the adjacent memory cells can be formed so as to share the lower protrusion 2. Even when the lower projection 2 is shared, there is no significant difference from the manufacturing process of the first embodiment. FIG. 5 shows a manufacturing process diagram of this embodiment. As can be seen from the drawing, the lower projection 2 can be formed large by sharing the lower projection 2, so that the lower projection 2 can be formed even if the miniaturization is further advanced, so that the present invention can be implemented. is there. Of course, also in this embodiment,
The material of the lower protrusion 2 has the same options as in the first embodiment. In the following, an example in which a SiN film is used as the material of the lower protrusion 2 will be described, but it is needless to say that the present invention is not limited to this. FIG. 5A: A gate insulating film 3 is formed on a semiconductor substrate 1, a lower projection 2 is formed, and a first conductive film 4 is formed. FIG. 5B: A SiN film 5 having an opening is formed and thermally oxidized to form a mini LOCOS film 6. FIG. 5C: The SiN film 5 is removed, and the first conductive film 4 is etched using the mini LOCOS film 6 as a mask to form a floating gate 7. FIG. 5D: The lower protrusion 2 is removed, and the tunnel insulating film 8 is removed.
A control gate 10 is formed, and source and drain regions 11 and 12 are formed. Thus, a split gate flash EEPROM is formed.

Next, a third embodiment of the present invention will be described. As shown in the prior art split gate flash EEPROM of FIG.
9 extends on the element isolation film 104. In the manufacturing method of the present embodiment, a lower projection is formed on an element isolation film. It should be noted that the process chart for explaining the present embodiment is a cross section different from the process charts of FIGS.
It is sectional drawing equivalent to -B cross section. FIG. 6A: An element isolation film 13 is formed on a semiconductor substrate 1 in the same manner as in the related art. Next, the lower protrusion 2 made of SiO2 is formed on the element isolation film 13. At this time, the end of the lower protrusion 2 is disposed on the inclined portion of the bird's beak 13 ′ of the element isolation film 13 or the upper end thereof. Next, the gate insulating film 3 is formed. FIG. 6B: The first conductive film 4 is formed. At this time, the first conductive film 4 forms a bird's beak 13 ′ of the element isolation film 13.
It has a slope 4 'on the top. Next, a SiN film 5 having an opening is formed. At this time, the end of the opening of the SiN film 5 is
The element isolation film 13 is disposed in the middle of the inclined portion of the bird's beak 13 ′ or at the lower end thereof. Fig. 6 (c): Thermal oxidation using SiN film 5 as a mask
The LOCOS film 6 is formed. The end of the mini LOCOS film 6 is located on the inclined portion of the first conductive film 4 and the device isolation film 13
It is located on the slope. FIG. 6D: The SiN film 5 is removed, and the first conductive film 4 is etched using the mini LOCOS film 6 as a mask to form a floating gate 7. Next, a tunnel insulating film 8 and a control gate 10 are formed, and source and drain regions are formed. (However, the source and drain regions are not shown because they are formed parallel to the plane of the paper.) Thus, the split gate flash EEPROM is formed.

According to the manufacturing method of this embodiment, the first conductive film 4 formed by the lower protrusions 2 is formed in the same manner as in the other embodiments described above.
In addition to the sharpening of the projection 7 ′ of the floating gate 7 by the inclined portion 4 ′, the inclination of the element isolation film 13 is further summed, so that the projection 7 ′ is further sharper than the other embodiments described above. Becomes Further, in this embodiment, since the lower protrusion 2 is formed on the element isolation film 13, if the material of the lower protrusion 2 is SiO2, it is not necessary to remove this material. Of course, the lower protrusion 2 can be formed even with the other materials described above. However, when the lower protrusion 2 is formed of polysilicon, it is preferable that the lower protrusion 2 be removed because electric charges may be unexpectedly accumulated here and a malfunction of the EEPROM may be caused.

According to the present embodiment, the control gate 10 is formed with the projection 10 'facing the floating gate 7. Such a protrusion 10 '
Causes a so-called RT (Reverse Tunneling) phenomenon in which an FN tunnel current flows in the reverse direction due to electric field concentration, which may cause malfunction. In order to prevent this, a sidewall spacer may be formed on the side of the floating gate 7. Further, as shown in FIG. 7, if the element isolation film 13 is formed by the trench method, the projection of the control gate 10 is not formed, and the RTV (Reverse Tunneli) is formed.
ng Voltage). FIG. 7A: A trench having a depth of about 1 μm is formed on the semiconductor substrate 1 at the position of the element isolation film 13 by using a trench method. Next, SiO2 is formed on the entire surface by CVD, and the entire surface is etched back to form an element isolation film 13. Next, the lower protrusion 2 made of SiO2 is formed on the element isolation film 13. FIG. 7B: The first conductive film 4 is formed. Next, a SiN film 5 having an opening is formed. At this time, the end of the opening of the SiN film 5 is disposed in the middle of the inclined portion 4 'of the first conductive film 4 or at the lower end thereof. Fig. 7 (c): Thermal oxidation using the SiN film 5 as a mask is performed
The LOCOS film 6 is formed. The end of the mini LOCOS film 6 is located on the inclined portion 4 ′ of the first conductive film 4. Next, the SiN film 5 is removed. FIG. 7D: The first conductive film 4 is etched using the mini LOCOS film 6 as a mask to form a floating gate 7. Next, a tunnel insulating film 8 and a control gate 10 are formed, and source and drain regions are formed. (However, since the source and drain regions are formed parallel to the paper,
Not shown. Thus, a split gate type flash EEPROM is formed.

The manufacturing method according to the fourth embodiment, in which some of the inventions of the above embodiments are combined, will be described below with reference to FIG.
This will be described with reference to FIGS. The manufacturing method of the present embodiment is an exemplification of a combination of the inventions of the other embodiments described above, and can be implemented by adopting any option of the other embodiments. 8 to 11 are similar to FIG.
(A) is a plan view, (b) is a cross-sectional view taken along line AA, and (c) is a line BB.
FIG. Figure 8: Device isolation film 1 on semiconductor substrate 1 using LOCOS method
Form 3 The element isolation film 13 has an inclined portion 13 '. Next, a gate insulating film 3 is formed to a thickness of 100 に on the entire surface by using a thermal oxidation method or a CVD method. Next, a lower protrusion 2 made of SiN is formed. In the present embodiment, it may be more appropriate to express the lower protrusion 2 as “SiN film 2 having opening 2 ′”. However, in order to ensure consistency with other embodiments, lower protrusion 2 is intentionally used. Write 2. FIG. 9: The first conductive film 4 is formed to a thickness of 3500 on the entire surface by using the CVD method.
Å formed. The first conductive film 4 has an inclined portion 4 ′ formed by the lower protrusion 2. Also, the element isolation film 1
The inclined portion 4 ′ on 3 is formed on the inclined portion of the element isolation film 13. Next, a SiN film 5 having an opening 5 'is formed. The end of the opening 5 ′ is connected to the inclined portion 4 ′ of the first conductive film 4.
Is located in the middle or at the lower end. FIG. 10: Using the SiN film 5 as a mask, the first conductive film 4 is thermally oxidized to form a mini LOCOS film 6. At this time, mini L
The end of the OCOS film 6 is located on the inclined portion 4 ′ of the first conductive film 4. FIG. 11: First conductive film 4 using mini LOCOS film 6 as a mask
Is etched to form a floating gate 7.
At this time, the floating gate 7 is formed with a sharp projection 7 ′ in which the slopes 4 ′ of the first conductive film 4, the bird's beak of the mini LOCOS film 6, and the bird's beak of the element isolation film 13 are summed. ing. Next, lower projection 2
Then, a tunnel insulating film 8 is formed to a thickness of 300 ° over the entire surface by using the CVD method, and a control gate 10 is formed. Next, ion implantation is performed using the floating gate 7 and the control gate 10 as a mask to form a drain region 11 and a source region 12. Thus, a split gate flash EEPROM is formed.

[0022]

According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, the inclined portion 4 'is formed in the first conductive film 4 by the lower protrusion 2, and the end of the mini-LOCOS film 6 is disposed here. Therefore, the projection 7 'of the floating gate 7 can be formed more steeply. Therefore, since the electric field can be more concentrated on the protrusion 7 ', information can be erased at a lower voltage, and the erase characteristics are improved.

In particular, according to the manufacturing method of the second aspect,
Since the lower protrusion is made of a gate insulating film and a film having etching selectivity such as SiN, for example, it is possible to prevent the gate insulating film from being simultaneously removed in the step of removing the lower protrusion. In particular, according to the manufacturing method of the third aspect, the lower protrusion is made of a film having no etching selectivity with the first conductive film, for example, the same material as the first conductive film. The lower protrusion can be removed together with the formation of the floating gate without providing a separate step of removing.

In particular, according to the manufacturing method of the fourth aspect,
Since the lower protrusion is shared by the adjacent nonvolatile semiconductor memory cells with the control gate facing the same, the lower protrusion can be formed large, and the present invention can be carried out even if it is further miniaturized. According to a fifth aspect of the present invention, there is provided a method of forming a lower projection on an element isolation film.

In particular, according to the manufacturing method of the sixth aspect,
Since the element isolation film is formed by the LOCOS method, it has an inclined portion formed by bird's beak, and the inclined portion of the first conductive film and the end of the mini-LOCOS film are arranged here. Can be formed more sharply, so that the erase voltage can be further reduced and the erase characteristics can be further improved. In particular, according to the manufacturing method of the seventh aspect, since the sidewall spacer is formed on the side of the floating gate, the protrusion 10 'is not formed on the control gate 10, and the reverse tunneling phenomenon can be prevented.

[0026] In particular, according to the manufacturing method of claim 8,
Since the element isolation film is formed by the trench, the projection 10 'is not formed on the control gate 10, and the reverse tunneling phenomenon can be prevented. As described above, by combining the features of the manufacturing method described in each claim, a nonvolatile semiconductor memory device having a sharp projection can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a manufacturing process of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a sectional view illustrating a manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing process when the lower protrusion is formed of SiN in the manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing process when the lower protrusion is formed of polysilicon in the manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a sectional view illustrating a manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 6 is a sectional view illustrating a manufacturing process of the nonvolatile semiconductor memory device according to the third embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining a manufacturing process in a case where an element isolation film is formed by a trench in the manufacturing process of the nonvolatile semiconductor memory device according to the third embodiment of the present invention.

FIG. 8 is a diagram illustrating a manufacturing process of the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 9 is a diagram illustrating a manufacturing process of the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 10 is a diagram illustrating a manufacturing process of the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 11 is a diagram illustrating a manufacturing process of the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 12 is a sectional view of a conventional nonvolatile semiconductor memory device.

FIG. 13 is a diagram of a conventional nonvolatile semiconductor memory device.

FIG. 14 is a sectional view illustrating a manufacturing process of a conventional nonvolatile semiconductor memory device.

FIG. 15 is a cross-sectional view illustrating a manufacturing step of a conventional nonvolatile semiconductor memory device.

Claims (8)

[Claims] A step of forming a lower protrusion directly on a semiconductor substrate or via a gate insulating film; and a step of forming the lower protrusion on the semiconductor substrate via the lower protrusion and the gate insulating film. Forming a first conductive film having an opening; forming an oxidation-resistant film having an opening in a predetermined region on the first conductive film; and forming the first conductive film using the oxidation-resistant film as a mask Forming a mini-LOCOS film having an end on the inclined portion, removing the oxidation-resistant film, and etching the first conductive film using the mini-LOCOS film as a mask to form a floating film. A step of forming a gate, a step of forming a tunnel insulating film over the entire surface, and a step of forming a second conductive film over the entire surface and etching a predetermined region of the second conductive film to form a control gate That Method of manufacturing a nonvolatile semiconductor memory device according to symptoms. 2. The method according to claim 1, wherein the lower protrusion comprises the gate insulating film and a film having an etching selectivity. 3. The method according to claim 1, wherein the lower protrusion is made of the first conductive film and a film having no etching selectivity. 4. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the lower protrusion is shared by adjacent nonvolatile semiconductor memory device cells with the control gate opposed thereto. 5. A step of forming an element isolation film and a gate insulating film on a semiconductor substrate, a step of forming a lower projection on the element isolation film, and forming the lower projection and the gate insulating film on the semiconductor substrate. Forming a first conductive film having an inclined portion derived from the lower projection through the first conductive film;
Forming an oxidation-resistant film having an opening in a predetermined region on the conductive film, and oxidizing the first conductive film using the oxidation-resistant film as a mask, and forming a mini-LOCOS having an end on the inclined portion.
Forming a film, and removing the oxidation-resistant film;
Forming a floating gate by etching the first conductive film using the mini-LOCOS film as a mask;
A non-volatile memory comprising: a step of forming a tunnel insulating film over the entire surface; and a step of forming a second conductive film over the entire surface and etching a predetermined region of the second conductive film to form a control gate. A method for manufacturing a semiconductor storage device. 6. The device isolation film is formed by thermal oxidation using an oxidation-resistant film as a mask, and has an inclined portion formed by bird's beak, and an end of the mini-LOCOS film has an inclined portion of the first conductive film. 6. The method for manufacturing a nonvolatile semiconductor memory device according to claim 5, wherein the non-volatile semiconductor storage device is located on a portion and on an inclined portion of the element isolation film. 7. The method for manufacturing a nonvolatile semiconductor memory device according to claim 6, further comprising a step of forming a sidewall spacer on a side portion of said floating gate. 8. The device isolation film forms a trench,
6. The method according to claim 5, wherein the trench is formed by filling the trench with an insulating film.