JP2008182118A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device comprising both regions of a logic power circuit region and a power circuit region on the same semiconductor substrate in which an increase in power consumption in the power circuit region can be inhibited while a high integration is maintained in the logic circuit region, and to provide a manufacturing method therefor. <P>SOLUTION: In the logic circuit 10, a recessed LOCOS oxide film 45 is employed that is formed such that an upper surface thereof is flush with the upper surface of the semiconductor substrate 30 and that insulates a p-type MOS transistor element from an n-type MOS transistor element which constitute a CMOS transistor element. In contrast, in the power circuit 20, a LOCOS oxide film 56 is employed that is formed by selectively oxidizing the surface of the semiconductor substrate 30 and that insulates a drain region 51 and a gate electrode 57 which constitute a horizontal MOS transistor element. In this manner, insulating films for separating elements are separately manufactured for the logic circuit 10 and the power circuit 20. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In semiconductor devices, LOCOS (local oxidation of silicon) is often used as a field oxide film for isolating elements. In such a LOCOS technology, an oxide film made of, for example, silicon oxide (SiO 2) is formed on the upper surface of a semiconductor substrate made of, for example, silicon (Si). A mask made of, for example, silicon nitride (Si3N4) having oxidation resistance is selectively formed on the upper surface of the oxide film. Then, a portion of the upper surface of the semiconductor substrate that is not covered with the mask is locally thermally oxidized to form LOCOS.

  By the way, during such thermal oxidation, oxygen may enter under the edge of the silicon nitride film used as a mask, and thermal oxidation may proceed in the direction along the surface of the semiconductor substrate. As a result, a so-called bird's beak is formed under the edge of the silicon nitride film. Since the bird's beak spreads in the lateral direction, the integration of the semiconductor device is hindered.

Therefore, conventionally, with a design rule of, for example, 0.35 μm or less, a recess that suppresses lateral spread by forming the upper surface so as to be flush with the semiconductor substrate, as in the technique described in Patent Document 1, for example. LOCOS and STI (shallow trench isolation) in which an oxide film is buried in a shallow groove formed on the surface of a semiconductor substrate are employed.
Showa 64-9639

  Thus, since the recess LOCOS and the STI have a bird's beak angle larger than that of a general LOCOS, the lateral spread can be suppressed. Can be planned.

  However, a logic circuit region in which a logic circuit including a CMOS transistor element is formed and a power circuit region in which a power circuit including a lateral MOS transistor element is formed are formed in the surface layer portion of the same semiconductor substrate. If the recess LOCOS or STI is used as it is for a so-called composite semiconductor device, the following problems may occur.

  That is, in the power circuit region including, for example, a lateral MOS transistor element, when the recess LOCOS or STI is adopted due to its structure, the bird's beak angle is large, so that the current flow path becomes longer or the current flow direction is The on-resistance value increases, such as a sudden change. Such an increase in the on-resistance value has a great influence on the power consumption in the power circuit area. Therefore, it is necessary to increase the area of the power circuit region in order to reduce the on-resistance value. As described above, when the recesses LOCOS and STI are applied as they are to a so-called composite semiconductor device, it is difficult to achieve high integration of the semiconductor device.

  The present invention has been made in view of such circumstances, and an object of the present invention is to achieve a high degree of integration in the logic circuit region with respect to a semiconductor device having both the logic circuit region and the power circuit region on the same semiconductor substrate. An object of the present invention is to provide a semiconductor device capable of suppressing an increase in power consumption in a power circuit region while maintaining the same, and a manufacturing method thereof.

  In order to achieve such an object, according to the first aspect of the present invention, a logic circuit region in which a logic circuit including a CMOS transistor element is formed and a power circuit in which a power circuit including a lateral MOS transistor element is formed are provided. As a semiconductor device in which the circuit region is formed on the surface layer portion of the same semiconductor substrate, of the angles formed by the direction along the side surface of the element isolation insulating film of the power circuit and the direction along the surface of the semiconductor substrate The angle between the direction along the side surface of the element isolation insulating film of the logic circuit and the direction along the surface of the semiconductor substrate, which is the smaller angle, is the bird's beak angle of the element isolation insulating film of the power circuit. Of these two circuits so that the smaller one of them is smaller than the bird's beak angle of the element isolation insulating film of the logic circuit. It was decided to release insulating film is divided into build.

  Here, when the bird's beak angle is decreased, the end portion of the insulating film for element isolation becomes gentler, so that the on-resistance value decreases, for example, the current flow path becomes shorter and the current flow direction becomes closer to a straight line. . In other words, power consumption can be reduced. By the way, as the bird's beak angle increases, the edge of the element isolation insulating film becomes steeper, so that the lateral expansion of the element isolation insulating film is suppressed, and the area of the element isolation insulating film on the surface of the semiconductor substrate is Get smaller. In other words, high integration of the semiconductor device can be achieved.

  Therefore, according to the above configuration as the semiconductor device, both of these circuits are configured such that the bird's beak angle of the element isolation insulating film in the power circuit region is smaller than the bird's beak angle of the element isolation insulating film in the logic circuit region. Therefore, the increase in power consumption in the power circuit region can be suppressed while maintaining a high degree of integration in the logic circuit region.

  Specifically, in the configuration according to claim 1, for example, as in the invention according to claim 2, the element isolation insulating film of the power circuit is formed by selectively oxidizing the surface of the semiconductor substrate. The LOCOS oxide film that insulates the gate electrode and the drain region constituting the lateral MOS transistor element, and the upper surface of the element isolation insulating film of the logic circuit is flush with the surface of the semiconductor substrate. The recess LOCOS oxide film that insulates the p-type MOS transistor element and the n-type MOS transistor element that constitute the CMOS transistor element from each other may be used.

  Alternatively, in the configuration according to claim 1, for example, as in the invention according to claim 3, the element isolation insulating film of the power circuit is formed by selectively oxidizing the surface of the semiconductor substrate. A LOCOS oxide film that insulates the gate electrode and drain region constituting the lateral MOS transistor element, and the element isolation insulating film of the logic circuit has an oxide film embedded in a groove formed on the surface of the semiconductor substrate. The formed STI may insulate the p-type MOS transistor element and the n-type MOS transistor element that constitute the CMOS transistor element.

  The bird's beak angle of the element isolation insulating film generally has a relationship of “normal LOCOS oxide film <recess LOCOS oxide film <STI”. In the second aspect of the present invention, a normal LOCOS oxide film is employed as the element isolation insulating film of the power circuit, and a recess LOCOS oxide film is employed as the element isolation insulating film of the logic circuit. Therefore, the bird's beak angle of the element isolation insulating film in the power circuit region is smaller than the bird's beak angle of the element isolation insulating film in the logic circuit region.

  Similarly, in the third aspect of the invention, a normal LOCOS oxide film is employed as the element isolation insulating film of the power circuit, and STI is employed as the element isolation insulating film of the logic circuit. Therefore, the bird's beak angle of the element isolation insulating film is smaller in the power circuit region than in the logic circuit region. Therefore, according to the configuration described in claims 2 and 3, it is possible to suppress an increase in power consumption in the power circuit area while maintaining a high degree of integration in the logic circuit area.

  Further, in the configuration according to claim 1, as in the invention according to claim 4, for example, the element isolation insulating film of the power circuit is deposited and patterned on the surface of the semiconductor substrate through chemical vapor deposition. In addition, an insulating film that insulates a gate electrode and a drain region constituting the lateral MOS transistor element, and the element isolation insulating film of the logic circuit is formed so that an upper surface thereof is flush with the surface of the semiconductor substrate. The recess LOCOS oxide film that insulates the p-type MOS transistor element and the n-type MOS transistor element constituting the CMOS transistor element may be used.

  Alternatively, in the configuration according to claim 1, as in the invention according to claim 5, the element isolation insulating film of the power circuit is deposited and patterned on the surface of the semiconductor substrate through chemical vapor deposition. Further, the insulating film for insulating the gate electrode and the drain region constituting the lateral MOS transistor element, and the insulating film for element isolation of the logic circuit has an oxide film embedded in a groove formed on the surface of the semiconductor substrate. It is good also as STI which insulates the p-type MOS transistor element and n-type MOS transistor element which comprise the said CMOS transistor element, and was formed.

  In the invention described in claim 4, an insulating film deposited through so-called CVD is employed as the element isolation insulating film of the power circuit, and a recess LOCOS oxidation film is used as the element isolation insulating film of the logic circuit. A membrane is adopted. The insulating film deposited through CVD is patterned so as to be smaller than the bird's beak angle of the recess LOCOS oxide film. Similarly, in the invention according to the fifth aspect, an insulating film deposited through so-called CVD is employed as the element isolation insulating film of the power circuit, and as the element isolation insulating film of the logic circuit, STI is adopted. The insulating film deposited through CVD is patterned so as to be smaller than the bird's beak angle of STI. Therefore, even with the configuration described in claims 4 and 5, an increase in power consumption in the power circuit region can be suppressed while maintaining a high degree of integration in the logic circuit region.

  Particularly, in the invention according to claim 4 or 5, as in the invention according to claim 6, for example, between the upper surface of the source region and the upper surface of the drain region constituting the lateral MOS transistor element, A step for reducing the on-resistance value between these two regions may be formed. As a result, the area in which the channel current flowing between these two regions can flow can be increased, so that the on-resistance value can be further reduced and an increase in power consumption in the power circuit region can be further suppressed. become.

  On the other hand, in order to achieve the above object, in the invention described in claim 7, a logic circuit region including a CMOS transistor element is formed therein, and a power circuit including a lateral MOS transistor element is formed therein. As a method for manufacturing a semiconductor device in which the power circuit region is formed on the surface layer portion of the same semiconductor substrate, the direction along the side surface of the element isolation insulating film of the power circuit and the direction along the surface of the semiconductor substrate The bird's beak angle of the insulating film for element isolation of the power circuit, which is the smaller one of the angles formed by the power circuit, is along the side surface of the insulating film for element isolation of the logic circuit and along the surface of the semiconductor substrate. This is smaller than the bird's beak angle of the element isolation insulating film of the logic circuit, which is the smaller one of the angles formed by the two directions. It was decided to divide build isolation insulating film Luo both circuits.

  Here, as described above, when the bird's beak angle is reduced, the end portion of the element isolation insulating film becomes smoother, so that the current flow path is shortened, the current flow direction is close to a straight line, etc. The on-resistance value is reduced. In other words, power consumption can be reduced. Incidentally, when the bird's beak angle is increased, the edge of the element isolation insulating film becomes steeper, so that the lateral expansion of the element isolation insulating film is suppressed, and the area of the element isolation insulating film occupying the surface of the semiconductor substrate Becomes smaller. In other words, high integration can be achieved.

  Therefore, according to the above method as a method for manufacturing a semiconductor device, both of the bird's beak angles of the element isolation insulating film in the power circuit region are smaller than the bird's beak angle of the element isolation insulating film in the logic circuit region. Since the circuit element isolation insulating film is manufactured separately, it is possible to manufacture a semiconductor device capable of suppressing an increase in power consumption in the power circuit region while maintaining high integration in the logic circuit region. .

  Specifically, in the method according to claim 7, for example, as in the invention according to claim 8, the element isolation insulating film of the power circuit is selectively oxidized through the surface of the semiconductor substrate. A LOCOS oxide film that insulates a gate electrode and a drain region constituting a lateral MOS transistor element is formed, and an upper surface of the logic circuit element isolation insulating film is flush with the surface of the semiconductor substrate. A recess LOCOS oxide film that insulates the p-type MOS transistor element and the n-type MOS transistor element constituting the CMOS transistor element may be formed.

  Alternatively, in the method according to claim 7, as in the invention according to claim 9, for example, the lateral MOS transistor can be used as an element isolation insulating film of the power circuit through selective oxidation of the surface of the semiconductor substrate. By forming a LOCOS oxide film that insulates a gate electrode and a drain region constituting an element, and burying an oxide film in a groove formed on the surface of the semiconductor substrate as an element isolation insulating film of the logic circuit, An STI that insulates the p-type MOS transistor element and the n-type MOS transistor element that constitute the CMOS transistor element may be formed.

  As described above, the bird's beak angle of the element isolation insulating film has a relationship of “normal LOCOS oxide film <recess LOCOS oxide film <STI”. In the invention described in claim 8, a normal LOCOS oxide film is employed as the element isolation insulating film of the power circuit, and a recess LOCOS oxide film is employed as the element isolation insulating film of the logic circuit. Therefore, the bird's beak angle of the element isolation insulating film is smaller in the power circuit region than in the logic circuit region. Similarly, in the invention described in claim 9, a normal LOCOS oxide film is employed as the element isolation insulating film of the power circuit, and STI is employed as the element isolation insulating film of the logic circuit. Therefore, the bird's beak angle of the element isolation insulating film is smaller in the power circuit region than in the logic circuit region. Therefore, according to the methods of claims 8 and 9, it is possible to manufacture a semiconductor device capable of suppressing an increase in power consumption in the power circuit region while maintaining a high degree of integration in the logic circuit region. . Moreover, such a semiconductor device can be manufactured using a general manufacturing method without using a special manufacturing method.

  Further, in the method according to claim 7, as in the invention according to claim 10, for example, a gate constituting the lateral MOS transistor element through chemical vapor deposition as an element isolation insulating film of the power circuit. An insulating film that insulates the electrode from the drain region is deposited on the surface of the semiconductor substrate, and as an insulating film for element isolation of the logic circuit, the upper surface thereof is flush with the surface of the semiconductor substrate. A recess LOCOS oxide film that insulates the p-type MOS transistor element and the n-type MOS transistor element constituting the CMOS transistor element may be formed.

  Alternatively, in the method according to claim 7, as in the invention according to claim 11, for example, as a device isolation insulating film of the power circuit, a gate constituting the lateral MOS transistor device through chemical vapor deposition. An insulating film that insulates the electrode from the drain region is deposited on the surface of the semiconductor substrate, and an oxide film is embedded in a groove formed on the surface of the semiconductor substrate as an insulating film for element isolation of the logic circuit. Then, an STI that insulates the p-type MOS transistor element and the n-type MOS transistor element that constitute the CMOS transistor element may be formed.

  In the invention described in claim 10, an insulating film is formed through so-called CVD as an element isolation insulating film of the power circuit, and a recess LOCOS oxide film is formed as an element isolation insulating film of the logic circuit. is doing. The insulating film formed through the CVD is patterned so as to be smaller than the bird's beak angle of the recess LOCOS oxide film. Similarly, in the invention described in claim 11, an insulating film is formed through so-called CVD as an element isolation insulating film of the power circuit, and STI is adopted as an element isolation insulating film of the logic circuit. is doing. The insulating film formed through CVD is patterned so as to be smaller than the STI bird's beak angle. Therefore, the method according to claims 10 and 11 can also manufacture a semiconductor device capable of suppressing an increase in power consumption in the power circuit region while maintaining a high degree of integration in the logic circuit region. Moreover, such a semiconductor device can be manufactured using a general manufacturing method without using a special manufacturing method.

  In particular, in the invention according to claim 10 or 11, as in the invention according to claim 12, for example, between the upper surface of the source region and the upper surface of the drain region constituting the lateral MOS transistor element, A step for reducing the on-resistance value between these two regions may be formed. As a result, the area in which the channel current flowing between these two regions can flow can be increased, so that the on-resistance value can be further reduced and an increase in power consumption in the power circuit region can be further suppressed. become.

(First embodiment)
A first embodiment of a semiconductor device according to the present invention will be described below with reference to FIG. FIG. 1 is a side sectional view of the semiconductor device according to the first embodiment.

  As shown in FIG. 1, the semiconductor device 1 according to the present embodiment basically includes a logic circuit region in which a logic circuit 10 including CMOS transistor elements is formed and a power circuit including lateral MOS transistor elements. A power circuit region 20 is formed in the surface layer portion of the same semiconductor substrate 30.

  Specifically, as shown in FIG. 1, the logic circuit 10 includes, for example, a low-concentration P-type P well 40 inside an N-type semiconductor substrate 30, and a surface layer portion (that is, P) of the semiconductor substrate 30. In the well 40), two N-type impurity regions are formed apart from each other. One of these impurity regions functions as the drain region 41 of the p-channel MOS transistor element, and the other functions as the source region 42 of the p-channel MOS transistor element. The drain electrode 46 is formed using a metal such as aluminum (Al) so as to be in contact with the upper surface of the drain region 41, and the source electrode 47 is also made of aluminum (so as to be in contact with the upper surface of the source region 42. It is formed using a metal such as Al). A gate electrode 43 covered with an insulating film 44 is formed of, for example, polycrystalline silicon on the upper surface of the semiconductor substrate 30 located between the drain region 41 and the source region 42. This electrode 43 functions as the gate electrode of the p-channel MOS transistor element. Thus, by forming “drain region 41 / gate electrode 43 / source region 42”, a p-channel MOS transistor element is configured in the logic circuit region of the semiconductor substrate 30. Although not shown, an n-channel MOS transistor element is also configured in the logic circuit region of the semiconductor substrate 30 in the same manner. These p-channel MOS transistor elements and n-channel MOS transistor elements are combined to form a CMOS transistor element. As shown in FIG. 1, the logic circuit region of the semiconductor substrate 30 has an upper surface that is flush with the upper surface of the semiconductor substrate 30 as an element isolation insulating film for electrically isolating such elements. A recess LOCOS oxide film 45 is formed so as to be within the range. The recess LOCOS oxide film 45 will be described later.

  On the other hand, in the power circuit 20, as shown in FIG. 1, an N-type high-concentration impurity region is formed in the surface layer portion of the semiconductor substrate 30, and this impurity region is the drain region 51 of the lateral MOS transistor element. Function as. A drain electrode 58 is formed using a metal such as aluminum (Al) so as to be in contact with the upper surface of the drain region 51. Similarly, two N-type impurity regions are formed at positions spaced from the drain region 51 in the surface layer portion of the semiconductor substrate 30, and these impurity regions function as the source region 52 of the lateral MOS transistor element. To do. A source electrode 59 is formed on the upper surface of the source region 52 using a metal such as aluminum (Al). In the surface layer portion of the semiconductor substrate 30, a P-type low-concentration impurity region and a P-type high-concentration impurity region located between the drain region 51 and the source region 52 are formed in the channel of the lateral MOS transistor element. Functions as regions 53 and 54. Further, as shown in FIG. 1, over the channel regions 54 and 53, an insulating material such as silicon oxide (SiO 2) is used to form a gate insulating film 55 and a LOCOS oxide film 56 as an element isolating insulating film. The gate electrode 57 is formed using a conductive material such as polycrystalline silicon through the gate insulating film 55 and the LOCOS oxide film 56. The LOCOS oxide film 56 will be described later.

  As described above, the semiconductor device 1 is a so-called composite semiconductor device including a logic circuit and a power circuit in the surface layer portion of the same semiconductor substrate. In such a composite semiconductor device, a recess LOCOS or STI having a bird's beak angle smaller than that of a normal LOCOS oxide film can be simply adopted as an insulating film for element isolation in order to achieve high integration. The inventors have confirmed that this problem occurs. This point will be further described with reference to FIGS. 2A to 2C are side cross-sectional views showing bird's beak angles in addition to a normal LOCOS oxide film, a recess LOCOS oxide film, and an STI.

  A normal LOCOS oxide film as shown in FIG. 2A is formed as follows, for example, as described in the background art section. That is, first, an oxide film made of silicon oxide is formed on the upper surface of a semiconductor substrate made of silicon. Next, a mask made of silicon nitride having oxidation resistance is selectively formed on the upper surface of the oxide film, and a portion of the upper surface of the semiconductor substrate that is not covered with the mask is locally thermally oxidized. The During such thermal oxidation, oxygen enters under the edge of the silicon nitride film used as a mask, and thermal oxidation proceeds in a direction along the surface of the semiconductor substrate. Therefore, as shown in FIG. 2A, the LOCOS oxide film has a shape like a bird's beak. In this figure, the smaller angle α of the angle formed by the straight line along the side surface of the LOCOS oxide film and the straight line along the surface on the semiconductor substrate is the bird's beak angle of a normal LOCOS oxide film. Therefore, it is about “30 degrees”.

  Further, the recess LOCOS oxide film as shown in FIG. 2B is basically formed according to a normal LOCOS oxide film. However, after a mask made of silicon nitride is selectively formed on the upper surface of the oxide film, the periphery of the mask is shallowly removed by etching and is not covered by the mask on the upper surface of the removed semiconductor substrate. The part is thermally oxidized locally. In this way, the upper surface is formed so as to be flush with the surface of the semiconductor substrate. In this figure, the smaller angle β of the angle formed by the straight line along the side surface of the recessed LOCOS oxide film and the straight line along the surface on the semiconductor substrate is the bird's beak angle of the recessed LOCOS oxide film. Therefore, it is about “55 degrees”.

  Still further, the STI as shown in FIG. 2C is formed as follows, for example. That is, first, an oxide film made of silicon oxide is formed on the upper surface of a semiconductor substrate made of silicon, and silicon nitride having oxidation resistance is formed on the upper surface of the oxide film. Next, the semiconductor substrate is etched using these silicon nitride and silicon oxide as a mask to form a shallow trench. The inner wall of the trench thus formed is oxidized, and an oxide film made of silicon oxide is formed on the inner wall of the trench. Silicon oxide is embedded or deposited in the trench thus formed and on the upper surface of the semiconductor substrate (specifically, silicon nitride) through, for example, CVD. Then, using the silicon nitride as a stopper, the surface of the semiconductor substrate is planarized through, for example, CMP. In this way, the STI is formed so that the upper surface thereof is flush with the surface of the semiconductor substrate, like the recess LOCOS oxide film. In this figure, the smaller angle γ of the angle formed by the straight line along the side surface of the STI and the straight line along the surface on the semiconductor substrate is the bird's beak angle of the STI. Degree ".

  As described above, the bird's beak angle of the element isolation insulating film generally has a relationship of “normal LOCOS oxide film <recess LOCOS oxide film <STI”. Because of this relationship, and as can be seen from the comparison of FIGS. 2A to 2C, the spread in the direction (lateral direction) along the surface of the semiconductor substrate is “STI <recessed LOCOS oxide film”. <Normal LOCOS oxide film> Therefore, in order to achieve high integration of the semiconductor device, it is better to adopt a recess LOCOS oxide film or STI as an element isolation insulating film than a normal LOCOS oxide film.

  However, for example, in the power circuit region including the lateral MOS transistor element, when the recess LOCOS or STI is used as the element isolation insulating film, the bird's beak angle is large, and therefore, FIGS. ), The on-resistance value increases, for example, the current flow path becomes longer or the current flow direction changes abruptly. In other words, the on-resistance value has a relationship of “normal LOCOS oxide film <recess LOCOS oxide film <STI”. Specifically, as shown in FIG. 12, by replacing the normal LOCOS oxide film with the recess LOCOS oxide film, the on-resistance increases by about “10%”, and by replacing the normal LOCOS oxide film with STI, The on-resistance value increases by about “20%”. Such an increase in the on-resistance value has a great influence on the power consumption of the power circuit. Therefore, in order to maintain the on-resistance value as it is or to reduce it, it is necessary to increase the area of the power circuit. As described above, when a normal LOCOS oxide film is simply replaced with the recess LOCOS oxide film or STI in a so-called composite semiconductor device, it is difficult to achieve high integration of the semiconductor device.

  Therefore, in the present embodiment, as described above, the logic circuit 10 employs a recess LOCOS oxide film having a small bird's beak angle as the element isolation insulating film instead of the normal LOCOS oxide film, thereby reducing the p. The channel type MOS transistor element and the n channel type MOS transistor element are insulated and separated, and the semiconductor device is highly integrated. On the other hand, in the power circuit 20, by adopting a normal LOCOS oxide film as the element isolation insulating film, the gate electrode 57 and the drain region 51 of the lateral MOS transistor element are insulated and separated, and the semiconductor device is consumed. Electric power is reduced. Thus, since the element isolation insulating films of both circuits are separately formed, it is possible to suppress an increase in power consumption in the power circuit region while maintaining a high degree of integration in the logic circuit region. .

  Hereinafter, a method for manufacturing the semiconductor device 1 configured as described above will be described with reference to FIGS. 4A to 4E are side cross-sectional views schematically showing a manufacturing process for forming an element isolation insulating film in both the logic circuit region and the power circuit region in the method of manufacturing the semiconductor device 1. FIG. 5A to 5D are side cross-sectional views schematically showing a manufacturing process for forming semiconductor elements in both the logic circuit region and the power circuit region, which is a manufacturing process subsequent to FIG.

  In manufacturing the semiconductor device 1, first, as shown in FIG. 4A, an N-type semiconductor substrate 30 made of silicon is prepared and accommodated in an oxidation furnace. In this oxidation furnace, silicon and oxygen are reacted to grow silicon oxide over the entire surface of the semiconductor substrate 30 to form a silicon oxide film (SiO 2) having a constant thickness. Thereafter, for example, through CVD, silane (SiH 4) gas and ammonia gas (NH 3) are chemically reacted in a gas phase to deposit and form a silicon nitride film (Si 3 N 4) on the entire surface of the silicon oxide film.

  Next, as shown in FIG. 4B, a resist is applied to the entire surface of the upper surface of the silicon nitride film, and this resist is patterned so that only the resist at a predetermined position remains. Then, using the patterned resist as a mask, the portion of the silicon nitride film where the resist is not left is removed by etching. At this time, the silicon oxide film under the silicon nitride film is left without being etched away. Then, after the etching removal of the silicon nitride film is finished, the resist used in this process is removed. Then, as shown in FIG. 4C, a resist is formed only on the surface of the semiconductor substrate 30 (more precisely, a silicon nitride film and a silicon oxide film) in the power circuit region where the power circuit is manufactured.

  Next, as shown in FIG. 4D, the silicon oxide film and a part of the upper surface of the semiconductor substrate 30 are removed by etching using the silicon nitride film in the logic circuit region in which the logic circuit is manufactured as a mask. 30 A shallow groove 45a is formed in a part of the upper surface. Also, the resist left in the power circuit area is removed.

  When such a semiconductor substrate 30 is exposed to an oxidizing atmosphere and brought to a high temperature state, that is, when the semiconductor substrate 30 is thermally oxidized, the upper surface is the upper surface of the semiconductor substrate 30 in the logic circuit region as shown in FIG. A recess LOCOS oxide film 45 is formed that fits in the same plane as (precisely the upper surface of the silicon nitride film). On the other hand, in the power circuit region, a normal LOCOS oxide film 56 whose upper surface reaches above the upper surface of the semiconductor substrate 30 (more precisely, the upper surface of the silicon oxide film) is formed. In this way, insulating films for element isolation are separately formed.

  Thus, when the recess LOCOS oxide film 45 and the normal LOCOS oxide film 56 are formed in the logic circuit region and the power circuit region, respectively, as shown in FIGS. Form.

  First, as shown in FIG. 5A, the recess LOCOS oxide film 45, the normal LOCOS oxide film 56, and the silicon oxide film are left on the surface of the semiconductor substrate 30, and the silicon nitride film is removed. Next, as shown in FIG. 5B, a P-type P well 40 is formed at a predetermined low concentration in the logic circuit region of the semiconductor substrate 30, while in the power circuit region of the semiconductor substrate 30, An N-type N well is formed at a predetermined concentration.

  As shown in FIG. 5C, in the logic circuit region of the semiconductor substrate 30, a plurality of P-type or N-type impurity regions are formed in the surface layer portion of the semiconductor substrate 30 at a predetermined concentration by, for example, ion implantation. Form. Among these, the N-type impurity region functions as the drain region 41 or the source region 42 of the above-described p-channel MOS transistor element. In addition, a polycrystalline silicon film is deposited on a portion of the upper surface of the semiconductor substrate 30 (more precisely, a silicon oxide film) between the drain region 41 and the source region 42 by, for example, CVD. The polycrystalline silicon film thus deposited functions as the gate electrode 43 of the p-channel MOS transistor element.

  On the other hand, as shown in FIG. 5C, in the power circuit region of the semiconductor substrate 30, a P-type or N-type impurity region is formed at a predetermined concentration in the surface layer portion of the semiconductor substrate 30 by, for example, ion implantation. It is formed by dividing into a plurality of times. Among these, the impurity region formed between the normal LOCOS oxide films 56 functions as the drain region 51 of the lateral MOS transistor element. Similarly, an N-type impurity region formed in a position away from the drain region 51 in the surface layer portion of the semiconductor substrate 30 functions as the source region 52 of the lateral MOS transistor element. Further, in the surface layer portion of the semiconductor substrate 30, the P-type low-concentration impurity region and the P-type high-concentration impurity region located between the drain region 51 and the source region 52 are the channel region of the lateral MOS transistor element. Functions as 53 and 54. Further, as shown in FIG. 5C, the silicon oxide film already formed over the channel regions 54 and 53 functions as the gate insulating film 55. Then, a polycrystalline silicon film is deposited on the upper surface of the gate insulating film 55 by, for example, CVD. The polycrystalline silicon film thus deposited functions as the gate electrode 57 of the lateral MOS transistor element.

  Next, as shown in FIG. 5D, a protective film is formed over the entire surface of the semiconductor substrate 30 by, for example, BPSG, a resist is applied to the upper surface of the protective film, and the resist is patterned. To do. Using the patterned resist as a mask, the protective film is removed by etching to form an electrode, whereby the semiconductor device 1 shown in FIG. 1 is manufactured. This protective film functions as the insulating film 44.

  Note that the semiconductor device and the manufacturing method thereof according to the present invention are not limited to the configuration and method illustrated in the first embodiment, and the embodiment is implemented as, for example, the following form as appropriate. You can also.

  In the first embodiment, a recess LOCOS oxide film having a bird's beak angle larger than that of a normal LOCOS oxide film is employed as the element isolation insulating film of the logic circuit 10, and the element isolation insulating film of the power circuit 20 is used as the element isolation insulating film. Although a normal LOCOS oxide film has been employed, the present invention is not limited to this. In addition, for example, an STI having a larger bird's beak angle than the recess LOCOS oxide film is used as the element isolation insulating film of the logic circuit 10, and a normal LOCOS oxide film is used as the element isolation insulating film of the power circuit 20. It is good. As a result, the semiconductor device can be further highly integrated.

  In the first embodiment, when the shallow groove 45a for forming the recess LOCOS oxide film is formed at a predetermined position on the upper surface of the semiconductor substrate 30 (see FIG. 4D), the logic circuit region and the power circuit are formed. Regardless of the region, the thickness of the silicon oxide film on the upper surface of the semiconductor substrate 30 is a constant thickness, but is not limited thereto. The thickness of the silicon oxide film in the logic circuit region of the semiconductor substrate 30 is made thinner than the thickness of the silicon oxide film in the power circuit region of the semiconductor substrate 30, and then a shallow groove for forming the recess LOCOS oxide film is formed. May be. In general, the thinner the silicon oxide film, the smaller the extension of the recess LOCOS oxide film in the direction (lateral direction) along the upper surface of the semiconductor substrate 30, so that the semiconductor device can be further highly integrated. .

(Second Embodiment)
Next, a second embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 6 and 7, the same elements as those shown in FIGS. 1 to 5 are denoted by the same reference numerals, and redundant description of each element is omitted.

  FIG. 6 is a side sectional view of the second embodiment. As shown in FIG. 6, this embodiment also has a structure according to the first embodiment. However, in the semiconductor device 2a of the present embodiment, the CVD insulating film 56a deposited and patterned on the surface of the semiconductor substrate 30 through chemical vapor deposition is employed as the element isolation insulating film of the power circuit 20a. .

  In the power circuit 20a, as shown in FIG. 6, an N-type high-concentration impurity region is formed in the surface layer portion of the semiconductor substrate 30, and this impurity region functions as the drain region 51 of the lateral MOS transistor element. To do. A drain electrode 58 is formed using a metal such as aluminum (Al) so as to be in contact with the upper surface of the drain region 51. Similarly, two N-type impurity regions are formed at positions spaced from the drain region 51 in the surface layer portion of the semiconductor substrate 30, and these impurity regions function as the source region 52 of the lateral MOS transistor element. To do. A source electrode 59 is formed on the upper surface of the source region 52 using a metal such as aluminum (Al). In the surface layer portion of the semiconductor substrate 30, a P-type low-concentration impurity region and a P-type high-concentration impurity region located between the drain region 51 and the source region 52 are formed in the channel of the lateral MOS transistor element. Functions as regions 53 and 54. Further, as shown in FIG. 6, over the channel regions 54 and 53, an insulating material such as silicon oxide (SiO 2) is used to form a gate insulating film 55 and a CVD insulating film 56a as an element isolating insulating film. The gate electrode 57 is formed using a conductive material such as polycrystalline silicon through the gate insulating film 55 and the CVD insulating film 56a.

  The bird's beak angle and on-resistance value of the CVD insulating film 56a will be described with reference to FIGS. 7 (a) and 7 (b).

  As shown in FIG. 7A, the smaller angle δ of the angles formed by the straight line along the side surface of the CVD insulating film 56a and the straight line along the upper surface of the semiconductor substrate 30 is the CVD insulating film 56a. Bird's beak angle. The bird's beak angle of the CVD insulating film 56a is approximately the same as the bird's beak angle of a normal LOCOS oxide film, although it depends on the performance of the patterning equipment.

  Further, the CVD insulating film 56 a is formed by being deposited on the surface of the semiconductor substrate 30. Therefore, as shown in FIG. 7B, due to the formation of the CVD insulating film 56a, the current flow path becomes longer or the current flow direction changes abruptly. There is almost no. Therefore, the current can flow linearly, and the on-resistance value hardly increases.

  As described above, in the present embodiment, in the logic circuit 10, by adopting a recess LOCOS oxide film having a small bird's beak angle instead of a normal LOCOS oxide film as an element isolation insulating film, a p-channel type MOS The transistor element and the n-channel MOS transistor element are insulated and separated, and the semiconductor device is highly integrated. On the other hand, in the power circuit 20a, the gate insulating film 56a and the drain region of the lateral MOS transistor element are adopted by adopting a CVD insulating film 56a deposited and patterned on the surface of the semiconductor substrate 30 through CVD as an element isolation insulating film. 51 is insulated and separated, and the power consumption of the semiconductor device is reduced. Thus, since the element isolation insulating films of both circuits are separately formed, it is possible to suppress an increase in power consumption in the power circuit region while maintaining a high degree of integration in the logic circuit region. .

  Hereinafter, a method of manufacturing the semiconductor device 2a configured as described above will be described with reference to FIGS. 8A to 8E are side cross-sectional views schematically showing a manufacturing process for forming an element isolation insulating film in the logic circuit region in the method for manufacturing the semiconductor device 2a. 9A to 9C are side cross-sectional views schematically showing the manufacturing process for forming the element isolation insulating film in the power circuit region, which is a manufacturing process subsequent to FIG. FIGS. 10A to 10D are side cross-sectional views schematically showing a manufacturing process subsequent to FIG. 9 and forming a semiconductor element in both the logic circuit region and the power circuit region. is there. This manufacturing method is also basically a method according to the method for manufacturing the semiconductor device 1 shown in FIGS.

  In manufacturing the semiconductor device 2a, as shown in FIG. 4A, first, as shown in FIG. 8A, an N-type semiconductor substrate 30 made of silicon is prepared, and this is used in an oxidation furnace. Accommodate. In this oxidation furnace, silicon and oxygen are reacted to grow silicon oxide over the entire surface of the semiconductor substrate 30 to form a silicon oxide film (SiO 2) having a constant thickness. Thereafter, for example, through CVD, silane (SiH 4) gas and ammonia gas (NH 3) are chemically reacted in a gas phase to deposit and form a silicon nitride film (Si 3 N 4) on the entire surface of the silicon oxide film.

  Next, as shown in FIG. 8B, a resist is applied to the entire surface of the upper surface of the silicon nitride film, and this resist is patterned so that only the resist at a predetermined position remains. Then, using the patterned resist as a mask, the portion of the silicon nitride film where the resist is not left is removed by etching. At this time, the silicon oxide film below the silicon nitride film is left without being removed by etching. Then, after the etching removal of the silicon nitride film is finished, the resist used in this process is removed. Then, as shown in FIG. 8C, a resist is formed only on the surface of the semiconductor substrate 30 (more precisely, a silicon nitride film and a silicon oxide film) in the power circuit region where the power circuit is manufactured.

  Next, as shown in FIG. 8D, the silicon oxide film and a part of the upper surface of the semiconductor substrate 30 are removed by etching using the silicon nitride film in the logic circuit region in which the logic circuit is manufactured as a mask. 30 A shallow groove 45b is formed in a part of the upper surface. Also, the resist left in the power circuit area is removed.

  When such a semiconductor substrate 30 is exposed to an oxidizing atmosphere and brought to a high temperature state, that is, when the semiconductor substrate 30 is thermally oxidized, the upper surface is the upper surface of the semiconductor substrate 30 in the logic circuit region as shown in FIG. A recess LOCOS oxide film 45 is formed that fits in the same plane as (precisely the upper surface of the silicon nitride film). On the other hand, in the power circuit region, since the upper surface of the semiconductor substrate 30 is not exposed to the atmosphere, the element isolation insulating film is not formed and is formed through the manufacturing process shown in FIG.

  First, as shown in FIG. 9A, the silicon oxide film and silicon nitride film remaining on the upper surface of the semiconductor substrate 30 in FIG. 8E are removed. A silicon oxide film (CVD film) is deposited and formed with a predetermined thickness on the entire surface of the semiconductor substrate 30 exposed by removing the silicon oxide film and the silicon nitride film, for example, by CVD.

  Next, as shown in FIG. 9B, a resist is applied to the entire surface of the upper surface of the CVD film, and this resist is patterned so that only the resist at a predetermined position remains. Then, using the patterned resist as a mask, a portion of the CVD film where the resist is not left is removed by etching. At this time, the upper surface of the semiconductor substrate 30 is exposed again. As described above, when the CVD film is removed by etching, the CVD insulating film 56a is formed at a predetermined position in the power circuit region as shown in FIG. 9C.

  Thus, when the recess LOCOS oxide film 45 and the CVD insulating film 56a are formed in the logic circuit region and the power circuit region, respectively, semiconductor elements are formed in the respective regions as shown in FIGS. .

  First, as shown in FIG. 10A, a silicon oxide film is formed with a predetermined film thickness on the upper surface of the semiconductor substrate 30 excluding a portion where the CVD insulating film 56a is located. Next, as shown in FIG. 10B, a P-type P well 40 is formed at a predetermined low concentration in the logic circuit region of the semiconductor substrate 30, while in the power circuit region of the semiconductor substrate 30, An N-type N well is formed at a predetermined concentration.

  Then, as shown in FIG. 10C, CMOS transistor elements and lateral MOS transistor elements are formed in the logic circuit area and the power circuit area of the semiconductor substrate 30 as in FIG. 5C.

  Further, as shown in FIG. 10D, a protective film is formed over the entire surface of the semiconductor substrate 30 by, for example, BPSG, a resist is applied to the upper surface of the protective film, and the resist is patterned. . Using this patterned resist as a mask, the protective film is removed by etching to form an electrode, whereby the semiconductor device 2a shown in FIG. 6 is manufactured. This protective film functions as the insulating film 44.

  Note that the semiconductor device and the manufacturing method thereof according to the present invention are not limited to the configuration and method illustrated in the second embodiment, and the embodiment is implemented as, for example, the following form as appropriate. You can also.

  In the second embodiment, a recess LOCOS oxide film having a bird's beak angle larger than that of a normal LOCOS oxide film is employed as the element isolation insulating film of the logic circuit 10, and the element isolation insulating film of the power circuit 20 is used as the element isolation insulating film. Although the CVD insulating film 56a having the same bird's beak angle as that of a normal LOCOS oxide film is employed, the present invention is not limited to this. In addition, for example, STI having a larger bird's beak angle than the recess LOCOS oxide film is employed as the element isolation insulating film of the logic circuit 10, and the CVD insulating film 56 a is employed as the element isolation insulating film of the power circuit 20. Also good. As a result, the on-resistance value of the power circuit portion is further reduced, so that an increase in power consumption in the power circuit region can be further suppressed while maintaining a high degree of integration in the logic circuit region.

  In the second embodiment, when the shallow groove 45b for forming the recess LOCOS oxide film is formed at a predetermined position on the upper surface of the semiconductor substrate 30 (see FIG. 8D), the logic circuit region and the power circuit are formed. Regardless of the region, the thickness of the silicon oxide film on the upper surface of the semiconductor substrate 30 is a constant thickness, but is not limited thereto. The thickness of the silicon oxide film in the logic circuit region of the semiconductor substrate 30 is made thinner than the thickness of the silicon oxide film in the power circuit region of the semiconductor substrate 30, and then a shallow groove for forming the recess LOCOS oxide film is formed. May be. In general, the thinner the silicon oxide film, the smaller the extension of the recess LOCOS oxide film in the direction (lateral direction) along the upper surface of the semiconductor substrate 30, so that the semiconductor device can be further highly integrated. .

  In the second embodiment (including modifications), since the semiconductor substrate 30 is a flat plate, it is between the upper surface of the source region 52 and the upper surface of the drain region 51 of the lateral MOS transistor element constituting the power circuit 20a. Although the structure has no vertical step on the upper surface of the semiconductor substrate 30, the structure is not limited to this. In addition, for example, as shown in FIG. 11 as a diagram corresponding to FIG. 6, between the upper surface of the source region 52 and the upper surface of the drain region 51 of the lateral MOS transistor element constituting the power circuit 20b, The semiconductor device 2a may be formed with a step D in the vertical direction on the upper surface of the semiconductor substrate 30a for reducing the on-resistance value. As a result, the area in which the channel current flowing between these two regions can flow can be increased, so that the on-resistance value can be further reduced and an increase in power consumption in the power circuit region can be further suppressed. become.

  In addition, there are the following elements that can be changed in common with the configurations and methods (including modifications) exemplified in the first and second embodiments.

  In each of the above-described embodiments (including modifications), a recess LOCOS oxide film or STI is adopted as the element isolation insulating film of the logic circuit 10, and a normal LOCOS is used as the element isolation insulating film of the power circuits 20 to 20b. Although an oxide film or a CVD insulating film has been employed, the present invention is not limited to this. In short, if the insulating films for element isolation of these circuits are made so that the bird's beak angle of the insulating film for element isolation of the power circuit is smaller than the bird's beak angle of the insulating film for element isolation of the logic circuit Can achieve the intended purpose.

Sectional drawing which shows the side structure about 1st Embodiment of the semiconductor device which concerns on this invention. (A) is side surface sectional drawing which shows the bird's beak angle of a normal LOCOS oxide film. (B) is side surface sectional drawing which shows the bird's beak angle of a recess LOCOS oxide film. (C) is side surface sectional drawing which shows the bird's beak angle of STI. (A) is side surface sectional drawing which shows the current pathway of the electric current which flows around a normal LOCOS oxide film. (B) is a side sectional view showing a current path of a current flowing around the recess LOCOS oxide film. (C) is a side sectional view showing a current path of a current flowing around the STI. (A)-(e) is side surface sectional drawing which shows typically the manufacturing process about the method of manufacturing the semiconductor device of 1st Embodiment. FIGS. 5A to 5D are side cross-sectional views schematically showing a manufacturing process following FIG. 4 for the method for manufacturing the semiconductor device of the first embodiment. Sectional drawing which shows the side structure about 2nd Embodiment of the semiconductor device which concerns on this invention. (A) is side surface sectional drawing which shows the bird's beak angle of a CVD insulating film. (B) is a side cross-sectional view showing a current path of a current flowing directly under a CVD insulating film. (A)-(e) is side surface sectional drawing which shows typically the manufacturing process about the method of manufacturing the semiconductor device of 2nd Embodiment. FIGS. 8A to 8C are side cross-sectional views schematically showing a manufacturing process following FIG. 7 for the method for manufacturing the semiconductor device of the second embodiment. FIGS. 9A to 9D are side cross-sectional views schematically showing a manufacturing process following FIG. 8 for the method for manufacturing the semiconductor device of the second embodiment. Sectional drawing which shows the side structure about the modification of the semiconductor device of 2nd Embodiment. The figure which shows the relationship between a bird's beak angle and on-resistance value.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2a, 2b ... Semiconductor device, 10 ... Logic circuit, 20, 20a, 20b ... Power circuit, 30, 30a ... Semiconductor substrate, 40 ... P well, 41, 42 ... Impurity region, 43 ... Gate electrode, 44 ... Insulation 45, Recessed LOCOS oxide film (element isolation insulating film), 45a, 45b ... Shallow groove, 46 ... Drain electrode, 47 ... Source electrode, 51 ... Drain region, 52 ... Source region, 53, 54 ... Channel region, 55... Gate insulating film, 56... LOCOS oxide film (element isolation insulating film), 56 a .. CVD insulating film (element isolation insulating film), 57... Gate electrode, 58.

Claims (12)

A semiconductor device in which a logic circuit area in which a logic circuit including a CMOS transistor element is formed and a power circuit area in which a power circuit including a lateral MOS transistor element is formed are formed in a surface layer portion of the same semiconductor substrate Because
The bird's beak of the element isolation insulating film of the power circuit, which is the smaller of the angles formed by the direction along the side surface of the element isolation insulating film of the power circuit and the direction along the surface of the semiconductor substrate Insulation for element isolation of the logic circuit, wherein the angle is a smaller one of angles formed by the direction along the side surface of the element isolation insulating film of the logic circuit and the direction along the surface of the semiconductor substrate. A semiconductor device characterized in that the insulating films for element isolation of these two circuits are separately formed so as to be smaller than the bird's beak angle of the film. The element isolation insulating film of the power circuit is a LOCOS oxide film that is formed by selectively oxidizing the surface of the semiconductor substrate and insulates a gate electrode and a drain region constituting the lateral MOS transistor element,
The element isolation insulating film of the logic circuit comprises a p-type MOS transistor element and an n-type MOS transistor element constituting the CMOS transistor element, the upper surface of which is formed to be flush with the surface of the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the semiconductor device is a recess LOCOS oxide film to be insulated. The element isolation insulating film of the power circuit is a LOCOS oxide film that is formed by selectively oxidizing the surface of the semiconductor substrate and insulates a gate electrode and a drain region constituting the lateral MOS transistor element,
The element isolation insulating film of the logic circuit includes a p-type MOS transistor element and an n-type MOS transistor element constituting the CMOS transistor element, wherein an oxide film is buried in a groove formed on the surface of the semiconductor substrate. The semiconductor device according to claim 1, wherein the semiconductor device is an STI that insulates. The element isolation insulating film of the power circuit is an insulating film that is deposited on the surface of the semiconductor substrate through chemical vapor deposition and patterned, and insulates the gate electrode and the drain region constituting the lateral MOS transistor element,
The element isolation insulating film of the logic circuit is formed so that an upper surface thereof is flush with the surface of the semiconductor substrate, and insulates the p-type MOS transistor element and the n-type MOS transistor element constituting the CMOS transistor element. The semiconductor device according to claim 1, wherein the semiconductor device is a recess LOCOS oxide film. The element isolation insulating film of the power circuit is an insulating film that is deposited on the surface of the semiconductor substrate through chemical vapor deposition and patterned, and insulates the gate electrode and the drain region constituting the lateral MOS transistor element,
The element isolation insulating film of the logic circuit includes a p-type MOS transistor element and an n-type MOS transistor element forming the CMOS transistor element, wherein an oxide film is buried in a groove formed on the surface of the semiconductor substrate. The semiconductor device according to claim 1, wherein the semiconductor device is an STI that insulates.   2. A step is formed between an upper surface of a source region and an upper surface of a drain region constituting the lateral MOS transistor element for reducing an on-resistance value between the two regions. 4. The semiconductor device according to 4 or 5. A semiconductor device in which a logic circuit area in which a logic circuit including a CMOS transistor element is formed and a power circuit area in which a power circuit including a lateral MOS transistor element is formed are formed in a surface layer portion of the same semiconductor substrate A method of manufacturing
The bird's beak of the element isolation insulating film of the power circuit, which is the smaller of the angles formed by the direction along the side surface of the element isolation insulating film of the power circuit and the direction along the surface of the semiconductor substrate Insulation for element isolation of the logic circuit, wherein the angle is a smaller one of angles formed by the direction along the side surface of the element isolation insulating film of the logic circuit and the direction along the surface of the semiconductor substrate. A method of manufacturing a semiconductor device, comprising separately forming an insulating film for element isolation of both circuits so as to be smaller than a bird's beak angle of the film. As the element isolation insulating film of the power circuit, a LOCOS oxide film that insulates the gate electrode and the drain region constituting the lateral MOS transistor element through selective oxidation of the surface of the semiconductor substrate is formed.
A recess that insulates the p-type MOS transistor element and the n-type MOS transistor element constituting the CMOS transistor element so that the upper surface of the logic circuit element isolation insulating film is flush with the surface of the semiconductor substrate. 8. The method of manufacturing a semiconductor device according to claim 7, wherein a LOCOS oxide film is formed. As the element isolation insulating film of the power circuit, a LOCOS oxide film that insulates the gate electrode and the drain region constituting the lateral MOS transistor element through selective oxidation of the surface of the semiconductor substrate is formed.
As an insulating film for element isolation of the logic circuit, an oxide film is buried in a groove formed on the surface of the semiconductor substrate, thereby insulating the p-type MOS transistor element and the n-type MOS transistor element constituting the CMOS transistor element. The method of manufacturing a semiconductor device according to claim 7, wherein the STI is formed. As the element isolation insulating film of the power circuit, an insulating film that insulates the gate electrode and the drain region constituting the lateral MOS transistor element through chemical vapor deposition is deposited on the surface of the semiconductor substrate,
A recess that insulates the p-type MOS transistor element and the n-type MOS transistor element constituting the CMOS transistor element so that the upper surface of the logic circuit element isolation insulating film is flush with the surface of the semiconductor substrate. 8. The method of manufacturing a semiconductor device according to claim 7, wherein a LOCOS oxide film is formed. As the element isolation insulating film of the power circuit, an insulating film that insulates the gate electrode and the drain region constituting the lateral MOS transistor element through chemical vapor deposition is deposited on the surface of the semiconductor substrate,
As an insulating film for element isolation of the logic circuit, an oxide film is buried in a groove formed on the surface of the semiconductor substrate, thereby insulating the p-type MOS transistor element and the n-type MOS transistor element constituting the CMOS transistor element. The method of manufacturing a semiconductor device according to claim 7, wherein the STI is formed.   11. A step is formed between an upper surface of a source region and an upper surface of a drain region constituting the lateral MOS transistor element to reduce an on-resistance value between these two regions. Or a method of manufacturing a semiconductor device according to 11;

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