JP2013105761A - Manufacturing method of power semiconductor device - Google Patents

Manufacturing method of power semiconductor device Download PDF

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JP2013105761A
JP2013105761A JP2011246265A JP2011246265A JP2013105761A JP 2013105761 A JP2013105761 A JP 2013105761A JP 2011246265 A JP2011246265 A JP 2011246265A JP 2011246265 A JP2011246265 A JP 2011246265A JP 2013105761 A JP2013105761 A JP 2013105761A
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power semiconductor
insulating substrate
semiconductor device
conductive pattern
manufacturing
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JP5987297B2 (en
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Fumihiko Momose
文彦 百瀬
Yoshitaka Nishimura
芳孝 西村
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a power semiconductor device capable of improving an isolation voltage and reliability under a high-temperature environment.SOLUTION: By combining an oxygen plasma surface treatment step (step 5) and a preliminary heating process (step 6) before silicone gel injection, adhesiveness between a silicone gel 9 (a protective material), and an insulating substrate 1 having a conductive pattern and a semiconductor chip 2 is improved, thus an isolation voltage and reliability of a power semiconductor device under a high-temperature environment can be improved.

Description

この発明は、パワー半導体装置の製造方法に係り、特に、シリコーンゲルなどが封入されたパワー半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a power semiconductor device, and more particularly to a method for manufacturing a power semiconductor device in which silicone gel or the like is enclosed.

パワー半導体モジュールなどのパワー半導体装置では、樹脂ケース内に配置される導電パターン付絶縁基板の導電パターンやこの導電パターン上に半田などで接合されるパワー半導体チップを保護するために樹脂ケース内にシリコーンゲルを充填し封止する。このシリコーンゲルによって樹脂ケース内での絶縁性能(絶縁耐圧)が確保されている。   In a power semiconductor device such as a power semiconductor module, silicone is contained in the resin case to protect the conductive pattern of the insulating substrate with the conductive pattern disposed in the resin case and the power semiconductor chip bonded to the conductive pattern with solder or the like. Fill with gel and seal. The silicone gel ensures the insulation performance (insulation breakdown voltage) in the resin case.

図11は、従来のパワー半導体装置の概略の製造工程図である。この工程図はシリコーンゲルが注入されるまでの概略の工程を示している。この各工程の詳細説明を以下の図12〜図16で示す。   FIG. 11 is a schematic manufacturing process diagram of a conventional power semiconductor device. This process diagram shows a schematic process until the silicone gel is injected. Detailed description of each step is shown in FIGS.

図12〜図16は、従来のパワー半導体装置の製造方法を工程順に示した要部製造工程断面図である。パワー半導体装置とは、ここではIGBTやパワーMOSFETなどのパワー半導体チップを収納したパワー半導体モジュールなどである。   12 to 16 are cross-sectional views of the main part manufacturing process showing the manufacturing method of the conventional power semiconductor device in the order of processes. Here, the power semiconductor device is a power semiconductor module that houses a power semiconductor chip such as an IGBT or a power MOSFET.

まず、図12(工程1)において、導電パターン付絶縁基板1上にパワー半導体チップ2を接合し、パワー半導体チップ2と導電パターン付絶縁基板1の図示しない導電パターンをボンディングワイヤ3で接続する。導電パターン付絶縁基板1とは、図示しないセラミックなどの絶縁基板上に回路配線パターンとなる導電パターンを接合し、裏面には裏面導電層を接合したものである。この導電パターンは通常は銅箔などで形成される。   First, in FIG. 12 (process 1), the power semiconductor chip 2 is joined on the insulating substrate 1 with the conductive pattern, and the power semiconductor chip 2 and the conductive pattern (not shown) of the insulating substrate 1 with the conductive pattern are connected by the bonding wire 3. The insulating substrate with conductive pattern 1 is obtained by bonding a conductive pattern to be a circuit wiring pattern on an insulating substrate such as ceramic (not shown) and bonding a back surface conductive layer on the back surface. This conductive pattern is usually formed of copper foil or the like.

つぎに、図13(工程2)において、導電パターン付絶縁基板1の図示しない裏面導電層を放熱ベース4に半田などで接合する。
つぎに、図14(工程3)において、樹脂ケース5の底部を放熱ベース4の側面に接着剤で固定する。接着剤はエポキシ樹脂系の接着剤であり、接着条件としては温度が150℃程度で処理時間が3分程度である。
Next, in FIG. 13 (process 2), the back surface conductive layer (not shown) of the insulating substrate 1 with the conductive pattern is joined to the heat dissipation base 4 with solder or the like.
Next, in FIG. 14 (step 3), the bottom of the resin case 5 is fixed to the side surface of the heat dissipation base 4 with an adhesive. The adhesive is an epoxy resin adhesive, and the bonding conditions are a temperature of about 150 ° C. and a processing time of about 3 minutes.

つぎに、図15(工程4)において、パワー半導体チップ2および導電パターンと樹脂ケース5に固定されている外部導出端子6をボンディングワイヤ3などで接続する。
つぎに、図16(工程5)において、シリコーンゲル9を樹脂ケース5内に注入する。
Next, in FIG. 15 (step 4), the power semiconductor chip 2 and the conductive pattern are connected to the external lead-out terminal 6 fixed to the resin case 5 by the bonding wire 3 or the like.
Next, in FIG. 16 (step 5), the silicone gel 9 is injected into the resin case 5.

また、特許文献1では、半導体素子とリードを、この半導体素子およびリードの外表面の少なくとも一部がポリイミドに被覆された状態で電気接続を行い、ついで上記リード付半導体素子を封止樹脂によって封止する半導体装置に製法であって、上記リード付半導体素子の樹脂封止に先立って、少なくともポリイミド部分をプラズマ処理するようにした。   Further, in Patent Document 1, electrical connection is made between a semiconductor element and a lead in a state where at least a part of the outer surface of the semiconductor element and the lead is covered with polyimide, and then the leaded semiconductor element is sealed with a sealing resin. A semiconductor device to be stopped is a manufacturing method, and at least a polyimide portion is subjected to plasma treatment prior to resin sealing of the leaded semiconductor element.

このプラズマ処理によって、封止樹脂に接するポリイミド表面が改質されて樹脂とのなじみ性が向上する。したがって、この方法によれば、ポリイミドと封止樹脂の境界面における両者の耐湿密着性に優れ、半田リフロー工程においてパッケージクラックを発生しにくい半導体装置を得ることができることが記載されている。   By this plasma treatment, the polyimide surface in contact with the sealing resin is modified and the compatibility with the resin is improved. Therefore, it is described that according to this method, it is possible to obtain a semiconductor device which is excellent in moisture resistance adhesion between the polyimide and the sealing resin at the interface and hardly causes package cracks in the solder reflow process.

また、特許文献2では、基板31上に半導体素子を搭載し、この半導体素子と基板の電極をワイヤボンディングにより接続してなる電子部品の製造方法において、銅電極上のニッケル膜上に形成された金膜の表面に、半導体素子接着時の熱処理によって生成する接合阻害物を、アルゴンガスによる第1のプラズマ処理により除去してワイヤボンディング性を向上させる。その後、第1のプラズマ処理によって樹脂モールドとの密着性が低下したレジストの表面を、酸素ガスプラズマを用いる第2のプラズマ処理によって改質し、封止樹脂の樹脂モールドとの密着性を向上させることが記載されている。   In Patent Document 2, a semiconductor element is mounted on a substrate 31 and formed on a nickel film on a copper electrode in a method of manufacturing an electronic component in which the semiconductor element and an electrode of the substrate are connected by wire bonding. On the surface of the gold film, bonding obstructions generated by the heat treatment at the time of bonding the semiconductor element are removed by the first plasma treatment with argon gas to improve the wire bonding property. Thereafter, the surface of the resist whose adhesion to the resin mold is reduced by the first plasma treatment is modified by the second plasma treatment using oxygen gas plasma to improve the adhesion of the sealing resin to the resin mold. It is described.

特開平5−152362号公報JP-A-5-152362 特開平11−145120号公報JP-A-11-145120

前記の図11の従来の工程および図12〜図16の従来の製造方法では、
(1)パワー半導体装置の耐絶縁特性として、常温環境と比較して高温環境下(例えば150℃雰囲気)においては、図17に示すように、絶縁破壊電圧(絶縁耐圧)が低下する。
(2)通常、パワー半導体装置はパワー半導体チップ2の発熱により、高温状態で使用されるため、高温下での絶縁耐圧の低下は信頼性の低下を招く。
In the conventional process of FIG. 11 and the conventional manufacturing method of FIGS.
(1) As the insulation resistance characteristics of the power semiconductor device, the dielectric breakdown voltage (insulation breakdown voltage) decreases in a high temperature environment (for example, 150 ° C. atmosphere) as compared with a normal temperature environment as shown in FIG.
(2) Normally, since the power semiconductor device is used in a high temperature state due to the heat generated by the power semiconductor chip 2, a decrease in the withstand voltage at a high temperature causes a decrease in reliability.

これらは、導電パターン付絶縁基板1およびパワー半導体チップ2とシリコーンゲル9との密着性が低下したために起こる現象である。
これを防ぐために、前記の特許文献1,2のようなOプラズマによる表面処理を施す方法がある。
These are phenomena that occur because the adhesion between the insulating substrate with a conductive pattern 1 and the power semiconductor chip 2 and the silicone gel 9 is lowered.
In order to prevent this, there is a method of performing surface treatment with O 2 plasma as described in Patent Documents 1 and 2 above.

しかし、特許文献1,2に示されているプラズマ表面処理では、高温環境下で用いられるパワー半導体モジュールなどのパワー半導体装置に対しては不十分であり、絶縁破壊電圧の低下と絶縁耐量の低下による信頼性の低下が懸念される。   However, the plasma surface treatments disclosed in Patent Documents 1 and 2 are insufficient for power semiconductor devices such as power semiconductor modules used in a high temperature environment, resulting in a decrease in dielectric breakdown voltage and a decrease in dielectric strength. There is a concern about the decline in reliability.

図17は、従来のIGBTモジュール温度と絶縁破壊耐圧の関係を示す図である。
常温での絶縁破壊電圧が7.0kV〜8.0kVである場合、150℃の高温になると5.0kV〜6.0kVに低下する。
FIG. 17 is a diagram showing the relationship between the conventional IGBT module temperature and the breakdown voltage.
When the dielectric breakdown voltage at normal temperature is 7.0 kV to 8.0 kV, the voltage drops to 5.0 kV to 6.0 kV at a high temperature of 150 ° C.

また、前記の特許文献1,2では、ICが対象の半導体装置であり、印加される電圧も数十V程度で低い。それに対して、パワー半導体装置では、数1000Vと高く、ICよりも絶縁破壊を起こし易い。   In Patent Documents 1 and 2, the IC is a target semiconductor device, and the applied voltage is as low as several tens of volts. On the other hand, a power semiconductor device is as high as several thousand volts, and is more likely to cause dielectric breakdown than an IC.

また、前記の特許文献1,2では、プラズマ表面処理を施す対象がエポキシ樹脂であり、シリコーンゲルを対象とした記述はされていない。また、プラズマ表面処理した後、保護材で表面を被覆する前に予備加熱することについては記載されていない。   Moreover, in the said patent documents 1, 2, the object which plasma-treats is an epoxy resin, and the description which made the silicone gel object is not made. Further, there is no description about preheating after the plasma surface treatment and before covering the surface with a protective material.

パワー半導体装置において、特に大きい樹脂ケース5が使用される場合には、シリコーンゲルの代わりにエポキシ樹脂を用いると、エポキシ樹脂は柔軟性が乏しく熱応力が大きいので樹脂ケースや導電パターン付絶縁基板にクラックが入ったり割れたりするため使用することが出来ない。   In a power semiconductor device, when an especially large resin case 5 is used, if an epoxy resin is used instead of a silicone gel, the epoxy resin has poor flexibility and a large thermal stress, so that the resin case or the insulating substrate with a conductive pattern is used. It cannot be used because it cracks or breaks.

また、前記の特許文献2では、基板のレジストと樹脂モールドとの密着性の向上については記載されているが、導電パターン付絶縁基板(セラミック基板と回路配線パターン)とシリコーンゲルとの密着性については記載されていない。   Moreover, in the said patent document 2, although the improvement of the adhesiveness of the resist of a board | substrate and resin mold is described, about the adhesiveness of an insulating substrate with a conductive pattern (ceramic board | substrate and circuit wiring pattern) and a silicone gel. Is not listed.

また、前記の特許文献では、外力によるダメージや異物の侵入を防止するために密着性の向上を図るということについては記載されているが、本発明のように半導体装置の絶縁耐圧が向上するということについては記載されていない。   In addition, although the above-mentioned patent document describes that the adhesion is improved in order to prevent damage due to external force and intrusion of foreign matter, the dielectric breakdown voltage of the semiconductor device is improved as in the present invention. There is no mention of that.

この発明の目的は、前記の課題を解決して、高温環境下での絶縁耐圧と信頼性の向上を図ることができるパワー半導体装置の製造方法を提供することにある。   An object of the present invention is to provide a method of manufacturing a power semiconductor device that can solve the above-described problems and improve the dielectric strength and reliability in a high temperature environment.

前記の目的を達成するために、特許請求の範囲の請求項1に記載の発明によれば、放熱ベース上に接合された導電パターン付絶縁基板と、該導電パターン付絶縁基板上に接合した半導体チップと、前記導電パターン付絶縁基板および前記半導体チップを収納し前記放熱ベースに接着された樹脂ケースと、該樹脂ケース内に充填された保護材とを備えるパワー半導体装置の製造方法において、導電パターン付絶縁基板上に半導体チップを接合する工程と、放熱ベースに前記導電パターン付絶縁基板を接合する工程と、前記放熱ベースに樹脂ケースを接着する工程と、前記放熱パターン付絶縁基板の表面および前記半導体チップの表面に酸素プラズマ表面処理を施す工程と、前記放熱パターン付絶縁基板および前記半導体チップを高温加熱し、湿気を除去する工程と、樹脂ケース内に保護材を充填する工程と、を含むことを特徴とする製造方法とする。   In order to achieve the above object, according to the first aspect of the present invention, an insulating substrate with a conductive pattern bonded on a heat dissipation base and a semiconductor bonded on the insulating substrate with a conductive pattern are provided. In a method for manufacturing a power semiconductor device, comprising: a chip; a resin case that houses the insulating substrate with the conductive pattern and the semiconductor chip; and is bonded to the heat dissipation base; and a protective material filled in the resin case. A step of bonding a semiconductor chip on the insulating substrate, a step of bonding the insulating substrate with the conductive pattern to the heat radiating base, a step of bonding a resin case to the heat radiating base, a surface of the insulating substrate with the heat radiating pattern, and the Performing oxygen plasma surface treatment on the surface of the semiconductor chip, heating the insulating substrate with a heat radiation pattern and the semiconductor chip at a high temperature, Removing the, the manufacturing method characterized by comprising the step of filling the protective material in the resin case, the.

また、特許請求の範囲の請求項2記載の発明によれば、請求項1に記載の発明において、前記酸素プラズマ表面処理条件において、プラズマのパワーが200W〜600Wであり、プラズマ処理時間が30秒〜700秒であり、酸素(O)の流量が30ml/分〜100ml/分であるとよい。 According to the invention described in claim 2, the plasma power is 200W to 600W and the plasma processing time is 30 seconds in the oxygen plasma surface treatment condition. It is preferable that the flow rate of oxygen (O 2 ) is 30 ml / min to 100 ml / min.

また、特許請求の範囲の請求項3に記載の発明によれば、請求項1に記載の発明において、前記の高温加熱の条件は、温度は100℃以上で200℃以下、加熱時間は30分以上で2時間以下であるとよい。   Further, according to the invention described in claim 3 of the claims, in the invention described in claim 1, the conditions for the high temperature heating are as follows: the temperature is 100 ° C. or more and 200 ° C. or less, and the heating time is 30 minutes. It is good that it is 2 hours or less.

また、特許請求の範囲の請求項4記載の発明によれば、請求項1に記載の発明において、前記保護材がシリコーンゲルもしくはエポキシ樹脂であるとよい。
また、特許請求の範囲の請求項5に記載の発明によれば、請求項1に記載の発明において、前記導電パターン付絶縁基板を構成する絶縁基板の材質が、Al、SiもしくはAlNであり、導電パターンの材質が銅であるとよい。
According to the invention described in claim 4 of the claims, in the invention described in claim 1, the protective material may be a silicone gel or an epoxy resin.
According to the invention described in claim 5, the material of the insulating substrate constituting the insulating substrate with conductive pattern in the invention described in claim 1 is Al 2 O 3 , Si 3 N. 4 or AlN, and the material of the conductive pattern is preferably copper.

なお、本願発明における酸素プラズマ表面処理とは、酸素等の酸化性ガスを用いて発生させたプラズマ中のイオンまたは活性種により、処理対象の表面をクリーニングもしくは親水化処理することをいう。   The oxygen plasma surface treatment in the present invention refers to cleaning or hydrophilizing the surface to be treated with ions or active species in plasma generated using an oxidizing gas such as oxygen.

この発明では、酸素プラズマ表面処理工程と、シリコーンゲル注入前の予備加熱工程を組み合わせることで、シリコーンゲル(保護材)と導電パターン付絶縁基板および半導体チップとの密着性を向上させ、高温環境下でのパワー半導体装置の絶縁耐圧と信頼性の向上を図ることができる。   In this invention, by combining the oxygen plasma surface treatment step and the preheating step before the silicone gel injection, the adhesion between the silicone gel (protective material), the insulating substrate with the conductive pattern, and the semiconductor chip is improved, under a high temperature environment. Thus, it is possible to improve the withstand voltage and reliability of the power semiconductor device.

この発明の第1実施例のパワー半導体装置の製造工程図である。It is a manufacturing process figure of the power semiconductor device of 1st Example of this invention. この発明の第1実施例のパワー半導体装置の要部製造工程断面図である。It is principal part manufacturing process sectional drawing of the power semiconductor device of 1st Example of this invention. 図2に続く、この発明の第1実施例のパワー半導体装置の要部製造工程断面図である。FIG. 3 is a cross-sectional view showing the main part manufacturing process of the power semiconductor device according to the first embodiment of the invention, following FIG. 2; 図3に続く、この発明の第1実施例のパワー半導体装置の要部製造工程断面図である。FIG. 4 is a cross-sectional view showing the main part manufacturing process of the power semiconductor device according to the first embodiment of the invention, following FIG. 3; 図4に続く、この発明の第1実施例のパワー半導体装置の要部製造工程断面図である。FIG. 5 is a cross-sectional view of the essential part manufacturing process of the power semiconductor device according to the first embodiment of the invention, following FIG. 4. 図5に続く、この発明の第1実施例のパワー半導体装置の要部製造工程断面図である。FIG. 6 is a cross-sectional view of the essential part manufacturing process of the power semiconductor device according to the first embodiment of the invention, following FIG. 5. 図6に続く、この発明の第1実施例のパワー半導体装置の要部製造工程断面図である。FIG. 7 is a cross-sectional view of the essential part manufacturing process of the power semiconductor device according to the first embodiment of the invention, following FIG. 6; 図7に続く、この発明の第1実施例のパワー半導体装置の要部製造工程断面図である。FIG. 8 is a cross-sectional view of the main part manufacturing process of the power semiconductor device according to the first embodiment of the invention, following FIG. 7. 酸素プラズマ処理条件と絶縁耐圧の関係を示す図である。It is a figure which shows the relationship between oxygen plasma processing conditions and withstand voltage. 本発明の製造方法を適用したときのIGBTモジュール温度と絶縁破壊耐圧の関係を示す図である。It is a figure which shows the relationship between IGBT module temperature and a dielectric breakdown voltage when the manufacturing method of this invention is applied. 従来のパワー半導体装置の概略の製造工程図である。It is a schematic manufacturing-process figure of the conventional power semiconductor device. 従来のパワー半導体装置の要部製造工程断面図である。It is principal part manufacturing process sectional drawing of the conventional power semiconductor device. 図12に続く、従来のパワー半導体装置の要部製造工程断面図である。FIG. 13 is a main-portion manufacturing process cross-sectional view of the conventional power semiconductor device, following FIG. 12; 図13に続く、従来のパワー半導体装置の要部製造工程断面図である。FIG. 14 is a main-portion manufacturing process cross-sectional view of the conventional power semiconductor device, following FIG. 13; 図14に続く、従来のパワー半導体装置の要部製造工程断面図である。FIG. 15 is a main-portion manufacturing process cross-sectional view of the conventional power semiconductor device, following FIG. 14; 図15に続く、従来のパワー半導体装置の要部製造工程断面図である。FIG. 16 is a main-portion manufacturing process cross-sectional view of the conventional power semiconductor device, following FIG. 15; 従来のIGBTモジュール温度と絶縁破壊耐圧の関係を示す図である。It is a figure which shows the relationship between the conventional IGBT module temperature and a dielectric breakdown voltage. 酸素プラズマ表面処理条件の好適範囲を示す図である。It is a figure which shows the suitable range of oxygen plasma surface treatment conditions.

実施の形態を以下の実施例で説明する。従来と同一部位には同一符号を付した。
<実施例1>
図1は、この発明の第1実施例のパワー半導体装置の製造工程図である。この工程図はシリコーンゲルが注入されるまでを示している。この各工程の詳細説明を以下の図2〜図8で示す。
Embodiments will be described in the following examples. The same reference numerals are assigned to the same parts as in the prior art.
<Example 1>
FIG. 1 is a manufacturing process diagram of a power semiconductor device according to a first embodiment of the present invention. This process diagram shows the process until the silicone gel is injected. Detailed description of each step is shown in FIGS.

図2〜図8は、この発明の第1実施例のパワー半導体装置の製造方法を工程順に示した要部製造工程断面図である。また、パワー半導体装置とは、ここではIGBTやパワーMOSFETなどのパワー半導体チップを収納したパワー半導体モジュールなどである。   2 to 8 are cross-sectional views of the main part manufacturing process showing the method of manufacturing the power semiconductor device according to the first embodiment of the present invention in the order of processes. Here, the power semiconductor device is a power semiconductor module that houses a power semiconductor chip such as an IGBT or a power MOSFET.

まず、図2(工程1)において、導電パターン付絶縁基板1上にパワー半導体チップ2を接合し、パワー半導体チップ2と導電パターン付絶縁基板1の図示しない導電パターンをボンディングワイヤ3などの接続導体で接続する。導電パターン付絶縁基板1とは、図示しないが、セラミックなどの絶縁基板上に回路配線パターンとなる導電パターンが接合し、裏面には裏面導電層が接合したものである。この導電パターンは通常、銅箔などで形成される。   First, in FIG. 2 (process 1), the power semiconductor chip 2 is joined on the insulating substrate 1 with the conductive pattern, and the conductive pattern (not shown) of the power semiconductor chip 2 and the insulating substrate 1 with the conductive pattern is connected to the connecting conductor such as the bonding wire 3. Connect with. Although not shown, the insulating substrate with a conductive pattern 1 is formed by bonding a conductive pattern serving as a circuit wiring pattern on an insulating substrate such as ceramic and bonding a back conductive layer on the back surface. This conductive pattern is usually formed of copper foil or the like.

つぎに、図3(工程2)において、導電パターン付絶縁基板1の図示しない裏面導電層を放熱ベース4に図示しない半田などで接合する。
つぎに、図4(工程3)において、樹脂ケース5の底部を放熱ベース4の側面に接着剤で固定する。接着剤はエポキシ樹脂系の接着剤であり、接着条件としては処理温度が150℃程度で処理時間が3分程度である。
Next, in FIG. 3 (process 2), the back surface conductive layer (not shown) of the insulating substrate 1 with the conductive pattern is joined to the heat radiating base 4 with solder (not shown).
Next, in FIG. 4 (step 3), the bottom of the resin case 5 is fixed to the side surface of the heat dissipation base 4 with an adhesive. The adhesive is an epoxy resin adhesive, and the bonding conditions are a processing temperature of about 150 ° C. and a processing time of about 3 minutes.

つぎに、図5(工程4)において、パワー半導体チップ2および導電パターンと樹脂ケース5に固定されている外部導出端子6をボンディングワイヤ3などの接続導体で接続する。   Next, in FIG. 5 (step 4), the power semiconductor chip 2 and the conductive pattern are connected to the external lead-out terminal 6 fixed to the resin case 5 with a connection conductor such as the bonding wire 3.

つぎに、図6(工程5)において、プラズマ処理装置50内で、導電パターン付絶縁基板1の表面およびパワー半導体チップ2の表面に酸素プラズマ表面処理を行う。前記したように導電パターン付絶縁基板1の導電パターンは銅箔であり、絶縁基板の材質は、Al,Si,AlNなどのセラミックである。 Next, in FIG. 6 (step 5), oxygen plasma surface treatment is performed on the surface of the insulating substrate with conductive pattern 1 and the surface of the power semiconductor chip 2 in the plasma processing apparatus 50. As described above, the conductive pattern of the insulating substrate with a conductive pattern 1 is a copper foil, and the material of the insulating substrate is ceramic such as Al 2 O 3 , Si 3 N 4 , AlN.

つぎに、図7(工程6)において、シリコーンゲル9を注入する前に、予備加熱を行なうこの予備加熱の条件は、加熱温度が150℃程度、加熱時間は1時間程度である。この予備加熱は恒温槽8や熱板を用いて行なう。   Next, in FIG. 7 (step 6), the preheating conditions for preheating before injecting the silicone gel 9 are as follows. The heating temperature is about 150 ° C. and the heating time is about 1 hour. This preheating is performed using a thermostat 8 or a hot plate.

つぎに、図8(工程7)において、シリコーンゲル9を樹脂ケース5内に注入する。
前記の図6(工程5)において、プラズマ処理装置50内に設けられた、酸素プラズマを発生させる平行平板型の電極7の大きさは、例えばL(縦)×W(横)=約250mm×150mm程度である。電極間距離Dは、例えば50mm〜100mm程度である。プラズマ発生の発振周波数fは13.56MHzである。また、プラズマ処理装置内に導入される酸素(O)10の流量Qは50ml/分程度が好適である。この流量Qは30ml以上で100ml以下がよい。流量Qが100ml超ではプラズマ酸化膜の膜質が変質して絶縁耐圧の低下を招く。一方、30ml未満ではプラズマ酸化膜が薄すぎて、密着性が低下し絶縁耐圧の低下を招く。プラズマ処理に用いる酸化性ガスとしては、酸素のほか、亜酸化窒素(NO)等を用いてもよい。
Next, in FIG. 8 (step 7), the silicone gel 9 is injected into the resin case 5.
In FIG. 6 (step 5), the size of the parallel plate electrode 7 for generating oxygen plasma provided in the plasma processing apparatus 50 is, for example, L (vertical) × W (horizontal) = about 250 mm × It is about 150 mm. The interelectrode distance D is, for example, about 50 mm to 100 mm. The oscillation frequency f of plasma generation is 13.56 MHz. The flow rate Q of oxygen (O 2 ) 10 introduced into the plasma processing apparatus is preferably about 50 ml / min. The flow rate Q is preferably 30 ml or more and 100 ml or less. If the flow rate Q exceeds 100 ml, the film quality of the plasma oxide film is changed and the dielectric strength is reduced. On the other hand, if it is less than 30 ml, the plasma oxide film is too thin, the adhesion is lowered, and the withstand voltage is lowered. As the oxidizing gas used for the plasma treatment, nitrous oxide (N 2 O) or the like may be used in addition to oxygen.

また、前記の図6(工程5)において、酸素プラズマ処理条件と絶縁耐圧について実験した結果について説明する。
図9は、酸素プラズマ処理条件と絶縁耐圧の関係を示す図である。図中の○は絶縁耐圧向上、△は絶縁耐圧変化なし、×は絶縁耐圧低下を示す。
In addition, the results of experiments on the oxygen plasma processing conditions and the withstand voltage in FIG. 6 (step 5) will be described.
FIG. 9 is a diagram showing the relationship between oxygen plasma treatment conditions and withstand voltage. In the figure, ◯ indicates that the withstand voltage is improved, Δ indicates no change in withstand voltage, and x indicates a decrease in withstand voltage.

酸素プラズマ表面処理条件として、プラズマのパワーPは200W〜600W、プラズマ処理時間tは30秒700秒である。プラズマのパワーPやプラズマの処理時間tがこの範囲を超えると、熱酸化膜が成長してプラズマ酸化膜から膜質が変質する。そのため、密着性が低下して絶縁耐量が低下する。一方、この範囲より小さい場合は、プラズマ酸化膜の厚みが薄くなり、やはり密着性が低下して絶縁耐量が低下する。また、プラズマのパワーPが250W〜600W、プラズマ処理時間tが30秒〜600秒の範囲が絶縁耐圧向上の面からさらに好ましい。   As oxygen plasma surface treatment conditions, the plasma power P is 200 W to 600 W, and the plasma treatment time t is 30 seconds to 700 seconds. If the plasma power P or the plasma processing time t exceeds this range, the thermal oxide film grows and the film quality is changed from the plasma oxide film. Therefore, the adhesiveness is lowered and the insulation resistance is lowered. On the other hand, when the thickness is smaller than this range, the thickness of the plasma oxide film is reduced, the adhesion is also lowered, and the dielectric strength is lowered. Further, it is more preferable that the plasma power P is 250 W to 600 W and the plasma processing time t is 30 seconds to 600 seconds from the viewpoint of improving the dielectric strength.

また、図9から分かるように、好ましい酸素プラズマ表面処理条件には、プラズマのパワーPとプラズマ処理時間tの関係には逆比例の関係がある。図18はこの関係を示したものであり、斜線部が好ましい条件の範囲を示している。従って、図9、18の範囲内で、プラズマのパワーPを増大させたときは、プラズマ処理時間tを減少させると、絶縁耐量を向上させることができる。なお、絶縁耐量が向上する理由は不明であるが、上記の条件においてプラズマ酸化膜の膜厚が数nm以上になるとシリコーンゲル9の密着性が向上する。   Further, as can be seen from FIG. 9, in the preferable oxygen plasma surface treatment conditions, the relationship between the plasma power P and the plasma treatment time t has an inversely proportional relationship. FIG. 18 shows this relationship, and the shaded area indicates the range of preferable conditions. Accordingly, when the plasma power P is increased within the range of FIGS. 9 and 18, the dielectric strength can be improved by reducing the plasma processing time t. Although the reason why the dielectric strength is improved is unknown, the adhesion of the silicone gel 9 is improved when the thickness of the plasma oxide film is several nm or more under the above conditions.

本実施例では前記の工程5の酸素プラズマ表面処理をした後で、前記の工程6の予備加熱することで、シリコーンゲル9が密着する相手側の導電パターン付絶縁基板1およびパワー半導体チップ2の表面が乾燥し、湿気が除去される。そのため、予備加熱しない場合に比べて、シリコーンゲル9と導電パターン付絶縁基板1やパワー半導体チップ2との密着性を向上させることができる。   In this embodiment, after the oxygen plasma surface treatment in the above step 5 is performed, the preheating in the above step 6 is performed so that the insulating substrate 1 with the conductive pattern and the power semiconductor chip 2 on the other side to which the silicone gel 9 is in close contact. The surface is dried and moisture is removed. Therefore, compared with the case where it does not preheat, the adhesiveness of the silicone gel 9, and the insulated substrate 1 with a conductive pattern, and the power semiconductor chip 2 can be improved.

前記の図7(工程6)において、予備加熱条件としては、加熱温度は100℃以上で200℃以下、加熱時間は30分以上で2時間以下がよい。この範囲から外れると酸化や不十分な湿気除去などの不具合が生じる。   In FIG. 7 (Step 6), as preheating conditions, the heating temperature is preferably 100 ° C. or more and 200 ° C. or less, and the heating time is 30 minutes or more and 2 hours or less. Outside this range, problems such as oxidation and insufficient moisture removal occur.

前記のように、酸素プラズマ表面処理工程と、シリコーンゲルを注入する前の予備加熱工程の組み合わせにより、シリコーンゲル9と導電パターン付絶縁基板1間での密着性、シリコーンゲル9とパワー半導体チップ1間での密着性を改善できる。   As described above, the combination of the oxygen plasma surface treatment step and the preheating step before injecting the silicone gel allows the adhesion between the silicone gel 9 and the insulating substrate 1 with the conductive pattern, the silicone gel 9 and the power semiconductor chip 1. The adhesion between the two can be improved.

密着性が改善することで、高温環境(例えば、150℃程度)下でのパワー半導体装置の絶縁耐圧の低下が防止され、パワー半導体装置の信頼性を向上させることができる。
図10は、本発明の製造方法を適用したときのIGBTモジュール温度と絶縁破壊耐圧の関係を示す図である。
By improving the adhesion, a reduction in the withstand voltage of the power semiconductor device under a high temperature environment (for example, about 150 ° C.) can be prevented, and the reliability of the power semiconductor device can be improved.
FIG. 10 is a diagram showing the relationship between the IGBT module temperature and the dielectric breakdown voltage when the manufacturing method of the present invention is applied.

常温での絶縁破壊電圧が7.0kV〜8.0kV程度である場合、150℃の高温では7.0kV〜9.5kV程度の絶縁破壊電圧となる。従来の製造方法での高温での絶縁破壊電圧と本発明の高温での絶縁破壊電圧を比べると確実に本発明の製造方法を適用したIGBTモジュールの高温での絶縁破壊電圧は高くなっている。   When the breakdown voltage at room temperature is about 7.0 kV to 8.0 kV, the breakdown voltage is about 7.0 kV to 9.5 kV at a high temperature of 150 ° C. When the breakdown voltage at a high temperature in the conventional manufacturing method is compared with the breakdown voltage at a high temperature of the present invention, the breakdown voltage at a high temperature of the IGBT module to which the manufacturing method of the present invention is surely applied is high.

つまり、本実施例では、半導体装置の製造方法において、酸素プラズマ表面処理工程と、シリコーンゲル注入前の予備加熱工程を組み合わせることにより、シリコーンゲル(保護材)と導電パターン付絶縁基板および半導体チップとの密着性を向上させることができるので、パワー半導体装置の絶縁耐圧を向上させることができる。   That is, in this embodiment, in the method of manufacturing a semiconductor device, by combining an oxygen plasma surface treatment step and a preheating step before silicone gel injection, a silicone gel (protective material), an insulating substrate with a conductive pattern, and a semiconductor chip Therefore, the withstand voltage of the power semiconductor device can be improved.

なお、前記の工程6は、前記工程7の直前に入れた場合について説明した。これは、前記工程7の直前に入れると前記工程7までの放置時間が短くなり好ましいからである。しかし、前記工程7の直前に入れずに、前記工程2と前記工程7の間の工程に入れても絶縁耐圧の向上は見られた。   In addition, the said process 6 demonstrated the case where it put just before the said process 7. FIG. This is because it is preferable to put it immediately before the step 7 because the standing time until the step 7 is shortened. However, even if the process is not performed immediately before the process 7 but is performed between the process 2 and the process 7, the breakdown voltage is improved.

このパワー半導体装置の絶縁性能を確保する保護材として、シリコーンゲル9について説明したが、絶縁性と弾力性が高い保護材であればこれに限るものではない。また、パワー半導体装置の樹脂ケースが比較的小さい場合には、エポキシ樹脂を用いることもある。   Although the silicone gel 9 has been described as a protective material for ensuring the insulating performance of the power semiconductor device, the protective material is not limited to this as long as the protective material has high insulation and elasticity. Moreover, when the resin case of the power semiconductor device is relatively small, an epoxy resin may be used.

特に、SiCやGaNで製造されるパワー半導体装置では、樹脂ケース5の大きさが比較的小さく、また高温動作のために、保護材としてエポキシ樹脂を用いる。この場合も本発明の製造方法を用いることで同様の効果を得ることができる。   In particular, in a power semiconductor device manufactured from SiC or GaN, the size of the resin case 5 is relatively small, and an epoxy resin is used as a protective material for high-temperature operation. In this case, the same effect can be obtained by using the manufacturing method of the present invention.

1 導電パターン付絶縁基板
2 パワー半導体チップ
3 ボンディングワイヤ
4 放熱ベース
5 樹脂ケース
6 外部導出端子
7 電極
8 恒温槽
9 シリコーンゲル
10 酸素
DESCRIPTION OF SYMBOLS 1 Insulation board | substrate with a conductive pattern 2 Power semiconductor chip 3 Bonding wire 4 Radiation base 5 Resin case 6 External lead-out terminal 7 Electrode 8 Thermostatic bath 9 Silicone gel 10 Oxygen

Claims (5)

放熱ベース上に接合された導電パターン付絶縁基板と、該導電パターン付絶縁基板上に接合した半導体チップと、前記導電パターン付絶縁基板および前記半導体チップを収納し前記放熱ベースに接着された樹脂ケースと、該樹脂ケース内に充填された保護材とを備えるパワー半導体装置の製造方法において、
導電パターン付絶縁基板上に半導体チップを接合する工程と、
放熱ベースに前記導電パターン付絶縁基板を接合する工程と、
前記放熱ベースに樹脂ケースを接着する工程と、
前記放熱パターン付絶縁基板の表面および前記半導体チップの表面に酸素プラズマ表面処理を施す工程と、
前記放熱パターン付絶縁基板および前記半導体チップを高温加熱し、湿気を除去する工程と、
樹脂ケース内に保護材を充填する工程と、
を含むことを特徴とするパワー半導体装置の製造方法。
Insulating substrate with conductive pattern bonded on heat dissipation base, semiconductor chip bonded on insulating substrate with conductive pattern, and resin case containing said insulating substrate with conductive pattern and said semiconductor chip and bonded to said heat dissipation base And a manufacturing method of a power semiconductor device comprising a protective material filled in the resin case,
Bonding a semiconductor chip on an insulating substrate with a conductive pattern;
Bonding the insulating substrate with a conductive pattern to a heat dissipation base;
Bonding a resin case to the heat dissipation base;
Performing oxygen plasma surface treatment on the surface of the insulating substrate with a heat radiation pattern and the surface of the semiconductor chip;
Heating the insulating substrate with a heat radiation pattern and the semiconductor chip at a high temperature to remove moisture;
Filling the resin case with a protective material;
The manufacturing method of the power semiconductor device characterized by the above-mentioned.
前記酸素プラズマ表面処理条件において、プラズマのパワーが200W〜600Wであり、プラズマ処理時間が30秒〜700秒であり、酸素(O)の流量が30ml/分〜100ml/分であることを特徴とする請求項1に記載のパワー半導体装置の製造方法。 In the oxygen plasma surface treatment conditions, the plasma power is 200 W to 600 W, the plasma treatment time is 30 seconds to 700 seconds, and the flow rate of oxygen (O 2 ) is 30 ml / min to 100 ml / min. A method for manufacturing a power semiconductor device according to claim 1. 前記の高温加熱の条件は、温度は100℃以上で200℃以下、加熱時間は30分以上で2時間以下であることを特徴とする請求項1に記載のパワー半導体装置の製造方法。   2. The method of manufacturing a power semiconductor device according to claim 1, wherein the high-temperature heating conditions are a temperature of 100 ° C. to 200 ° C. and a heating time of 30 minutes to 2 hours. 前記保護材がシリコーンゲルもしくはエポキシ樹脂であることを特徴とする請求項1に記載のパワー半導体装置の製造方法。   The method for manufacturing a power semiconductor device according to claim 1, wherein the protective material is silicone gel or epoxy resin. 前記導電パターン付絶縁基板を構成する絶縁基板の材質が、Al、SiもしくはAlNであり、導電パターンの材質が銅であることを特徴とする請求項1に記載のパワー半導体装置の製造方法。 2. The power semiconductor according to claim 1, wherein a material of an insulating substrate constituting the insulating substrate with a conductive pattern is Al 2 O 3 , Si 3 N 4 or AlN, and a material of the conductive pattern is copper. Device manufacturing method.
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