JP2009105266A - Method of manufacturing semiconductor apparatus - Google Patents

Method of manufacturing semiconductor apparatus Download PDF

Info

Publication number
JP2009105266A
JP2009105266A JP2007276454A JP2007276454A JP2009105266A JP 2009105266 A JP2009105266 A JP 2009105266A JP 2007276454 A JP2007276454 A JP 2007276454A JP 2007276454 A JP2007276454 A JP 2007276454A JP 2009105266 A JP2009105266 A JP 2009105266A
Authority
JP
Japan
Prior art keywords
surface electrode
lead frame
melting point
semiconductor device
igbt chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2007276454A
Other languages
Japanese (ja)
Inventor
Katsuhiko Yoshihara
克彦 吉原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Device Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Device Technology Co Ltd filed Critical Fuji Electric Device Technology Co Ltd
Priority to JP2007276454A priority Critical patent/JP2009105266A/en
Publication of JP2009105266A publication Critical patent/JP2009105266A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754—Coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754—Coating
    • H01L2224/37599—Material
    • H01L2224/376—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73219—Layer and TAB connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/842—Applying energy for connecting
    • H01L2224/8421—Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/84214—Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor apparatus inexpensively fixing a surface electrode on a semiconductor chip to a lead frame in a short time by laser welding without damaging the semiconductor chip. <P>SOLUTION: A low-melting-point metal 27 is arranged on a surface of the lead frame 21 or a surface electrode 8 of an IGBT chip 7, and the low-melting-point metal 27 is melted, thereby the lead frame 21 and the surface electrode 27 on the IGBT chip 7 can be laser-welded to each other without melting the surface electrode 27 by a laser beam. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

この発明は、ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）モジュールなどの半導体装置の製造方法に関する。   The present invention relates to a method of manufacturing a semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) module.

図２は、従来の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図である。この半導体装置は例えばＩＧＢＴであり、その製造方法も含めて説明する。
放熱ベースとなる銅ベース１と、裏面銅箔３・セラミックス４・コレクタ銅箔５からなる絶縁基板５０とを、はんだ２で接合し、ＩＧＢＴチップ７と、裏面銅箔３・セラミックス４・コレクタ銅箔５からなる絶縁基板５０とを、はんだ６で接合する。通常、これらのはんだ２及びはんだ６による接合（固着）は同時に行われる。
すなわち、銅ベース１の上面にはんだ２を配置し、さらにその上面に裏面銅箔３・セラミックス４・コレクタ銅箔５からなる絶縁基板５０を重ね、その上面にはんだ６を重ね、その上面にＩＧＢＴチップ７を重ねた状態でＮ2又はＨ2ガスで還元された雰囲気中で加熱することで、はんだ２及びはんだ６を同時に溶融させた状態で真空引きを行い、はんだ層中に残存する気泡を除去する。
所定時間加熱・真空引きした後、冷却することではんだ２及びはんだ６が再凝固し、銅ベース１と裏面銅箔３・セラミックス４・コレクタ銅箔５からなる絶縁基板５０と、裏面銅箔３・セラミックス４・コレクタ銅箔５からなる絶縁基板５０とＩＧＢＴチップ７とが接合される。 2A and 2B are configuration diagrams of a conventional semiconductor device, in which FIG. 2A is a plan view of the main part, and FIG. 2B is a cross-sectional view of the main part taken along line XX in FIG. . This semiconductor device is, for example, an IGBT and will be described including its manufacturing method.
A copper base 1 serving as a heat dissipation base and an insulating substrate 50 comprising a back surface copper foil 3, ceramics 4, and collector copper foil 5 are joined with solder 2, and an IGBT chip 7, back surface copper foil 3, ceramics 4, and collector copper are joined. The insulating substrate 50 made of the foil 5 is joined with the solder 6. Usually, joining (fixing) by these solder 2 and solder 6 is performed simultaneously.
That is, the solder 2 is disposed on the upper surface of the copper base 1, the insulating substrate 50 made of the back surface copper foil 3, the ceramic 4, and the collector copper foil 5 is stacked on the upper surface, the solder 6 is stacked on the upper surface, and the IGBT is stacked on the upper surface. By heating in an atmosphere reduced with N 2 or H 2 gas in a state where the chips 7 are stacked, vacuuming is performed in a state where the solder 2 and the solder 6 are melted at the same time, and bubbles remaining in the solder layer are removed. Remove.
The solder 2 and the solder 6 are re-solidified by heating and evacuating for a predetermined time and then cooling, and the insulating substrate 50 including the copper base 1, the back surface copper foil 3, the ceramic 4 and the collector copper foil 5, and the back surface copper foil 3 The insulating substrate 50 made of the ceramic 4 and the collector copper foil 5 and the IGBT chip 7 are joined.

次に、エミッタ端子１１・ゲート端子１２・コレクタ端子１３がインサート成型またはアウトサート成型された樹脂ケース１０を接着剤１６を用いて銅ベース１に嵌合させ、加熱することで接着剤１６を硬化して接合される。樹脂ケース１０には、ＰＢＴ（ポリブチレンテレフタレート）やＰＰＳ（ポリフェニレンサルファイド）などのエンジニアリングプラスチックが用いられる。接着剤１６にはシリコーン系接着剤が用いられる。接着剤の硬化のための加熱は、先に再凝固させたはんだ２及びはんだ６の溶融温度以下、例えば１５０℃で行われる。
次に、ＩＧＢＴチップ７上に形成された表面電極８と、樹脂ケース１０に具備されたエミッタ端子１１をアルミワイヤ１４によって電気的に接続する。同様に、コレクタ銅箔５とコレクタ端子１３をアルミワイヤ１７によって電気的に接続する。また、ＩＧＢＴチップ７の表面に形成されたゲートパッド９とゲート端子１２をアルミワイヤ１５によって電気的に接続する。
これらのアルミワイヤ１４・アルミワイヤ１７・アルミワイヤ１５は、加圧力を加えながら超音波振動によりアルミワイヤ端部を振動させることで、表面電極８・ゲートパッド９・アルミワイヤ１４・アルミワイヤ１７・アルミワイヤ１５表面の酸化膜を除去しながら摺動による摩擦熱でアルミワイヤ自身が軟化し、塑性流動を伴いながら相手材に金属学的に接合する。 Next, the resin case 10 in which the emitter terminal 11, the gate terminal 12, and the collector terminal 13 are insert-molded or outsert-molded is fitted to the copper base 1 using the adhesive 16 and heated to cure the adhesive 16. Are joined together. For the resin case 10, an engineering plastic such as PBT (polybutylene terephthalate) or PPS (polyphenylene sulfide) is used. A silicone adhesive is used for the adhesive 16. Heating for curing the adhesive is performed at a temperature equal to or lower than the melting temperature of the re-solidified solder 2 and solder 6, for example, 150 ° C.
Next, the surface electrode 8 formed on the IGBT chip 7 and the emitter terminal 11 provided in the resin case 10 are electrically connected by an aluminum wire 14. Similarly, the collector copper foil 5 and the collector terminal 13 are electrically connected by an aluminum wire 17. Further, the gate pad 9 formed on the surface of the IGBT chip 7 and the gate terminal 12 are electrically connected by an aluminum wire 15.
These aluminum wire 14, aluminum wire 17, and aluminum wire 15 are made to vibrate the end portion of the aluminum wire by ultrasonic vibration while applying pressure, so that the surface electrode 8, the gate pad 9, the aluminum wire 14, the aluminum wire 17, While removing the oxide film on the surface of the aluminum wire 15, the aluminum wire itself is softened by frictional heat generated by sliding, and is metallurgically bonded to the counterpart material with plastic flow.

インバータ等に用いられるパワーモジュールでは、電流容量が数１０Ａ〜数１００ＡのＩＧＢＴチップを搭載するため、ＩＧＢＴチップ７とエミッタ端子１１及びコレクタ銅箔５とコレクタ端子１３の電気的接続に用いられるアルミワイヤ１４およびアルミワイヤ１７は、線径３００μｍ〜５００μｍのものが用いられる。
アルミワイヤの必要本数は、その線径と配線長さによって様々であるが、例えば、定格１００ＡのＩＧＢＴチップで線径４００μｍのアルミワイヤを使用した場合、アルミワイヤは８本必要となる。これはアルミワイヤ１本あたりの許容電流を１２．５Ａとした場合である。この許容電流はアルミワイヤの溶断電流で決められる。電流定格が大きくなればなるほど、アルミワイヤ１４およびびアルミワイヤ１７の本数を増やさなくてはならない。
この後、絶縁保護のために図示しないシリコーンゲルを樹脂ケース１０内に充填・加熱硬化させ、図２に示した従来の半導体装置が完成する。
ここで示した従来の半導体装置では、簡略化のためにＩＧＢＴチップが１つの場合を示したが、インバータ動作をさせる場合には、この他にダイオードが必要となる。また、ＩＧＢＴとダイオードを複数組み合わせたモジュールでも、上述したのと同様な工程で作られる。 In a power module used for an inverter or the like, since an IGBT chip having a current capacity of several tens to several hundreds of A is mounted, an aluminum wire used for electrical connection between the IGBT chip 7, the emitter terminal 11, the collector copper foil 5, and the collector terminal 13 is used. 14 and the aluminum wire 17 have a wire diameter of 300 μm to 500 μm.
The required number of aluminum wires varies depending on the wire diameter and wiring length. For example, when an aluminum wire with a wire diameter of 400 μm is used with a rated 100 A IGBT chip, 8 aluminum wires are required. This is a case where the allowable current per aluminum wire is 12.5A. This allowable current is determined by the fusing current of the aluminum wire. As the current rating increases, the number of aluminum wires 14 and aluminum wires 17 must be increased.
Thereafter, a silicone gel (not shown) is filled in the resin case 10 and heat-cured for insulation protection, and the conventional semiconductor device shown in FIG. 2 is completed.
In the conventional semiconductor device shown here, the case where there is one IGBT chip is shown for the sake of simplification. However, when an inverter operation is performed, another diode is required. Also, a module in which a plurality of IGBTs and diodes are combined can be manufactured by the same process as described above.

また、特許文献１には、リードフレームと半導体素子の表面側素子電極とを低融点金属層を介して加熱加圧して両者を固着することが開示されている。
また、特許文献２には、金属部材の溶接部にレーザ光の吸収を高める表面処理を施し、金属部材同士をレーザ溶接することが開示されている。
また、特許文献３には、リードフレームと放熱板の少なくとも一方の表面を錫もしくは錫合で被覆した後でＹＡＧレーザ溶接することが開示されている。
特開２００４−１１１９３６号公報 特開平１０−１８０４７８号公報 特開平１１−１９１６０７号公報 Patent Document 1 discloses that a lead frame and a surface element electrode of a semiconductor element are heated and pressed through a low melting point metal layer to fix them together.
Patent Document 2 discloses that a metal member is subjected to a surface treatment for enhancing the absorption of laser light and the metal members are laser-welded to each other.
Patent Document 3 discloses YAG laser welding after covering at least one surface of a lead frame and a heat sink with tin or tin alloy.
JP 2004-111936 A JP-A-10-180478 JP 11-191607 A

前記した図２の従来の半導体装置において、次のような課題がある。
第１の課題は、ＩＧＢＴチップ表面におけるアルミワイヤの接合可能面積の縮小である。従来の半導体装置では低コスト化のため、ＩＧＢＴチップ７の製造歩留まりを向上させる必要があり、このためには１枚のシリコンウェハから取り出せるＩＧＢＴチップ７の個数（取れ数）を増やすことが効果的である。
ＩＧＢＴチップ７を小型化することで取れ数を増やすことが可能となるが、ＩＧＢＴチップ７の小型化にともない、ＩＧＢＴチップ７の表面に形成されている表面電極８の面積も縮小される。この場合、アルミワイヤの溶断電流から決められたアルミワイヤの必要本数分の接合領域が確保できなくなる。
例えば１００Ａで８本必要だったアルミワイヤが、同１００Ａで６本しか接合できなくなった場合、アルミワイヤ１本当たりに電流が１６．７Ａ流れることとなり、アルミワイヤの発するジュール熱でアルミワイヤが溶断してしまう。
このため、アルミワイヤの線径を太くし、アルミワイヤ１本あたりの通電可能電流を増やすことが考えられるが、線径が太くなった場合には、超音波接合時における加圧力も大きくしなければ接合できなくなる。加圧力を大きくした場合、ＩＧＢＴチップ７を損傷する確率が高くなり、逆に歩留まりが低下してしまうため、アルミワイヤ線径の拡大によるＩＧＢＴチップ７表面の接合可能面積縮小化には限界がある。 The conventional semiconductor device shown in FIG. 2 has the following problems.
The first problem is to reduce the area where the aluminum wire can be bonded on the surface of the IGBT chip. In the conventional semiconductor device, it is necessary to improve the manufacturing yield of the IGBT chip 7 in order to reduce the cost. For this purpose, it is effective to increase the number of IGBT chips 7 that can be taken out from one silicon wafer. It is.
Although the number can be increased by reducing the size of the IGBT chip 7, the area of the surface electrode 8 formed on the surface of the IGBT chip 7 is reduced as the size of the IGBT chip 7 is reduced. In this case, it becomes impossible to secure a bonding area for the required number of aluminum wires determined from the fusing current of the aluminum wires.
For example, if only 6 wires can be joined at 100A, only 6 wires can be joined at 100A, the current will flow 16.7A per aluminum wire, and the aluminum wire will melt due to the Joule heat generated by the aluminum wire. Resulting in.
For this reason, it is conceivable to increase the wire diameter of the aluminum wire and increase the current that can be energized per aluminum wire. However, if the wire diameter increases, the applied pressure during ultrasonic bonding must also be increased. If it is not possible to join. If the applied pressure is increased, the probability of damaging the IGBT chip 7 is increased, and conversely, the yield is lowered. Therefore, there is a limit to the reduction of the bondable area on the surface of the IGBT chip 7 by increasing the aluminum wire diameter. .

第２の課題は、ＩＧＢＴチップ７およびアルミワイヤ１４・アルミワイヤ１７から生じるジュール熱の低減である。
ＩＧＢＴチップ７が流すことのできる最大電流は、ＩＧＢＴチップ７の内部に形成されたｐｎ接合部（ｐ型半導体とｎ型半導体の接した部分）の最高接合温度（定格接合温度、Ｔｊｍａｘ：ＩＧＢＴの場合、通常１５０℃程度である）で決まっている。動作中の接合温度Ｔｊが高くなり最高接合温度Ｔｊｍａｘを超すと、電流制御ができなくなって熱暴走状態となり、チップの破壊に至る。
この動作中の接合温度Ｔｊを下げることができれば、最高接合温度Ｔｊｍａｘに達する電流を増大できて、同じＩＧＢＴチップ７でも電流を多く流すことができるようになる。つまり、同じ電流を流す場合にはＩＧＢＴチップ７を小さくできるので、ＩＧＢＴモジュールなどの半導体装置を小型化できる。
しかしながら、チップ取れ数の増加を狙ってＩＧＢＴチップ７を小型化すると、電流密度が高くなり動作中の接合温度Ｔｊも上昇してしまう。このために、コレクタ銅箔５や裏面銅箔３を厚くしてＩＧＢＴチップ７の裏面からの放熱効率を上げる方法や、セラミックス４の材料をより高熱伝導率の材料にする方法があるが、どちらもコストが高くなってしまうという課題がある。 A second problem is the reduction of Joule heat generated from the IGBT chip 7 and the aluminum wires 14 and 17.
The maximum current that the IGBT chip 7 can flow is the maximum junction temperature (rated junction temperature, Tjmax: IGBT) of the pn junction part (the part where the p-type semiconductor and the n-type semiconductor are in contact) formed inside the IGBT chip 7. In the case, it is usually about 150 ° C.). If the junction temperature Tj during operation increases and exceeds the maximum junction temperature Tjmax, current control becomes impossible and a thermal runaway state occurs, leading to chip destruction.
If the junction temperature Tj during this operation can be lowered, the current reaching the maximum junction temperature Tjmax can be increased, and a large amount of current can flow even in the same IGBT chip 7. That is, since the IGBT chip 7 can be made small when the same current flows, a semiconductor device such as an IGBT module can be downsized.
However, if the IGBT chip 7 is downsized to increase the number of chips that can be taken, the current density increases and the junction temperature Tj during operation also increases. For this purpose, there are a method of increasing the heat radiation efficiency from the back surface of the IGBT chip 7 by increasing the thickness of the collector copper foil 5 and the back surface copper foil 3, and a method of making the material of the ceramic 4 a material having higher thermal conductivity. However, there is a problem that the cost becomes high.

また、上述したコレクタ銅箔５や裏面銅箔３の厚化や、セラミックス４の高熱伝導率化を行った場合でも、アルミワイヤ１４やアルミワイヤ１７から発生するジュール熱が問題となる。ＩＧＢＴチップ７から電流をより多く取り出した場合、アルミワイヤ１４やアルミワイヤ１７の１本あたりの電流値が増加し、アルミワイヤから発生するジュール熱が増えるためにＩＧＢＴチップ７の温度が上昇し、動作中の接合温度Ｔｊが高くなってしまう。
このためにアルミワイヤ１４やアルミワイヤ１７の線径を太くし、抵抗を低くすることが効果的であるが、線径を太くした場合には、第１の課題に示したように、超音波接合時にＩＧＢＴチップ７を損傷してしまう確率が高くなってしまうという課題が生じる。
このように、従来のアルミワイヤによる配線方法では限界があった。
上述の課題を解決するため、図３に示すＩＧＢＴチップ上の配線構造が考えられる。この構造においては、従来のアルミワイヤに代わってリードフレーム２１を使用する。リードフレーム２１は銅や銅合金が使用されるため、アルミワイヤよりも電気抵抗・熱抵抗が低く、ジュール熱の発生量を低減することができる。また、ＩＧＢＴチップ７の小型化にともなう表面電極８上の接合面積の縮小化にも、リードフレームは従来のアルミワイヤのような点接合ではなく面接合となるため、有利となる。 Further, even when the collector copper foil 5 or the back copper foil 3 is thickened or the ceramic 4 is increased in thermal conductivity, the Joule heat generated from the aluminum wire 14 or the aluminum wire 17 becomes a problem. When more current is extracted from the IGBT chip 7, the current value per one of the aluminum wire 14 and the aluminum wire 17 increases, and the temperature of the IGBT chip 7 rises because Joule heat generated from the aluminum wire increases. The junction temperature Tj during operation becomes high.
For this reason, it is effective to increase the wire diameter of the aluminum wire 14 or the aluminum wire 17 and reduce the resistance. However, when the wire diameter is increased, as shown in the first problem, the ultrasonic wave There arises a problem that the probability of damaging the IGBT chip 7 at the time of bonding increases.
Thus, the conventional wiring method using aluminum wires has a limit.
In order to solve the above-mentioned problem, a wiring structure on the IGBT chip shown in FIG. 3 can be considered. In this structure, a lead frame 21 is used in place of the conventional aluminum wire. Since the lead frame 21 is made of copper or a copper alloy, the electrical resistance / thermal resistance is lower than that of the aluminum wire, and the generation amount of Joule heat can be reduced. In addition, the lead frame is advantageous in reducing the bonding area on the surface electrode 8 with the miniaturization of the IGBT chip 7 because the lead frame is not a point bonding like a conventional aluminum wire but a surface bonding.

このリードフレーム２１とＩＧＢＴチップ７上の表面電極８との接合は、はんだ１９を用いるのが一般的である。ＩＧＢＴチップ７上の表面電極８はアルミニウムあるいはアルミニウム合金（Ａｌ−Ｓｉなど）が一般的であり、電極表面にできた酸化膜によってはんだが濡れにくくなっているので、表面電極８上には通常、ニッケル−金めっきが被覆される。
しかし、リ−ドフレーム２１とＩＧＢＴチップ７上の表面電極８をはんだ１９で固着する工程で、すでにコレクタ銅箔５とはんだ６で固着しているＩＧＢＴチップ７が、このはんだ６の再溶融により回転するという不具合を生じることがある。これを解決するために、レーザ溶接でリードフレーム２１とＩＧＢＴチップ７の表面電極８を固着する方法が考えられるが、次のような不具合がある。
図４は、レーザ溶接した場合の不具合を説明する図であり、同図（ａ）は半導体装置の要部断面図、同図（ｂ）は同図（ａ）のＢ部拡大図である。尚、リードフレーム２１の表面にはレーザ光の吸収を良くするためのニッケル膜３１が被覆されている。
表面電極８とリードフレーム２１とをレーザ溶接で固着させるために、レーザ光によってニッケル膜３１が被覆されているリードフレーム２１を溶融させる。溶融部３２が表面電極８に達すると、表面電極８が溶融する。表面電極８は薄いのでこの溶融部３２はＩＧＢＴチップ７（シリコン面）に到達する。 For joining the lead frame 21 and the surface electrode 8 on the IGBT chip 7, a solder 19 is generally used. The surface electrode 8 on the IGBT chip 7 is generally made of aluminum or an aluminum alloy (Al—Si or the like), and the solder is hardly wetted by an oxide film formed on the electrode surface. Nickel-gold plating is coated.
However, in the process of fixing the lead frame 21 and the surface electrode 8 on the IGBT chip 7 with the solder 19, the IGBT chip 7 that has already been fixed with the collector copper foil 5 and the solder 6 is remelted. It may cause a problem of rotating. In order to solve this, a method of fixing the lead frame 21 and the surface electrode 8 of the IGBT chip 7 by laser welding can be considered, but there are the following problems.
FIGS. 4A and 4B are diagrams for explaining defects in the case of laser welding, where FIG. 4A is a cross-sectional view of the main part of the semiconductor device, and FIG. 4B is an enlarged view of part B of FIG. The surface of the lead frame 21 is covered with a nickel film 31 for improving the absorption of laser light.
In order to fix the surface electrode 8 and the lead frame 21 by laser welding, the lead frame 21 covered with the nickel film 31 is melted by laser light. When the melting part 32 reaches the surface electrode 8, the surface electrode 8 is melted. Since the surface electrode 8 is thin, the melting part 32 reaches the IGBT chip 7 (silicon surface).

そうすると、図４（ｂ）に示すように、ＩＧＢＴチップ７の表面層が溶融して損傷し（損傷部３０）特性劣化を招く。そのため損傷部３０が形成されないようにするために、溶融部３２がＩＧＢＴチップ７の表面電極８に達しないようにして、リードフレーム２１の表面層のみに溶融部３２を形成するようにする。しかしこれでは、リードフレーム２１の下面が溶融しないので、表面電極８とリードフレーム２１はレーザ溶接されない。つまり、レーザ溶接でリードフレーム２１と表面電極８を直接固着することは困難である。
また、特許文献１では、加熱は１０秒から１８０秒行うことが段落００９４に記載されており、高温炉を用いての加熱と推測され、数１０ｍｓ程度の短時間加熱できるレーザ溶接ついては記載されていない。
また、特許文献２、特許文献３には、半導体チップ上の表面電極とリードフレームを直接固着することは記載されていない。
この発明の目的は、前記の課題を解決して、低コストで半導体チップに損傷を与えることなくリードフレームと半導体チップの表面電極とを短時間でレーザ溶接できる半導体装置の製造方法を提供することにある。 Then, as shown in FIG. 4B, the surface layer of the IGBT chip 7 is melted and damaged (damaged portion 30), resulting in deterioration of characteristics. Therefore, in order to prevent the damaged portion 30 from being formed, the melted portion 32 is formed only on the surface layer of the lead frame 21 so that the melted portion 32 does not reach the surface electrode 8 of the IGBT chip 7. However, in this case, since the lower surface of the lead frame 21 is not melted, the surface electrode 8 and the lead frame 21 are not laser-welded. That is, it is difficult to directly fix the lead frame 21 and the surface electrode 8 by laser welding.
Further, in Patent Document 1, it is described in paragraph 0094 that heating is performed for 10 seconds to 180 seconds, and it is estimated that the heating is performed using a high-temperature furnace, and laser welding that can be heated in a short time of about several tens of milliseconds is described. Absent.
Further, Patent Document 2 and Patent Document 3 do not describe that the surface electrode on the semiconductor chip and the lead frame are directly fixed.
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-described problems and can perform laser welding of a lead frame and a surface electrode of a semiconductor chip in a short time without damaging the semiconductor chip. It is in.

前記の目的を達成するために、半導体チップ（ＩＧＢＴチップ７）の表面電極８（エミッタ電極）と、外囲器（樹脂ケース１０）に固着した外部導出端子（エミッタ端子１１など）とを有し、該外部導出端子と前記表面電極とが接続導体（リードフレーム２１）で接続する半導体装置の製造方法において、前記表面電極と前記接続導体との固着がレーザ光で前記表面電極を直接溶融させずにレーザ溶接で行われる製造方法とする。レーザ溶接することで高温炉などを用いる場合に比べて短時間で加熱ができる。また、溶融範囲を表面電極下のシリコンに及ばないようにすることで半導体チップが損傷するのを防止できる。
また、前記表面電極と前記接続導体が互いに対向する面の少なくとも一方の面に前記表面電極および前記接続導体の融点より低い低融点金属層が形成されるとよい。接続導体の表面をレーザ光で溶融させ、その熱で低融点金属層を溶融させて表面電極と接続導体を固着する。
また、前記低融点金属層の材質が錫または錫合金であると後述する表面電極やリードフレームより低融点となり、低融点金属層が溶融しても表面電極を溶融させることがなく、半導体チップの損傷を防止できる。
また、前記低融点金属層の厚さは、必要な接合強度を得るために、１μｍ〜２０μｍであるとよい。 In order to achieve the above object, the semiconductor chip (IGBT chip 7) has a surface electrode 8 (emitter electrode) and an external lead terminal (emitter terminal 11 etc.) fixed to the envelope (resin case 10). In the method of manufacturing a semiconductor device in which the external lead-out terminal and the surface electrode are connected by a connection conductor (lead frame 21), the surface electrode and the connection conductor do not directly melt the surface electrode with laser light. The manufacturing method is performed by laser welding. By laser welding, heating can be performed in a shorter time than when a high temperature furnace or the like is used. Further, the semiconductor chip can be prevented from being damaged by preventing the melting range from reaching the silicon below the surface electrode.
A low melting point metal layer lower than the melting point of the surface electrode and the connection conductor may be formed on at least one surface of the surface electrode and the connection conductor facing each other. The surface of the connection conductor is melted by laser light, and the low melting point metal layer is melted by the heat to fix the surface electrode and the connection conductor.
Further, if the material of the low melting point metal layer is tin or a tin alloy, the melting point becomes lower than that of the surface electrode and lead frame described later, and even if the low melting point metal layer is melted, the surface electrode is not melted. Damage can be prevented.
Further, the thickness of the low melting point metal layer is preferably 1 μm to 20 μm in order to obtain a required bonding strength.

また、前記接続導体がリードフレームであるとよい。
また、前記接続導体の材質が，銅または銅合金であると電気伝導や熱伝導の点で好ましい。
また、前記表面電極の材質がアルミニウムまたはシリコンを含有したアルミニウムであると、前記の錫や錫合金で形成した低融点金属層より融点が高くなり、低融点金属層が溶融しても表面電極が溶融せず、半導体チップが損傷しないのでよい。
また、前記レーザ溶接に用いるレーザ光の波長範囲が、０．３３μｍ（半導体レーザ）〜１０．６μｍ（ＣＯ2レーザ）であると接続導体を溶融させるのに好適である。 The connection conductor may be a lead frame.
Moreover, it is preferable that the material of the connection conductor is copper or a copper alloy in terms of electrical conduction and thermal conduction.
Further, when the material of the surface electrode is aluminum or aluminum containing silicon, the melting point is higher than that of the low melting point metal layer formed of the tin or tin alloy, and the surface electrode is not melted even if the low melting point metal layer is melted. It does not melt and the semiconductor chip is not damaged.
Moreover, when the wavelength range of the laser beam used for the laser welding is 0.33 μm (semiconductor laser) to 10.6 μm (CO 2 laser), it is suitable for melting the connection conductor.

この発明によれば、リードフレームの表面もしくは半導体チップ（ＩＧＢＴチップ）の表面電極上に低融点金属層を配置することにより、表面電極をレーザ光で溶融させることなく、リードフレームと半導体チップ上の表面電極をレーザ溶接できる。
レーザ溶接で表面電極を溶融しないために、半導体チップに損傷を与えないようにできる。
また、アルミワイヤ配線に比べてリードフレーム配線は、ＩＧＢＴチップの小型化ができて低コスト化を図ることができる。 According to the present invention, the low melting point metal layer is disposed on the surface of the lead frame or on the surface electrode of the semiconductor chip (IGBT chip), so that the surface electrode is not melted with the laser beam on the lead frame and the semiconductor chip. The surface electrode can be laser welded.
Since the surface electrode is not melted by laser welding, the semiconductor chip can be prevented from being damaged.
Further, the lead frame wiring can reduce the size of the IGBT chip and reduce the cost as compared with the aluminum wire wiring.

実施の形態を以下の実施例で説明する。尚、従来構造と同一な部位には同一な符号を付した。   Embodiments will be described in the following examples. In addition, the same code | symbol was attached | subjected to the site | part same as a conventional structure.

図１は、この発明の第１実施例の半導体装置の製造方法を説明する図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図、同図（ｃ）は同図（ｂ）のＡ部拡大図である。この半導体装置は例えばＩＧＢＴであり、その製造方法も含めて説明する。
図３との違いは、ＩＧＢＴチップの表面電極８（エミッタ電極）とリードフレーム２１（接続導体）の固着をはんだの代わりにレーザ溶接で行なう。また、図４との違いは表面電極８をレーザ光で直接溶融することなく、レーザ光でリードフレーム２１の表面層を溶融させその熱で低融点金属層２７を溶融させてリードフレーム２１と表面電極８を固着（レーザ溶接）する点である。
銅ベース１と、裏面銅箔３・セラミックス４・コレクタ銅箔５からなる絶縁基板５１とを、はんだ２で接合し、ＩＧＢＴチップ７と、裏面銅箔３・セラミックス４・コレクタ銅箔５からなる絶縁基板５１とを、はんだ６で接合する。通常、これらのはんだ２およびはんだ６による接合（固着）は同時に行われる。
すなわち、銅ベース１の上面にはんだ２を配置し、さらにその上面に裏面銅箔３・セラミックス４・コレクタ銅箔５からなる絶縁基板５１を重ね、その上面にはんだ６を重ね、その上面にＩＧＢＴチップ７を重ねた状態でＮ2又はＨ2ガスで還元された雰囲気中で加熱することで、はんだ２およびはんだ６を同時に溶融させた状態で真空引きを行い、はんだ層中に残存する気泡を除去する。 1A and 1B are views for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view of the main part, and FIG. 1B is an XX of FIG. The principal part sectional drawing cut | disconnected by the line | wire, the figure (c) is the A section enlarged view of the figure (b). This semiconductor device is, for example, an IGBT and will be described including its manufacturing method.
The difference from FIG. 3 is that the surface electrode 8 (emitter electrode) and the lead frame 21 (connection conductor) of the IGBT chip are fixed by laser welding instead of solder. Also, the difference from FIG. 4 is that the surface layer of the lead frame 21 is melted by the laser beam and the low melting point metal layer 27 is melted by the laser beam without melting the surface electrode 8 directly by the laser beam. The point is that the electrode 8 is fixed (laser welding).
The copper base 1 and the insulating substrate 51 made of the back surface copper foil 3, the ceramic 4, and the collector copper foil 5 are joined with the solder 2, and the IGBT chip 7, the back surface copper foil 3, the ceramic 4, and the collector copper foil 5 are formed. The insulating substrate 51 is joined with the solder 6. Usually, joining (fixing) by these solder 2 and solder 6 is performed simultaneously.
That is, the solder 2 is disposed on the upper surface of the copper base 1, the insulating substrate 51 made of the back surface copper foil 3, the ceramic 4 and the collector copper foil 5 is stacked on the upper surface, the solder 6 is stacked on the upper surface, and the IGBT is stacked on the upper surface. By heating in an atmosphere reduced with N 2 or H 2 gas in a state where the chips 7 are stacked, vacuuming is performed in a state where the solder 2 and the solder 6 are simultaneously melted, and bubbles remaining in the solder layer are removed. Remove.

所定時間加熱・真空引きした後、冷却することではんだ２およびはんだ６が再凝固し、銅ベース１と裏面銅箔３・セラミックス４・コレクタ銅箔５からなる絶縁基板５０と、裏面銅箔３・セラミックス４・コレクタ銅箔５からなる絶縁基板５０とＩＧＢＴチップ７とが接合される。
次に、エミッタ端子１１・ゲート端子１２・コレクタ端子１３がインサート成型またはアウトサート成型された樹脂ケース１０（外囲器）を接着剤１６を用いて銅ベース１に嵌合させ、加熱することで接着剤１６を硬化して接合される。ここまでは従来と同じである。
次に、ＩＧＢＴチップ７上に形成されたエミッタ電極である表面電極８と、樹脂ケース１０に具備されたエミッタ端子１１をリードフレーム２１によって電気的に接続する。コレクタ銅箔５とコレクタ端子１３をリードフレーム２４によって電気的に接続する。また、従来と同様にＩＧＢＴチップ７の表面に形成されたゲートパッド９とゲート端子１２をアルミワイヤ１５によって電気的に接続する。この電気的接続はレーザ溶接で行われる。その方法について説明する。
図１（ｂ）、図１（ｃ）に示すように、例えば、アルミニウム（Ａｌ）やシリコン含有のアルミニウム（Ａｌ−Ｓｉ）などで形成された表面電極８と対向（対峙）する、例えば、銅や銅合金で形成されたリードフレーム２１の表面に、めっきや真空蒸着法などによって、例えば、錫や錫合金などの前記の表面電極８やリードフレーム２１より低融点の低融点金属層２７を予め形成しておく。この低融点金属層２７はＩＧＢＴチップ７の表面電極８上に形成しても構わないし、場合によっては、両者に被覆しても構わない。 After being heated and evacuated for a predetermined time, the solder 2 and the solder 6 are re-solidified by cooling, an insulating substrate 50 comprising the copper base 1, the back copper foil 3, the ceramic 4 and the collector copper foil 5, and the back copper foil 3 The insulating substrate 50 made of the ceramic 4 and the collector copper foil 5 and the IGBT chip 7 are joined.
Next, the resin case 10 (envelope) in which the emitter terminal 11, the gate terminal 12, and the collector terminal 13 are insert-molded or outsert-molded is fitted to the copper base 1 using the adhesive 16 and heated. The adhesive 16 is cured and joined. The process up to this point is the same as before.
Next, the surface electrode 8 which is an emitter electrode formed on the IGBT chip 7 and the emitter terminal 11 provided in the resin case 10 are electrically connected by the lead frame 21. The collector copper foil 5 and the collector terminal 13 are electrically connected by the lead frame 24. Further, the gate pad 9 formed on the surface of the IGBT chip 7 and the gate terminal 12 are electrically connected by an aluminum wire 15 as in the conventional case. This electrical connection is made by laser welding. The method will be described.
As shown in FIG. 1B and FIG. 1C, for example, copper (eg, copper) facing (opposite) the surface electrode 8 formed of aluminum (Al), silicon-containing aluminum (Al—Si), or the like. A low melting point metal layer 27 having a melting point lower than that of the surface electrode 8 or the lead frame 21 made of, for example, tin or a tin alloy is preliminarily formed on the surface of the lead frame 21 made of or copper alloy by plating or vacuum deposition. Form it. The low melting point metal layer 27 may be formed on the surface electrode 8 of the IGBT chip 7 or may be coated on both.

また、リードフレーム２１の表面全域に低融点金属層２７を形成せずに表面電極８と対向する面のみに形成しても構わない。
また、低融点金属層２７と表面電極８の接合強度を高めるために、表面電極８上を図示しないニッケル−金めっき膜で被覆してもよい。
この低融点金属層２７を形成することで、表面電極８をレーザ光で溶かすことなく、リードフレーム２１の表面層をレーザ光で溶融し（溶融部２２）、その熱で低融点金属膜層２７を溶融することで低融点金属層２７に溶融部２８を形成し、表面電極８とリードフレーム２１とを固着（レーザ溶接）することができる。
つぎに、レーザ溶接についてさらに具体的に説明する。
図１（ｂ）、（ｃ）において、ＩＧＢＴチップ７上の表面電極８に低融点金属層２７を予め形成しておいたリードフレーム２１を重ね、リードフレーム２１の上面（表面電極８に接する面の反対側の面）に図示しないレーザ光を照射する。このレーザ光がリードフレーム２１で吸収され、熱エネルギに変換されることにより溶融部２２が生じる。この溶融部２２は表面電極８に到達しないように、レーザ光の照射条件を選ぶ。
表面電極８と対向したリードフレーム２１の面には、融点の低い低融点金属層２７が形成されているため、リードフレーム２１の溶融部２２が表面金属８と対向する側の低融点金属層２７に到達しなくても、溶融部２２から伝達される熱で低融点金属層２７は溶融して溶融部２８を形成し、この溶融部２８により、リードフレーム２１と表面金属２８とが固着（レーザ溶接）する。 Further, the low melting point metal layer 27 may not be formed on the entire surface of the lead frame 21 but may be formed only on the surface facing the surface electrode 8.
Further, in order to increase the bonding strength between the low melting point metal layer 27 and the surface electrode 8, the surface electrode 8 may be covered with a nickel-gold plating film (not shown).
By forming the low melting point metal layer 27, the surface layer of the lead frame 21 is melted with laser light without melting the surface electrode 8 with laser light (melting portion 22), and the low melting point metal film layer 27 is heated by the heat. Is melted to form a melted portion 28 in the low melting point metal layer 27 and the surface electrode 8 and the lead frame 21 can be fixed (laser welding).
Next, laser welding will be described more specifically.
1B and 1C, a lead frame 21 in which a low melting point metal layer 27 is formed in advance is overlaid on the surface electrode 8 on the IGBT chip 7, and the upper surface of the lead frame 21 (the surface in contact with the surface electrode 8). A laser beam (not shown) is irradiated on the surface opposite to the above. The laser beam is absorbed by the lead frame 21 and converted into heat energy, thereby generating a melting portion 22. The irradiation condition of the laser beam is selected so that the melting part 22 does not reach the surface electrode 8.
Since a low melting point metal layer 27 having a low melting point is formed on the surface of the lead frame 21 facing the surface electrode 8, the low melting point metal layer 27 on the side where the molten portion 22 of the lead frame 21 faces the surface metal 8. However, the low melting point metal layer 27 is melted by the heat transmitted from the melting part 22 to form the melting part 28, and the lead frame 21 and the surface metal 28 are fixed (laser) by the melting part 28. Weld.

例えば、リードフレーム２１に銅を使用し、低融点金属層２７に錫めっき（もしくは錫合金）を使用すると良い。錫めっきの場合、銅の融点は１０８４℃であり、錫の融点は２３２℃であるために、リードフレーム２１の溶融部２２が表面電極８に到達しなくても、熱伝導によりリードフレーム２１の表面電極８に対向した面に形成された低融点金属層２７である錫めっき層を充分溶融する温度にすることができる。
ここで重要なのは、錫めっき層の下部にある表面電極８の融点を超えないことである。これは、表面金属８が溶融し、溶融した低融点金属層２７と同時に凝固すると、ＩＧＢＴチップ７の表面層に機械的な応力を発生させ、ＩＧＢＴチップの耐圧特性などに悪影響を及ぼす惧れがある。そのため、表面電極８は溶融しないようにする。
表面電極８がアルミニウムの場合には、アルミニウムの融点の６６０℃以下となるように、レーザ光の照射条件を設定すると良い。すなわち、表面電極８における温度を、錫の融点以上（２３２℃）でアルミニウムの融点以下（６６０℃）にコントロールする。このレーザ光の波長範囲としては０．３３μｍ（半導体レーザ）〜１０．６μｍ（ＣＯ2レーザ）とするとよい。またレーザ光の照射時間は数１０ｍｓ程度であり、高温炉での加熱（１０秒から１８０秒）に比べて大幅に短縮できるので、このレーザ溶接を用いることで工数低減を図ることができる。 For example, copper may be used for the lead frame 21 and tin plating (or a tin alloy) may be used for the low melting point metal layer 27. In the case of tin plating, since the melting point of copper is 1084 ° C. and the melting point of tin is 232 ° C., even if the melting part 22 of the lead frame 21 does not reach the surface electrode 8, The temperature of the tin plating layer, which is the low melting point metal layer 27 formed on the surface facing the surface electrode 8, can be sufficiently melted.
What is important here is that the melting point of the surface electrode 8 under the tin plating layer is not exceeded. This is because when the surface metal 8 is melted and solidified at the same time as the melted low melting point metal layer 27, a mechanical stress is generated in the surface layer of the IGBT chip 7, which may adversely affect the breakdown voltage characteristics of the IGBT chip. is there. Therefore, the surface electrode 8 is not melted.
When the surface electrode 8 is aluminum, it is preferable to set the irradiation condition of the laser beam so that the melting point of aluminum is 660 ° C. or lower. That is, the temperature of the surface electrode 8 is controlled to be not lower than the melting point of tin (232 ° C.) and not higher than the melting point of aluminum (660 ° C.). The wavelength range of this laser light is preferably 0.33 μm (semiconductor laser) to 10.6 μm (CO 2 laser). Further, the irradiation time of the laser beam is about several tens of milliseconds, which can be significantly shortened compared with heating in a high temperature furnace (from 10 seconds to 180 seconds). Therefore, the number of steps can be reduced by using this laser welding.

また、低融点金属層２７の厚さを１μｍ〜２０μｍの範囲とするとよい。１μｍ未満では、溶融した低融点金属層２７の厚さが薄すぎて表面金属８との固着が弱く、必要とされる接合強度が得られない。また２０μｍを超えても接合強度は変わらないので、２０μｍを超えて厚くする必要はない。
本発明のレーザ溶接は、前述したＩＧＢＴチップ７上の表面電極８とリードフレーム２１間の他に、エミッタ端子１１とリードフレーム２１間、コレクタ銅箔５とリードフレーム２４間、コレクタ端子１３とリードフレーム２４間にも適用している。
これらの部分においては、下側になる金属部材の厚さが０．３ｍｍ〜１ｍｍと厚いため、リードフレーム２１の溶融部２３をエミッタ端子１１に溶け込ませても問題なく、同様にリードフレーム２４の溶融部２６をコレクタ銅箔５およびコレクタ端子１３に溶け込ませても問題ない。
また、図２に示した従来の半導体装置では、ＩＧＢＴチップ７の小型化にともなう表面電極８の縮小により、アルミワイヤ１４の接合可能領域が小さくなり、ＩＧＢＴチップ７の小型化のネックとなっていた。しかし、図１に示した本発明の実施例では、従来のアルミワイヤ１４の代わりにリードフレーム２１を用いることで、ＩＧＢＴチップ７の小型化が可能となる。 The thickness of the low melting point metal layer 27 is preferably in the range of 1 μm to 20 μm. If the thickness is less than 1 μm, the thickness of the molten low melting point metal layer 27 is too thin and the adhesion to the surface metal 8 is weak, and the required bonding strength cannot be obtained. Further, since the bonding strength does not change even if it exceeds 20 μm, it is not necessary to increase the thickness beyond 20 μm.
In the laser welding of the present invention, in addition to the surface electrode 8 and the lead frame 21 on the IGBT chip 7 described above, between the emitter terminal 11 and the lead frame 21, between the collector copper foil 5 and the lead frame 24, and between the collector terminal 13 and the lead. This is also applied between the frames 24.
In these portions, the thickness of the lower metal member is as thick as 0.3 mm to 1 mm. Therefore, there is no problem even if the melting portion 23 of the lead frame 21 is melted into the emitter terminal 11. There is no problem even if the melting part 26 is melted into the collector copper foil 5 and the collector terminal 13.
In the conventional semiconductor device shown in FIG. 2, the area where the aluminum wire 14 can be bonded is reduced due to the reduction of the surface electrode 8 accompanying the downsizing of the IGBT chip 7, which is a bottleneck for downsizing the IGBT chip 7. It was. However, in the embodiment of the present invention shown in FIG. 1, the IGBT chip 7 can be downsized by using the lead frame 21 instead of the conventional aluminum wire 14.

この理由は、従来のアルミワイヤ１４による接合は、例えばφ３００μｍやφ４００μｍといった細線による点接合であったのに比べ、リードフレーム２１による配線では、ＩＧＢＴチップ７上の表面電極８に対して面で接合するため、ＩＧＢＴチップ７の小型化にともなった表面電極８の面積縮小にも充分対応できるためである。
また、リードフレーム２１の材質に銅や銅合金を使用することで、従来のアルミワイヤに比べ低電気抵抗の配線が可能となり、電力損失の改善を図ることができる。
また、低電気抵抗配線となることにより、ジュール発熱が抑えられ、ＩＧＢＴチップ７の動作中の接合温度Ｔｊを低下させることができて、ＩＧＢＴチップ７の下部のはんだ６の長寿命化を図ることができる。 This is because the conventional bonding with the aluminum wire 14 is a point bonding with a thin wire such as φ300 μm or φ400 μm, for example, and the wiring with the lead frame 21 is bonded to the surface electrode 8 on the IGBT chip 7 on the surface. Therefore, it is possible to sufficiently cope with the area reduction of the surface electrode 8 accompanying the miniaturization of the IGBT chip 7.
In addition, by using copper or a copper alloy as the material of the lead frame 21, wiring with a lower electrical resistance than that of a conventional aluminum wire is possible, and power loss can be improved.
Further, by using the low electric resistance wiring, Joule heat generation can be suppressed, the junction temperature Tj during the operation of the IGBT chip 7 can be lowered, and the life of the solder 6 under the IGBT chip 7 can be extended. Can do.

この発明の第１実施例の半導体装置の製造方法を説明する図であり、（ａ）は要部平面図、（ｂ）は（ａ）のＸ−Ｘ線で切断した要部断面図、（ｃ）は（ｂ）のＡ部拡大図BRIEF DESCRIPTION OF THE DRAWINGS It is a figure explaining the manufacturing method of the semiconductor device of 1st Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the XX line of (a), ( c) Enlarged view of part A of (b) 従来の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）は（ａ）のＸ−Ｘ線で切断した要部断面図FIG. 2 is a configuration diagram of a conventional semiconductor device, where (a) is a plan view of the main part, and (b) is a cross-sectional view of the main part taken along line XX of (a). 従来の半導体装置でアルミワイヤに代わってリードフレーム２１を使用した場合の要部断面図Cross-sectional view of main parts when a lead frame 21 is used in place of aluminum wire in a conventional semiconductor device レーザ溶接した場合の不具合を説明する図であり、（ａ）は半導体装置の要部断面図、（ｂ）は同図（ａ）のＢ部拡大図It is a figure explaining the malfunction at the time of laser welding, (a) is principal part sectional drawing of a semiconductor device, (b) is the B section enlarged view of the same figure (a).

符号の説明Explanation of symbols

１ 銅ベース
２、６ はんだ
３ 裏面銅箔
４ セラミックス
５ コレクタ銅箔
７ ＩＧＢＴチップ
８ 表面電極（エミッタ電極）
９ ゲートパッド
１０ 樹脂ケース
１１ エミッタ端子（外部導出端子）
１２ ゲート端子
１５ アルミワイヤ
１６ 接着剤
２１、２４ リードフレーム（接続導体）
２２、２３、２４、２５ 溶融部（リードフレーム）
２７ 低融点金属層
２８ 溶融部（低融点金属層）
５０ 絶縁基板（回路パターン付き）
DESCRIPTION OF SYMBOLS 1 Copper base 2, 6 Solder 3 Back surface copper foil 4 Ceramics 5 Collector copper foil 7 IGBT chip 8 Surface electrode (emitter electrode)
9 Gate pad 10 Resin case 11 Emitter terminal (external lead-out terminal)
12 Gate terminal 15 Aluminum wire 16 Adhesive 21, 24 Lead frame (connection conductor)
22, 23, 24, 25 Melting zone (lead frame)
27 Low melting point metal layer 28 Melting zone (low melting point metal layer)
50 Insulating substrate (with circuit pattern)

Claims (8)

半導体チップの表面電極と、外囲器に固着した外部導出端子とを有し、該外部導出端子と前記表面電極とが接続導体で接続する半導体装置の製造方法において、前記表面電極と前記接続導体との固着がレーザ光で前記表面電極を直接溶融させずにレーザ溶接で行われることを特徴とする半導体装置の製造方法。 In a method of manufacturing a semiconductor device having a surface electrode of a semiconductor chip and an external lead terminal fixed to an envelope, and the external lead terminal and the surface electrode are connected by a connection conductor, the surface electrode and the connection conductor The semiconductor device is manufactured by laser welding without directly melting the surface electrode with laser light. 前記表面電極と前記接続導体が互いに対向する面の少なくとも一方の面に前記表面電極および前記接続導体の融点より低い低融点金属層が形成されることを特徴とする請求項１に記載の半導体装置の製造方法。 2. The semiconductor device according to claim 1, wherein a low melting point metal layer having a melting point lower than the melting point of the surface electrode and the connection conductor is formed on at least one surface of the surface electrode and the connection conductor facing each other. Manufacturing method. 前記低融点金属層の材質が錫または錫合金であることを特徴する請求項２に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 2, wherein a material of the low melting point metal layer is tin or a tin alloy. 前記低融点金属層の厚さが、１μｍ〜２０μｍであることを特徴とする請求項２または３に記載の半導体装置の製造方法。 4. The method of manufacturing a semiconductor device according to claim 2, wherein a thickness of the low melting point metal layer is 1 μm to 20 μm. 前記接続導体がリードフレームであることを特徴とする請求項１または２に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, wherein the connection conductor is a lead frame. 前記接続導体の材質が，銅または銅合金であることを特徴とする請求項１、２または５のいずれか一項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1, wherein a material of the connection conductor is copper or a copper alloy. 前記表面電極の材質がアルミニウムまたはシリコンを含有したアルミニウムであることを特徴とする請求項１または２に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1, wherein the material of the surface electrode is aluminum or aluminum containing silicon. 前記レーザ溶接に用いるレーザ光の波長範囲が、０．３３μｍ〜１０．６μｍであることを特徴とする請求項１に記載の半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein a wavelength range of laser light used for the laser welding is 0.33 [mu] m to 10.6 [mu] m.
JP2007276454A 2007-10-24 2007-10-24 Method of manufacturing semiconductor apparatus Withdrawn JP2009105266A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007276454A JP2009105266A (en) 2007-10-24 2007-10-24 Method of manufacturing semiconductor apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007276454A JP2009105266A (en) 2007-10-24 2007-10-24 Method of manufacturing semiconductor apparatus

Publications (1)

Publication Number Publication Date
JP2009105266A true JP2009105266A (en) 2009-05-14

Family

ID=40706660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007276454A Withdrawn JP2009105266A (en) 2007-10-24 2007-10-24 Method of manufacturing semiconductor apparatus

Country Status (1)

Country Link
JP (1) JP2009105266A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7939921B2 (en) * 2008-09-10 2011-05-10 Advanced Semiconductor Engineering, Inc. Leadframe
JP2012243890A (en) * 2011-05-18 2012-12-10 Denso Corp Semiconductor device, and method for manufacturing the same
WO2016132453A1 (en) * 2015-02-17 2016-08-25 株式会社日立製作所 Semiconductor device
WO2017208941A1 (en) * 2016-06-01 2017-12-07 三菱電機株式会社 Semiconductor device and method for manufacturing same
CN109249129A (en) * 2017-07-14 2019-01-22 赛米控电子股份有限公司 The method for manufacturing power electronic submodule by welding method
KR101982555B1 (en) * 2018-11-27 2019-05-27 제엠제코(주) Multiple Combination clip structure and Semiconductor package with clip structure
DE112018002384T5 (en) 2017-05-10 2020-01-16 Rohm Co., Ltd. Power semiconductor device and manufacturing process for the same
WO2020179369A1 (en) * 2019-03-05 2020-09-10 ローム株式会社 Semiconductor device and bonding method
WO2020255663A1 (en) * 2019-06-20 2020-12-24 ローム株式会社 Semiconductor device and production method for semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004311539A (en) * 2003-04-03 2004-11-04 Toshiba Corp Method of manufacturing semiconductor device
WO2005086218A1 (en) * 2004-03-02 2005-09-15 Fuji Electric Holdings Co., Ltd. Process for producing semiconductor module
JP2008177307A (en) * 2007-01-17 2008-07-31 Toyota Motor Corp Wiring joining method for semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004311539A (en) * 2003-04-03 2004-11-04 Toshiba Corp Method of manufacturing semiconductor device
WO2005086218A1 (en) * 2004-03-02 2005-09-15 Fuji Electric Holdings Co., Ltd. Process for producing semiconductor module
JP2008177307A (en) * 2007-01-17 2008-07-31 Toyota Motor Corp Wiring joining method for semiconductor device

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7939921B2 (en) * 2008-09-10 2011-05-10 Advanced Semiconductor Engineering, Inc. Leadframe
JP2012243890A (en) * 2011-05-18 2012-12-10 Denso Corp Semiconductor device, and method for manufacturing the same
WO2016132453A1 (en) * 2015-02-17 2016-08-25 株式会社日立製作所 Semiconductor device
WO2017208941A1 (en) * 2016-06-01 2017-12-07 三菱電機株式会社 Semiconductor device and method for manufacturing same
US11302665B2 (en) 2017-05-10 2022-04-12 Rohm Co., Ltd. Power semiconductor apparatus and fabrication method for the same
US11848295B2 (en) 2017-05-10 2023-12-19 Rohm Co., Ltd. Power semiconductor apparatus and fabrication method for the same
DE112018002384T5 (en) 2017-05-10 2020-01-16 Rohm Co., Ltd. Power semiconductor device and manufacturing process for the same
CN109249129A (en) * 2017-07-14 2019-01-22 赛米控电子股份有限公司 The method for manufacturing power electronic submodule by welding method
CN109249129B (en) * 2017-07-14 2022-09-27 赛米控电子股份有限公司 Method for producing power electronic modules by means of soldering
US10896889B2 (en) 2018-11-27 2021-01-19 Jmj Korea Co., Ltd. Multilayer clip structure attached to a chip
KR101982555B1 (en) * 2018-11-27 2019-05-27 제엠제코(주) Multiple Combination clip structure and Semiconductor package with clip structure
JPWO2020179369A1 (en) * 2019-03-05 2020-09-10
CN113491010A (en) * 2019-03-05 2021-10-08 罗姆股份有限公司 Semiconductor device and bonding method
WO2020179369A1 (en) * 2019-03-05 2020-09-10 ローム株式会社 Semiconductor device and bonding method
JP7368450B2 (en) 2019-03-05 2023-10-24 ローム株式会社 Semiconductor device and bonding method
CN113491010B (en) * 2019-03-05 2024-05-03 罗姆股份有限公司 Semiconductor device and bonding method
WO2020255663A1 (en) * 2019-06-20 2020-12-24 ローム株式会社 Semiconductor device and production method for semiconductor device
JP7451521B2 (en) 2019-06-20 2024-03-18 ローム株式会社 Semiconductor device and semiconductor device manufacturing method

Similar Documents

Publication Publication Date Title
JP2009105266A (en) Method of manufacturing semiconductor apparatus
JP6234630B2 (en) Power module
JP4976688B2 (en) Joining method between heat spreader and metal plate
JP5239291B2 (en) Semiconductor device and manufacturing method thereof
JP4775327B2 (en) Manufacturing method of semiconductor device
WO2017195625A1 (en) Semiconductor device and method for manufacturing semiconductor device
CN109698179B (en) Semiconductor device and method for manufacturing semiconductor device
WO2018181727A1 (en) Semiconductor device and manufacturing method therefor, and power conversion device
JP2008098586A (en) Semiconductor device
JP2020017562A (en) Semiconductor device, power converter, manufacturing method of semiconductor device, and manufacturing method of power converter
JP5737412B2 (en) Semiconductor device manufacturing method and semiconductor device manufactured using the manufacturing method
JP5119139B2 (en) Semiconductor device and manufacturing method of semiconductor device
JPWO2020105476A1 (en) Semiconductor device
JP5899952B2 (en) Semiconductor module
JP2004134623A (en) Semiconductor device
KR20200068285A (en) Dual side cooling power module and manufacturing method of the same
JP6381489B2 (en) Manufacturing method of semiconductor device
JP2019133965A (en) Semiconductor device and manufacturing method thereof
JP2015015335A (en) Semiconductor device
JP5840102B2 (en) Power semiconductor device
JP2020013866A (en) Manufacturing method for power semiconductor device
JP2007305620A (en) Manufacturing method of semiconductor device
JP5763467B2 (en) Electronic device manufacturing method and electronic device
JP2022125445A (en) Semiconductor device and method for manufacturing the same
WO2017208941A1 (en) Semiconductor device and method for manufacturing same

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20090219

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20091112

A625 Written request for application examination (by other person)

Free format text: JAPANESE INTERMEDIATE CODE: A625

Effective date: 20100812

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20110422

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20111227

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120207

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20120405