CN103107100A - Manufacturing method of power semiconductor device - Google Patents
Manufacturing method of power semiconductor device Download PDFInfo
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- CN103107100A CN103107100A CN2012104415137A CN201210441513A CN103107100A CN 103107100 A CN103107100 A CN 103107100A CN 2012104415137 A CN2012104415137 A CN 2012104415137A CN 201210441513 A CN201210441513 A CN 201210441513A CN 103107100 A CN103107100 A CN 103107100A
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- power semiconductor
- insulated substrate
- conductive pattern
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides the manufacturing method of a power semiconductor device, wherein the insulation property, the voltage resistance and the reliability of the power semiconductor device are improved. According to the technical scheme of the invention, the adhesiveness of silica gel (9) (served as protection materials) with an insulating substrate (1) printed with conductive patterns and a semiconductor chip (2) is improved by means of an oxygen plasma combining and surface treatment step (step 5) and silica gel pre-injecting and preheating step (step 6). In this way, the insulation property, the voltage resistance and the reliability of the power semiconductor device under a high-temperature environment can be improved.
Description
Technical field
The present invention relates to the manufacture method of power semiconductor, particularly enclose the manufacture method of the power semiconductor that silica gel etc. is arranged.
Background technology
In power semiconductor modular constant power semiconductor device; to be bonded on power semiconductor chip this conductive pattern on the conductive pattern of the insulated substrate of conductive pattern with by scolding tin etc. in order protecting to be disposed in resin-case, to fill sealing silica gel in resin-case.Utilize this silica gel to guarantee the insulation property (dielectric voltage withstand) that resin-case is interior
Figure 11 is the summary manufacturing procedure picture of existing power semiconductor.This process chart represents to inject silica gel summary operation before.The detailed description of this each operation is represented by following Figure 12～Figure 16.
Figure 12～Figure 16 represents the major part manufacturing process sectional view of the manufacture method of existing power semiconductor by process sequence.Here, power semiconductor refers to IGBT(Insulated Gate Bipolar Transistor), power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) etc. takes in power semiconductor modular of power semiconductor chip etc.
At first, in Figure 12 (operation 1), power semiconductor chip 2 is engaged on insulated substrate 1 with conductive pattern, power semiconductor chip 2 is connected with closing line (bonding wire) 3 with not shown conductive pattern with the insulated substrate 1 of conductive pattern.Insulated substrate 1 with conductive pattern is that the conductive pattern as the circuit layout pattern is engaged on the not shown insulated substrates such as pottery, backside conductive layer engaged with the back side and consist of.This conductive pattern is formed by Copper Foil etc. usually.
Then, in Figure 13 (operation 2), wait and to engage with heat dissipation base 4 with the not shown backside conductive layer of the insulated substrate 1 of conductive pattern by welding.
Then, in Figure 14 (operation 3), with bonding agent, the bottom of resin-case 5 is fixed in the side of heat dissipation base 4.Bonding agent is the bonding agent of epoxy resin, and as Sticking condition, temperature is 150 ℃ of left and right, and the processing time is about 3 minutes.
Then, in Figure 15 (operation 4), with closing line 3 grades, power semiconductor chip 2 and conductive pattern are connected with the outside leading-out terminal 6 that is fixed in resin-case 5.
Then, in Figure 16 (operation 5), to the interior injection silica gel 9 of resin-case 5.
In addition, disclose to be gathered under the state that (acyl) imines covers at least a portion of the outer surface of semiconductor element and lead-in wire in patent documentation 1 this semiconductor element and lead-in wire have been electrically connected to, then with the manufacture method of the above-mentioned semiconductor device with the lead semiconductor element of sealing resin sealing, with before lead semiconductor element resin-sealed, at least poly-(acyl) imines is partly carried out plasma treatment above-mentioned.
Process by this plasma, poly-(acyl) imines surface modification of joining with sealing resin improves with the amalgamation of resin.Therefore, according to the method, can access both moisture-proof adaptation on the boundary face of poly-(acyl) imines and sealing resin excellent and be difficult to produce the semiconductor device in packaging body crack in the reflow soldering operation.
In addition, record a kind of manufacture method of electronic unit in patent documentation 2, semiconductor element mounted thereon on substrate 31, the electrode that connects this semiconductor element and substrate by wire-bonded, in the manufacture method of such electronic unit, the joint encumbrance that heat treatment when the surface of the golden film that forms on the nickel film on copper electrode, the first plasma treatment by utilizing argon gas will be bonding by semiconductor element generates is removed, and improves wire-bonded.Then, by using the second plasma treatment of oxygen gas plasma, will reduce surface modification with the resist of the adaptation of resin mould by the first plasma treatment, thereby improve the adaptation with the resin mould of sealing resin.
The prior art document
Patent documentation
Patent documentation 1: Japanese kokai publication hei 5-152362 communique
Patent documentation 2: Japanese kokai publication hei 11-145120 communique
Summary of the invention
The problem that invention will solve
In the manufacture method of the prior art of the operation of the prior art of above-mentioned Figure 11 and Figure 12～Figure 16: (1) is as the anti-insulation characterisitic of power semiconductor, compare with normal temperature environment under hot environment (for example 150 ℃ of atmosphere), as shown in figure 17, insulation breakdown voltage (dielectric voltage withstand) reduces.(2) common, power semiconductor uses under the condition of high temperature because of the heating of power semiconductor chip 2, so the reduction of the dielectric voltage withstand under high temperature causes reliability to reduce.
Above-mentioned is because reducing with the insulated substrate 1 of conductive pattern and the adaptation of power semiconductor chip 2 and silica gel 9 phenomenon that causes.
In order to prevent this situation, implement the surface-treated method just like above-mentioned patent documentation 1,2 described such O2 plasmas that utilize.
But, plasma surface treatment shown in patent documentation 1,2, be inadequate for the power semiconductor modular constant power semiconductor device that uses under hot environment, may produce the reliability that the reduction by the reduction of insulation breakdown voltage and dielectric strength causes and reduce.
Figure 17 means the figure of the IGBT module temperature of prior art and the withstand voltage relation of insulation breakdown.Insulation breakdown voltage at normal temperatures is in the situation of 7.0kV～8.0kV, can be reduced to 5.0kV～6.0kV when the high temperature that reaches 150 ℃.
In addition, in above-mentioned patent documentation 1,2, IC is the semiconductor device as object, and the voltage that applies is all lower tens of V left and right.On the other hand, in power semiconductor up to the thousands of V of several 1000V(), compare with IC and easily cause insulation breakdown.
In addition, in above-mentioned patent documentation 1,2, implement plasma surface treatment to as if epoxy resin, and not with the record of silica gel as object.In addition, be not documented in plasma surface treatment after, prepare heating before with the protective material covering surfaces.
In power semiconductor, particularly in the situation that use larger resin-case 5, when using epoxy resin to replace silica gel, due to epoxy resin lack flexibility and thermal stress larger, so at resin-case, with insulated substrate generation crack or the division of conductive pattern, therefore can not use.
In addition, in above-mentioned patent documentation 2, put down in writing the resist and the adaptation of resin mould that improve substrate, but not about the record with the adaptation of the insulated substrate (ceramic substrate and circuit layout pattern) of conductive pattern and silica gel.
In addition, in above-mentioned patent documentation, damage and the foreign body intrusion put down in writing in order to prevent from causing because of external force improve adaptation, but there is no the record about the dielectric voltage withstand that improves semiconductor device as the present invention.
The objective of the invention is to solve above-mentioned problem, the manufacture method that can realize the power semiconductor of the raising of dielectric voltage withstand and reliability under hot environment is provided.
Be used for solving the method for problem
To achieve these goals, according to a first aspect of the invention, a kind of manufacture method of power semiconductor, this power semiconductor comprises: be bonded on the insulated substrate with conductive pattern on heat dissipation base; Be bonded on this with the semiconductor chip on the insulated substrate of conductive pattern; Take in above-mentioned insulated substrate with conductive pattern and above-mentioned semiconductor chip and be bonded in the resin-case of above-mentioned heat dissipation base; With the protective material that is filled in this resin-case, the manufacture method of above-mentioned power semiconductor is characterised in that, comprising: semiconductor chip is bonded on the operation on the insulated substrate of conductive pattern; Above-mentioned insulated substrate with conductive pattern is bonded on the operation of heat dissipation base; Resin-case is bonded in the operation of above-mentioned heat dissipation base; Oxygen plasma surface-treated operation is implemented on the surface of above-mentioned surface with the radiating pattern insulated substrate and above-mentioned semiconductor chip; To the above-mentioned operation of carrying out high-temperature heating and removing moisture with radiating pattern insulated substrate and above-mentioned semiconductor chip; With the operation that protective material is filled in resin-case.
In addition, according to a second aspect of the invention, in the manufacture method of the power semiconductor of a first aspect of the present invention, as above-mentioned oxygen plasma surface treatment condition, the power of plasma is 200W～600W, and plasma treatment time is 30 seconds～700 seconds, oxygen (O
2) flow be 30ml/ divide～100ml/ divides.
In addition, according to a third aspect of the invention we, in the manufacture method of the power semiconductor of a first aspect of the present invention, as the condition of above-mentioned high-temperature heating, temperature is more than 100 ℃ below 200 ℃, and be more than 30 minutes below 2 hours heating time.
In addition, according to a forth aspect of the invention, in the manufacture method of the power semiconductor of a first aspect of the present invention, above-mentioned protective material is silica gel or epoxy resin.
In addition, according to a fifth aspect of the invention, in the manufacture method of the power semiconductor of a first aspect of the present invention, the material that consists of the insulated substrate of above-mentioned insulated substrate with conductive pattern is Al
2O
3, Si
3N
4Or AlN, the material of conductive pattern is copper.
In addition, ion or active particle in the plasma that oxygen plasma surface treatment of the present invention refers to produce by oxidizing gas such as use oxygen clean or hydrophilicity-imparting treatment the surface of processing object.
The invention effect
In the present invention; by combination oxygen plasma surface treatment procedure and the preflood preparation heating process of silica gel; silica gel (protective material) and adaptation with insulated substrate and the semiconductor chip of conductive pattern be can improve, the dielectric voltage withstand of power semiconductor under hot environment and the raising of reliability realized.
Description of drawings
Fig. 1 is the manufacturing procedure picture of the power semiconductor of the first embodiment of the present invention.
Fig. 2 is the major part manufacturing process sectional view of the power semiconductor of the first embodiment of the present invention.
Fig. 3 is the major part manufacturing process sectional view of the power semiconductor of the then first embodiment of the present invention of Fig. 2.
Fig. 4 is the major part manufacturing process sectional view of the power semiconductor of the then first embodiment of the present invention of Fig. 3.
Fig. 5 is the major part manufacturing process sectional view of the power semiconductor of the then first embodiment of the present invention of Fig. 4.
Fig. 6 is the major part manufacturing process sectional view of the power semiconductor of the then first embodiment of the present invention of Fig. 5.
Fig. 7 is the major part manufacturing process sectional view of the power semiconductor of the then first embodiment of the present invention of Fig. 6.
Fig. 8 is the major part manufacturing process sectional view of the power semiconductor of the then first embodiment of the present invention of Fig. 7.
Fig. 9 means the figure of the relation of oxygen plasma treatment condition and dielectric voltage withstand.
The figure of the relation that the IGBT module temperature when Figure 10 means application manufacture method of the present invention and insulation breakdown are withstand voltage.
Figure 11 is the manufacturing procedure picture of summary of the power semiconductor of prior art.
Figure 12 is the major part manufacturing process sectional view of the power semiconductor of prior art.
Figure 13 is the major part manufacturing process sectional view of the power semiconductor of the then prior art of Figure 12.
Figure 14 is the major part manufacturing process sectional view of the power semiconductor of the then prior art of Figure 13.
Figure 15 is the major part manufacturing process sectional view of the power semiconductor of the then prior art of Figure 14.
Figure 16 is the major part manufacturing process sectional view of the power semiconductor of the then prior art of Figure 15.
Figure 17 means the figure of the IGBT module temperature of prior art and the withstand voltage relation of insulation breakdown.
Figure 18 means the figure of the proper range of oxygen plasma surface treatment condition.
Description of reference numerals
1 insulated substrate with conductive pattern
2 power semiconductor chips
3 closing lines
4 heat dissipation bases
5 resin-cases
6 outside leading-out terminals
7 electrodes
8 thermostats
9 silica gel
10 oxygen
Embodiment
With following embodiment, execution mode is described.To mark identical Reference numeral in position same as the prior art.
(embodiment 1)
Fig. 1 is the manufacturing procedure picture of the power semiconductor of the first embodiment of the present invention.Before this process chart represents to inject silica gel.The detailed description of this each operation is represented by following Fig. 2～Fig. 8.
Fig. 2～Fig. 8 represents the major part manufacturing process sectional view of manufacture method of the power semiconductor of the first embodiment of the present invention by process sequence.In addition, here, power semiconductor refers to that IGBT, power MOSFET etc. take in the power semiconductor modular of power semiconductor chip etc.
At first, in Fig. 2 (operation 1), power semiconductor chip 2 is engaged on insulated substrate 1 with conductive pattern, with closing line 3 bonding conductors such as grade, power semiconductor chip 2 is connected with not shown conductive pattern with the insulated substrate 1 of conductive pattern.Although not shown, be the conductive pattern as the circuit layout pattern to be engaged in pottery wait on insulated substrate, backside conductive layer is bonded on the back side forms with the insulated substrate 1 of conductive pattern.This conductive pattern is formed by Copper Foil etc. usually.
Then, in Fig. 3 (operation 2), will be bonded on heat dissipation base 4 with the not shown backside conductive layer of the insulated substrate 1 of conductive pattern by not shown scolding tin etc.
Then, in Fig. 4 (operation 3), with bonding agent, the bottom of resin-case 5 is fixed in the side of heat dissipation base 4.Bonding agent is the bonding agent of epoxy resin, and as Sticking condition, treatment temperature is 150 ℃ of left and right, and the processing time is about 3 minutes.
Then, in Fig. 5 (operation 4), with closing line 3 bonding conductors such as grade, power semiconductor chip 2 and conductive pattern are connected to the outside leading-out terminal 6 that is fixed in resin-case 5.
Then, in Fig. 6 (operation 5), in plasma processing apparatus 50, to carrying out the oxygen plasma surface treatment with the surface of the insulated substrate 1 of conductive pattern and the surface of power semiconductor chip 2.As mentioned above, be Copper Foil with the conductive pattern of the insulated substrate 1 of conductive pattern, the material of insulated substrate is Al
2O
3, Si
3N
4, the pottery such as AlN.
Then, in Fig. 7 (operation 6), prepared heating before injecting silica gel 9, the condition of this preparation heating is: heating-up temperature is 150 ℃ of left and right, and be about 1 hour heating time.This preparation heating uses thermostat 8, hot plate to carry out.
Then, in Fig. 8 (operation 7), to the interior injection silica gel 9 of resin-case 5.
In above-mentioned Fig. 6 (operation 5), be arranged on the size of the electrode 7 of parallel plate-type in plasma processing apparatus 50, that produce oxygen plasma, for example vertical for L() * W(is horizontal)=approximately about 250mm * 150mm.Interelectrode distance D is for example about 50mm～100mm.The frequency of oscillation f of plasma generation is 13.56MHz.In addition, be imported into the interior oxygen (O of plasma processing apparatus
2) 10 flow Q preferably 50ml/ divide the left and right.This flow Q can be below the above 100ml of 30ml.When flow Q surpassed 100ml, the membranous of plasma oxide film went bad, and caused dielectric voltage withstand to reduce.On the other hand, during less than 30ml, plasma oxide film is excessively thin, causes adaptation reduction, dielectric voltage withstand to reduce.As the oxidizing gas that plasma treatment is used, also can use nitrous oxide (N beyond deoxygenation
2O) etc.
In addition, in above-mentioned Fig. 6 (operation 5), the experimental result about oxygen plasma treatment condition and dielectric voltage withstand is described.
Fig. 9 means the figure of the relation of oxygen plasma treatment condition and dielectric voltage withstand.In figure, zero expression dielectric voltage withstand improves, and △ represents that dielectric voltage withstand is unchanged, and * expression dielectric voltage withstand reduces.
As oxygen plasma surface treatment condition, the power P of plasma is 200W～600W, and plasma treatment time t is 30 seconds～700 seconds.When the power P of plasma, plasma treatment time t surpassed this scope, heat oxide film was grown up, and is membranous rotten from plasma oxide film.Therefore, adaptation reduces, and dielectric strength reduces.On the other hand, in the little situation of this scope, the thickness attenuation of plasma oxide film, same adaptation reduces, and dielectric strength reduces.In addition, from improving the viewpoint of dielectric voltage withstand, more preferably the power P of plasma is 250W～600W, and plasma treatment time t is the scope of 30 seconds～600 seconds.
In addition, as can be seen from Figure 9, in preferred oxygen plasma surface treatment condition, there is the relation of inverse ratio in the relation of the power P of plasma and plasma treatment time t.Figure 18 represents this relation, and oblique line partly represents the scope of preferred condition.Therefore, in the scope of Fig. 9, Figure 18, when increasing the power P of plasma, plasma treatment time t reduces, and can improve dielectric strength.In addition, although the reason that dielectric strength improves is indefinite, at the thickness of above-mentioned condition applying plasma oxide-film for number nm when above, the adaptation raising of silica gel 9.
In the present embodiment, after the oxygen plasma surface treatment of carrying out above-mentioned operation 5, the preparation heating by above-mentioned operation 6 with the dry tack free with insulated substrate 1 and the power semiconductor chip 2 of conductive pattern of the other side's one side of silica gel 9 driving fits, is removed moisture.Therefore, compare with the situation of not preparing heating, can improve silica gel 9 and adaptation with insulated substrate 1 and the power semiconductor chip 2 of conductive pattern.
In above-mentioned Fig. 7 (operation 6), as the preparation heating condition, heating-up temperature is more than 100 ℃ below 200 ℃, and be to get final product below 2 hours more than 30 minutes heating time.If leave this scope, can produce oxidation or dehumidify the bad problem such as insufficient.
As mentioned above, by the preparation heating process before combination oxygen plasma surface treatment procedure and injection silica gel, can improve silica gel 9 and with the adaptation between the insulated substrate 1 of conductive pattern, improve the adaptation between silica gel 9 and power semiconductor chip 1.
By improving adaptation, can prevent that the dielectric voltage withstand of the power semiconductor of (for example 150 ℃ of left and right) under hot environment from reducing, improve the reliability of power semiconductor.
The figure of the relation that the IGBT module temperature when Figure 10 means application manufacture method of the present invention and insulation breakdown are withstand voltage.
Insulation breakdown voltage under normal temperature is in the situation of 7.0kV～8.0kV left and right, is the insulation breakdown voltage of 7.0kV～9.5kV left and right when the high temperature that reaches 150 ℃.Adopt the insulation breakdown voltage at high temperature of existing manufacture method to compare with the insulation breakdown voltage under high temperature of the present invention, the IGBT module insulation breakdown voltage at high temperature of using manufacture method of the present invention increases really.
Namely; in the present embodiment; in the manufacture method of semiconductor device; by combination oxygen plasma surface treatment procedure and the preflood preparation heating process of silica gel; can improve silica gel (protective material) and adaptation with insulated substrate and the semiconductor chip of conductive pattern, therefore can improve the dielectric voltage withstand of power semiconductor.
In addition, be illustrated above-mentioned operation 6 just being inserted into above-mentioned operation 7 situation before.This is due to before just being inserted into above-mentioned operation 7 time, shortens the standing time till the above-mentioned operation 7 and preferred.But, before just being inserted into above-mentioned operation 7, even insert the operation that becomes between above-mentioned operation 2 and above-mentioned operation 7, can find that also dielectric voltage withstand improves.
As the protective material of the insulation property of guaranteeing this power semiconductor, silica gel 9 is illustrated, but so long as the high protective material of insulating properties and elastic force is not limited to this.In addition, in the situation that the resin-case of power semiconductor is smaller, there is the situation of using epoxy resin.
Particularly, in the power semiconductor of being made by SiC, GaN, resin-case 5 big or small smaller is perhaps for the high temperature action, as protective material use epoxy resin.In this case, use manufacture method of the present invention also can access same effect.
Claims (5)
1. the manufacture method of a power semiconductor, this power semiconductor comprises: be bonded on the insulated substrate with conductive pattern on heat dissipation base; Be bonded on described with the semiconductor chip on the insulated substrate of conductive pattern; Take in described insulated substrate with conductive pattern and described semiconductor chip and be bonded in the resin-case of described heat dissipation base; With the protective material that is filled in described resin-case, the manufacture method of described power semiconductor is characterised in that, comprising:
Semiconductor chip is bonded on the operation on the insulated substrate of conductive pattern;
Described insulated substrate with conductive pattern is bonded on the operation of heat dissipation base;
Resin-case is bonded in the operation of described heat dissipation base;
Oxygen plasma surface-treated operation is implemented on the surface of described surface with the radiating pattern insulated substrate and described semiconductor chip;
To the described operation of carrying out high-temperature heating and removing moisture with radiating pattern insulated substrate and described semiconductor chip; With
Protective material is filled into operation in resin-case.
2. the manufacture method of power semiconductor as claimed in claim 1 is characterized in that:
As described oxygen plasma surface-treated condition, the power of plasma is 200W～600W, and plasma treatment time is 30 seconds～700 seconds, oxygen (O
2) flow be 30ml/ divide～100ml/ divides.
3. the manufacture method of power semiconductor as claimed in claim 1 is characterized in that:
As the condition of described high-temperature heating, temperature is more than 100 ℃ below 200 ℃, and be more than 30 minutes below 2 hours heating time.
4. the manufacture method of power semiconductor as claimed in claim 1 is characterized in that:
Described protective material is silica gel or epoxy resin.
5. the manufacture method of power semiconductor as claimed in claim 1 is characterized in that:
The material that consists of the insulated substrate of described insulated substrate with conductive pattern is Al
2O
3, Si
3N
4Or AlN, the material of conductive pattern is copper.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011-246265 | 2011-11-10 | ||
| JP2011246265A JP5987297B2 (en) | 2011-11-10 | 2011-11-10 | Method for manufacturing power semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103107100A true CN103107100A (en) | 2013-05-15 |
| CN103107100B CN103107100B (en) | 2015-11-18 |
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ID=48314861
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|---|---|---|---|
| CN201210441513.7A Active CN103107100B (en) | 2011-11-10 | 2012-11-07 | The manufacture method of power semiconductor |
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|---|---|
| JP (1) | JP5987297B2 (en) |
| CN (1) | CN103107100B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110447098A (en) * | 2017-03-29 | 2019-11-12 | 三菱电机株式会社 | Power semiconductor modular |
| CN111033736A (en) * | 2017-09-05 | 2020-04-17 | 三菱电机株式会社 | Power module, method for manufacturing same, and power conversion device |
| CN111162057A (en) * | 2020-01-06 | 2020-05-15 | 珠海格力电器股份有限公司 | Semiconductor power device and power processing assembly for semiconductor power device |
| CN111681993A (en) * | 2019-03-11 | 2020-09-18 | 富士电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05152362A (en) * | 1991-11-30 | 1993-06-18 | Nitto Denko Corp | Manufacture of semiconductor device |
| JPH11145120A (en) * | 1997-11-12 | 1999-05-28 | Matsushita Electric Ind Co Ltd | Plasma treating device for electronic parts and manufacture of electronic parts |
| CN1287385A (en) * | 1999-09-08 | 2001-03-14 | 广州市高科通信设备有限公司 | Technological process of lowering the junction temperature of semiconductor power device |
| CN1604321A (en) * | 2003-09-30 | 2005-04-06 | 三洋电机株式会社 | Semiconductor device containing stacked semiconductor chips and manufacturing method thereof |
| CN1774801A (en) * | 2003-04-02 | 2006-05-17 | Abb研究有限公司 | Insulated power semiconductor module with reduced partial discharge and manufacturing method |
| CN101752210A (en) * | 2008-12-19 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | Reduce the residual charge method of plasma etching industrial |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000228413A (en) * | 1999-02-05 | 2000-08-15 | Seiko Epson Corp | Manufacture of semiconductor package |
| JP4381630B2 (en) * | 2001-06-06 | 2009-12-09 | 株式会社日立製作所 | Resin-sealed module device for automobile control |
| JP3988735B2 (en) * | 2004-03-15 | 2007-10-10 | 日立金属株式会社 | Semiconductor device and manufacturing method thereof |
| JP2009252869A (en) * | 2008-04-03 | 2009-10-29 | Nec Electronics Corp | Method of manufacturing semiconductor device, and semiconductor device manufactured by the method |
-
2011
- 2011-11-10 JP JP2011246265A patent/JP5987297B2/en active Active
-
2012
- 2012-11-07 CN CN201210441513.7A patent/CN103107100B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05152362A (en) * | 1991-11-30 | 1993-06-18 | Nitto Denko Corp | Manufacture of semiconductor device |
| JPH11145120A (en) * | 1997-11-12 | 1999-05-28 | Matsushita Electric Ind Co Ltd | Plasma treating device for electronic parts and manufacture of electronic parts |
| CN1287385A (en) * | 1999-09-08 | 2001-03-14 | 广州市高科通信设备有限公司 | Technological process of lowering the junction temperature of semiconductor power device |
| CN1774801A (en) * | 2003-04-02 | 2006-05-17 | Abb研究有限公司 | Insulated power semiconductor module with reduced partial discharge and manufacturing method |
| CN1604321A (en) * | 2003-09-30 | 2005-04-06 | 三洋电机株式会社 | Semiconductor device containing stacked semiconductor chips and manufacturing method thereof |
| CN101752210A (en) * | 2008-12-19 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | Reduce the residual charge method of plasma etching industrial |
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| CN110447098A (en) * | 2017-03-29 | 2019-11-12 | 三菱电机株式会社 | Power semiconductor modular |
| CN110447098B (en) * | 2017-03-29 | 2022-11-25 | 三菱电机株式会社 | Power semiconductor module |
| CN111033736A (en) * | 2017-09-05 | 2020-04-17 | 三菱电机株式会社 | Power module, method for manufacturing same, and power conversion device |
| CN111681993A (en) * | 2019-03-11 | 2020-09-18 | 富士电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2013105761A (en) | 2013-05-30 |
| JP5987297B2 (en) | 2016-09-07 |
| CN103107100B (en) | 2015-11-18 |
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