JP2000340719A - Power semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a level of insulating withstand voltage by coating a boundary of a conductive part on a creepage surface of an insulating substrate between a conductive pattern end and a base plate with an amorphous inorganic glass material, which is larger in breakdown voltage than an insulation-resistant gelling agent and has high resistance against discharged withstand voltage. SOLUTION: A boundary of the end of a conductive pattern 3b is coated on the creepage surface of an insulating substrate, such as aluminum nitride 3a. The conductive patterns 3b, such as Cu foil, are brazed with Ag on both surfaces of the insulating substrate. For instance, a discharging method such as a mask printing method is used. Coating is made with crystalline inorganic glass 4a such as a Bi2O3-B2O3 material, which is higher in breakdown voltage than an insulation-resistant gelling agent 5a by 10 kV or higher, has high resistance against discharged withstand voltage, and has a thermal expansion coefficient of 3.2 to 12.5×10-6/ deg.C. Afterwards, a heating operation is performed in the air or in N2 gas, and fusion bonding is carried out at a sealing temperature of 410 to 750 deg.C. A case structure 6, which is made of a polyphenylene sulfide insulating resin material, is bonded and sealed into the peripheral part of a base plate 1 with an adhesive 7 made of silicon resin, to complete a module.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an internal withstand voltage structure in a power semiconductor device.

[0002]

2. Description of the Related Art A conventional device is a semiconductor device having a structure disclosed in Japanese Patent Application Laid-Open No. H08-125071 (schematic explanatory diagram; shown in FIG. 8A).
Then, a ceramic plate 3a having a copper plate and a copper circuit 3b formed thereon is soldered to the container bottom plate 1, an external lead-out terminal 9 is taken out from the copper circuit, a container outer wall 6 is provided outside the container bottom plate 1, and a peripheral edge of the circuit board is provided. After the portion is covered with a silicone rubber adhesive 10a having a strong adhesive force to the substrate and the container bottom plate, a potting agent (gel-like silicone rubber) 5a is injected, and an epoxy resin 13 is further filled. The main purpose of this structure is to prevent the potting material 5a from peeling off from the circuit board and reducing the withstand voltage performance.

[0003]

The following problems occur in the conventional structure.

First, since the potting material 5a is completely sealed with the epoxy resin 13, when the potting material 5a expands and contracts during operation of the apparatus, the silicone rubber adhesive 10a is generated due to the internal stress 14 generated. Defects (16 in FIG. 8B) are likely to occur at the interface with. Such peeling defects lead to dielectric breakdown. Second, in this conventional structure, the silicone rubber adhesive 10a covering the peripheral portion of the circuit board expands and contracts (FIG. 8).
Since the peripheral portion of the circuit board is raised or lowered according to 15) A), the peripheral portion of the circuit board (the ceramic substrate 3a) may be brittlely broken (3c in FIG. 8B). As a result, there is a concern that the peripheral edge distance serving to provide the withstand voltage is reduced, and the withstand voltage performance is reduced.

Third, unlike the use conditions of semiconductor devices up to now, a high withstand voltage (withstand voltage: 9 kVrms or more) structure with a higher additional voltage has been required in recent years.
The dielectric strength withstand voltage of the conventional structure (FIG. 7A) is based on the withstand voltage characteristics of the circuit board, the distance between the copper circuit end formed on the upper surface of the circuit board and the container bottom plate, the potting material filled inside and the peripheral portion of the circuit board. It is considered that it is left to the insulating properties of the silicone rubber adhesive coated with the resin. However, in the case of a semiconductor device with a higher voltage, A
7g, a partial discharge occurs due to electric field concentration at the brazing portion (3d in FIGS. 7A and 7B), and 18a in FIG. 7A and 18a in FIG.
As shown in the model diagram of FIG. 18b, a partial discharge that breaks the bonding strength of the insulating resin progresses, and often causes dielectric breakdown.

An object of the present invention is to improve the withstand voltage and withstand voltage of the internal structure of a power semiconductor device.

[0007]

In the power semiconductor device according to the present invention, the boundary region between the end of the conductive pattern and the conductive portion on the surface of the insulating substrate between the base plate has a higher breakdown voltage than the insulating gel. Highly inorganic material having high partial discharge resistance, for example, an amorphous inorganic glass having a coefficient of thermal expansion of 7.5 to 9.0 × 10 −6 / ° C., a sealing temperature of 500 to 600 ° C., and a withstand voltage of 10 kVrms or more. (Bi ₂ O ₃ -B ₂ O ₃ ) material.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.
This will be described with reference to FIG. 7B.

FIG. 1 is a partially enlarged sectional view for explaining a power semiconductor device according to one embodiment of the present invention, and FIG. 2 is a plan view thereof.

As shown in FIGS. 1 and 2, a conductive pattern 3b (for example, Cu foil) is brazed between the front and back with Ag (for example, Cu-Ag containing Ti at a melting temperature of 800 to 850 ° C.).
The boundary between the surface of the insulating substrate (e.g., aluminum nitride: AlN) 3a on which eutectic Ag brazing is performed and the end of the conductive pattern 3b is formed using, for example, a mask printing method or a discharge method such as a dispenser. Inorganic glass 4a having a higher dielectric breakdown voltage (10 kV or more) than the gel agent 5a and having a high partial discharge resistance (having a strong bonding force in the material) as shown in Table 1
(E.g. _{A: Bi 2 O 3 -B 2} O 3 system) coated with material was then heated in air or in N ₂ gas (700 ° C.) was fused.

[0011]

[Table 1]

Then, a semiconductor chip 19a is formed on the conductive pattern 3b with a high melting point solder material (for example, Pb-5 wt% Sn-
1.5 wt% Ag: melting point: 296-305 ° C)
Bonding wiring is performed with the Al wire 20a. Next, these ALN insulating substrates are used as base plates (molybdenum: Mo or Al-SiC composite material or CuCuO ₂ sintered material).
Solder No. 1 (for example, Sn-40 wt% Pb: melting point 183 or more)
(191 ° C.) 2 Both are joined by heating in H ₂ gas. Then, a case structure 6 made of a PPS (polyphenylene sulfide) insulating resin material is bonded to the outer peripheral portion of the base plate 1 with an adhesive 7 made of a silicone resin. Further, after the upper layer is filled with the insulating gel agent 5a and cured, the upper part is sealed to complete the module.

In the present invention, the boundary region between the end of the conductive pattern 3b and the conductive portion on the surface of the ALN insulating substrate 3a between the base plate 1 is formed by using a crystalline inorganic glass (Bi ₂ O ₃ -B ₂ O ₃ system). )
By having a structure covered with a material, the insulating gel agent 5
Since the dielectric breakdown voltage is higher than that of a and the progress of the breakdown due to the partial discharge can be suppressed, the withstand voltage between the end of the conductive pattern 3b and the base plate 1 is greatly improved.

The insulating substrate 3a soldered 2 on the base plate 1 is a substrate made of ceramics or the like, and the structure bonded and arranged on the entire outer peripheral surface of the insulating substrate 3a is By using the same insulating resin or the same ceramic material as the insulating substrate, the intended withstand voltage resistance can be reliably ensured.

Further, the base material 1 to which the insulating substrate 3a on which the conductive pattern 3b is formed is soldered 2 is made of a material having a coefficient of linear expansion of three times or less that of silicone (Si). In operation, the difference in the coefficient of linear expansion between the insulating substrate 3a and the base material 1 can be reduced, so that the thermal strain on the solder 2 can be reduced. Thus, a highly reliable semiconductor device can be obtained.

For the reasons described above, the base material is preferably a metal material or a composite material such as molybdenum (Mo) or an Al—SiC composite material or a CuCuO ₂ sintered material. By these effects, a structure excellent in high withstand voltage and withstand voltage can be obtained, and a low-cost and highly reliable power semiconductor device can be obtained.

FIG. 3 is an enlarged sectional view of another embodiment of the present invention.

A non-metallic material shown in Table 2 is applied to the end of the conductive pattern 3b on the surface of the ALN insulating substrate 3a on which the conductive pattern 3b is Ag-brazed between the front and back sides by using, for example, a mask printing method or a discharge method such as a dispenser. , For example, Au-Sn2
A paste of a eutectic brazing material (melting temperature: 280 ° C.) consisting of the original system is coated and heated (320 ° C.) to be fused, and the joint end is formed into a spherical shape having a radius of curvature of 0.15 mm or more. I did it.

[0019]

[Table 2]

The main point of making the joint end portion into a spherical shape having a radius of curvature of 0.15 mm or more is that the ALN insulating substrate 3a
The eutectic brazing material composed of the Au-Sn binary system does not directly wet the bulk surface. Therefore, it is spheroidized by the surface tension specific to the molten metal. The brazing material wets only at the end of the conductive pattern 3b and the joined Ag brazing portion. Therefore, by adjusting the supply amount of the paste material of the eutectic brazing material by a discharge printing method such as a screen printing method or a dispenser, the joining end portion can be formed into a spherical shape having a radius of curvature of 0.15 mm or more.

In the conventional structure, when the conductive pattern 3b is formed on the ALN substrate, it is joined by a Cu-Ag eutectic Ag solder containing Ti, but since the end portion of the joined Ag solder has an acute angle shape. The electric field strength concentrates on that part,
The structure was such that partial discharge easily occurred.

By adopting the structure of the present invention, the concentration of the electric field at the end portions is reduced, the generation of partial discharge and the progress of growth are suppressed, and the same high dielectric strength voltage as described above was obtained.

FIGS. 4A, 4B and 4C are enlarged sectional views of another embodiment of the present invention.

FIG. 4A shows a crystalline inorganic glass material (Bi ₂ O ₃ -B ₂
O ₃ ), and the other areas were coated with a silicone-based high insulation voltage-resistant resin agent 4 having excellent voltage resistance shown in Table 1D.
FIG. 4B shows a dielectric breakdown voltage shown in D of Table 1 on the surface of the insulating substrate covered with the inorganic material, and on the surface of the insulating substrate including the region. FIG. 4C includes a conductive portion boundary region on the surface of an insulating substrate coated with the inorganic material, and a portion between the base on the conductive portion insulating substrate and the base. The region has a structure in which the region is covered with the silicone-based high-breakdown-voltage resin agent described above.

With the structure of FIG. 4A of the present invention, ALN
Since the structure is such that the progress of destruction due to partial discharge on the surface of the insulating substrate 3a can be suppressed in two steps, the withstand voltage resistance can be further improved. Further, by adopting the structure of FIG. 4B of the present invention,
In addition to extending the creepage distance of the insulating substrate to improve the withstand voltage, the covering portion with the inorganic material can be protected and the destruction progress due to partial discharge on the ALN insulating substrate 3a can be suppressed by a double structure. Therefore, the withstand voltage resistance can be further improved. In addition, with the structure of FIG. 4C of the present invention, a high withstand voltage withstand voltage up to the inter-base side was obtained.

In the three structures according to the present invention, the concentration of the electric field at the end is alleviated by the inorganic material of the first layer, and furthermore, the withstand voltage around the periphery is ensured. As a result, the same high dielectric strength voltage as described above was obtained.

Further, since the high insulation withstand voltage resin agent 4 used in the present invention is made of a silicone resin or a polyamide resin having good adhesion to the surface of the ALN insulating substrate,
The structure can be obtained easily and at a low cost in terms of the assembling process. FIG. 5 is an enlarged sectional view of another embodiment of the present invention.

FIG. 5 shows that the boundary region between the conductive portion on the surface of the insulating substrate 3a and the conductive glass is coated with the above-mentioned inorganic glass material, and then the PPS (polyphenylene sulfide) resin is applied to the outer peripheral portion of the surface of the insulating substrate other than the boundary region. This is a structure in which an insulating resin structure 12 made of a material or a ceramic material is bonded with a silicone-based high withstand voltage resin material 4b.

By employing the structure of the present invention, the creepage distance of the insulating substrate can be extended to twice or more, and a higher dielectric strength voltage higher than the breakdown voltage of the conventional structure can be obtained.

FIG. 6 is an explanatory diagram showing the withstand voltage withstand voltage according to the present invention in terms of the dielectric breakdown voltage and comparing it with that of the conventional structure.

FIG. 3 shows the results showing the breakdown voltage of the representative structure according to the present invention. A structure in which the boundary area between the conductive pattern edge and the conductive part on the surface of the ALN insulating substrate between the base plate and the conductive part is covered with a crystalline inorganic glass material or a non-ferrous metal material.
By alleviating the electric field concentration, it is possible to suppress the progress of destruction of the insulating gel agent due to partial discharge, and by adopting a structure in which the above-mentioned structures of the present invention are bonded so as to be covered with a silicone-based high withstand voltage resin, A high internal withstand voltage withstand voltage structure with several levels of dielectric breakdown voltage higher than that of the conventional structure filled with insulating gel was successfully established.

[0032]

According to the present invention, a high breakdown voltage (for example, about 16 kVrms) can be secured in a power semiconductor device having an insulating substrate mounted thereon.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view of a power semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing the entire AlN insulating substrate of the present invention (FIG. 1).

FIG. 3 is a partial cross-sectional view of a power semiconductor device according to a second embodiment of the present invention.

FIGS. 4A, 4B and 4C are partial cross-sectional views of power semiconductor devices according to third, fourth and fifth embodiments of the present invention.

FIG. 5 is a partial sectional view of a power semiconductor device according to a sixth embodiment of the present invention.

FIG. 6 shows an example of a relationship between a creepage distance of an insulating substrate and a dielectric breakdown voltage according to the embodiment of the present invention.

FIG. 7A is a sectional structural model diagram showing a destruction phenomenon in a conventional power semiconductor device.

FIG. 7B is a plan model diagram showing a breakdown phenomenon in a conventional power semiconductor device.

FIG. 8 is a view showing a separation defect in a second example of the conventional power semiconductor device.

FIG. 9 is a cross-sectional structural model diagram showing a breakdown phenomenon in a conventional power semiconductor device.

FIG. 10 is a cross-sectional structural model diagram showing a breakdown phenomenon in a conventional power semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Base plate, 2 ... Solder, 3a ... Insulating board, 3b ... Conductive pattern, 3c ... Insulating board edge part, 3d ... Ag brazing part, 4
a: inorganic glass material, 4b: high insulation withstand voltage resin (silicone) agent, 4c: non-ferrous metal material, 5a: insulating gel (silicone) agent, 6: case structure (PPS resin), 7
... case adhesive, 8 ... terminal block, 9 ... external lead-out terminal, 10a ... silicone rubber adhesive, 12 ... insulating resin structure, 13 ... hard epoxy resin, 14 ... internal stress arrow diagram, 15 ... expansion and contraction arrow diagram , 16: peeling defect, 17: partial discharge portion, 18a: destruction trace, 19a: semiconductor chip, 2
0a: Al wire, 21: high voltage circuit, 22: high voltage AC meter.

Continued on the front page (72) Inventor Ryuichi Saito 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Kazuhiro Suzuki 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd.Hitachi Research Laboratories (72) Inventor Yoshihiko Koike 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. No. 1-1 F-term in Hitachi Research Laboratory, Hitachi, Ltd. F-term (reference) 4M109 AA02 AA03 BA03 CA02 DB02 DB09 DB10 DB16 EC07 ED04 GA02

Claims (6)

[Claims] 1. A structure in which a case structure made of an insulating resin is arranged on an outer peripheral portion of a base material on which at least one insulating substrate on which a conductive pattern is formed is mounted, and the entire inner region is filled with an insulating gel agent. In the power semiconductor device of (1), the boundary area between the end of the conductive pattern and the conductive portion on the surface of the insulating substrate between the base plate is defined by a coefficient of thermal expansion of 3.2 to 12.5 × 10 ⁻⁶ / ° C. and a sealing temperature of 410 to 410. A power semiconductor device characterized by being coated with a crystalline and non-crystalline inorganic glass material having 750 ° C. and a withstand voltage of 10 kVrms or more. 2. The method according to claim 1, wherein a boundary region between an end of the conductive pattern of the insulating substrate on which the conductive pattern is formed and a conductive portion on the surface of the insulating substrate between the base plate is formed by melting at a temperature of 200 to 500 ° C. Fused with a non-ferrous metal material
A power semiconductor device having a structure in which a shape having a radius of curvature of 0.15 mm or more is formed, and an electric field intensity at an end portion is reduced to reduce a partial discharge. 3. A high withstand voltage with high adhesion to the surface of the insulating substrate other than the conductive region boundary region on the surface of the insulating substrate coated with an inorganic material and having a higher dielectric breakdown voltage than an insulating gel agent. A power semiconductor device characterized by being coated with an organic resin agent. 4. A surface of a conductive part insulating substrate including a conductive part boundary region on a surface of the insulating substrate coated with an inorganic material is coated with a high dielectric strength resin having a higher dielectric breakdown voltage than an insulating gel. A power semiconductor device, comprising: 5. A high withstand voltage resin including a conductive portion boundary region on an insulating substrate surface covered with an inorganic material, and having a higher dielectric breakdown voltage than the insulating gel agent between the conductive portion insulating substrate surface and the base. A power semiconductor device characterized by being coated with an agent. 6. An insulating resin structure is adhered to a conductive portion of an insulating substrate coated with an inorganic material and an outer peripheral surface of the insulating substrate other than a boundary region thereof with a high-breakdown-voltage resin material. A power semiconductor device characterized by extending the length.