JP2014150203A - Power module and manufacturing method of the same - Google Patents

Power module and manufacturing method of the same Download PDF

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JP2014150203A
JP2014150203A JP2013019074A JP2013019074A JP2014150203A JP 2014150203 A JP2014150203 A JP 2014150203A JP 2013019074 A JP2013019074 A JP 2013019074A JP 2013019074 A JP2013019074 A JP 2013019074A JP 2014150203 A JP2014150203 A JP 2014150203A
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semiconductor element
sealing resin
resin
inner frame
power module
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Kazuhiro Tada
和弘 多田
Noriyuki Betsushiba
範之 別芝
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
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    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/1304—Transistor
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    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a power module which is operated at high temperature and achieves high reliability.SOLUTION: A power module includes: a semiconductor element substrate; a semiconductor element fastened to the semiconductor element substrate; an inner frame provided at a peripheral part of the semiconductor element substrate; a first sealing resin which seals the interior of the inner frame; a heat radiation plate which is joined to a rear surface of the semiconductor element substrate; an outer frame provided at a peripheral part of the heat radiation plate; and a second sealing resin which seals the interior of the outer frame so as to cover the first sealing resin, the inner frame, and the semiconductor element substrate. A clearance is formed between the inner frame and the first sealing resin. The clearance is filled with the second sealing resin. An elastic modulus of the second sealing resin is smaller than an elastic modulus of the first sealing resin.

Description

この発明は、電力用半導体素子を実装したパワーモジュール、特に高温で動作するパワーモジュールの実装構造、およびその製造方法に関するものである。   The present invention relates to a power module on which a power semiconductor element is mounted, and more particularly to a mounting structure for a power module that operates at a high temperature, and a method for manufacturing the same.

従来のケース型のパワーモジュールは、一般にシリコンゲルにてチップ周辺が封止されている。一方、エポキシ封止はチップ周辺を硬い樹脂で拘束することからヒートサイクルやパワーサイクル信頼性が高い。しかし、エポキシ樹脂は硬いことから界面に発生する応力が高く、剥離やクラックという問題が発生するため、構造の制約が非常に多い。（例えば特許文献１）。   Conventional case-type power modules are generally sealed around the chip with silicon gel. On the other hand, epoxy sealing has high heat cycle and power cycle reliability because the periphery of the chip is constrained by a hard resin. However, since the epoxy resin is hard, the stress generated at the interface is high, and the problem of peeling or cracking occurs, so the structure is very limited. (For example, patent document 1).

特許文献１に記載されているパワーモジュールは、半導体素子と絶縁基板間の接合の長寿命化を実現するために、絶縁基板の周囲に分割板を設け、半導体素子の上面における金属ワイヤが接続される部分を、絶縁性の第１の樹脂で覆っている。さらに、絶縁基板の金属回路箔の側面を被覆する絶縁性の第２の樹脂を有し、線膨張係数が半田と等しい絶縁性の第３の樹脂を分割板で囲まれた領域内に注入した構造となっている。この構造体が、複数の絶縁基板毎に設けられ、互いに離れている。さらに全体をシリコンゲル（第４の樹脂）で封止している。このように、各所で樹脂を使い分け、最終的に４種類の樹脂を用いている。   The power module described in Patent Document 1 is provided with a dividing plate around the insulating substrate to connect the metal wires on the upper surface of the semiconductor element in order to realize a long life of the bonding between the semiconductor element and the insulating substrate. The portion to be covered is covered with an insulating first resin. Further, an insulating second resin that covers the side surface of the metal circuit foil of the insulating substrate is injected and an insulating third resin having a linear expansion coefficient equal to that of the solder is injected into the region surrounded by the dividing plate. It has a structure. This structure is provided for each of the plurality of insulating substrates and is separated from each other. Further, the whole is sealed with silicon gel (fourth resin). Thus, the resin is properly used in various places, and finally four types of resins are used.

特開２０１２−１５２２２号公報JP 2012-15222 A

しかしながら、上記のようなパワーモジュールにおいては、４種類の樹脂を使い分ける必要があり、必ずしも樹脂を塗布または注入後に同時に樹脂の硬化過程を実施することができないために、製造工程が多く、生産性に劣るといった課題がある。   However, in the power module as described above, it is necessary to use four types of resins properly, and it is not always possible to carry out the curing process of the resin at the same time after applying or injecting the resin. There is a problem of being inferior.

また、特許文献１では、半導体素子全体を覆う第３の樹脂の線膨張係数は半田と等しいことが開示されている。絶縁基板は窒化アルミニウムや窒化シリコン等のセラミックス製と記載されているように、半田とは大きく線膨張係数が異なる。このため、絶縁基板と第３の樹脂との線膨張係数差が大きく、高温で動作するパワーモジュールでは、界面に発生する応力は大きくなり界面剥離が発生し、半田接合層に応力が集中し半田クラックを引き起こす恐れがある。したがって、高温で動作するパワーモジュールでは、本来の目的である半導体素子と絶縁基板間の接合の長寿命化を達成することができなくなる。   Patent Document 1 discloses that the third resin covering the entire semiconductor element has a linear expansion coefficient equal to that of solder. As described that the insulating substrate is made of a ceramic such as aluminum nitride or silicon nitride, the linear expansion coefficient is significantly different from that of solder. For this reason, in the power module operating at a high temperature with a large difference in linear expansion coefficient between the insulating substrate and the third resin, the stress generated at the interface increases and the interface peeling occurs, stress concentrates on the solder joint layer and the solder May cause cracks. Therefore, in the power module that operates at a high temperature, it is impossible to achieve a long life of the junction between the semiconductor element and the insulating substrate, which is the original purpose.

この発明は、上記のような問題点を解決するためになされたものであり、製造工程が少なく、高温で動作するパワーモジュールにおいても、信頼性の高いパワーモジュールを得ることを目的としている。   The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a highly reliable power module even in a power module operating at a high temperature with few manufacturing processes.

本発明は、絶縁基板の片面に表面電極パターンが、および絶縁基板の他の面に裏面電極パターンが、それぞれ形成された半導体素子基板と、表面電極パターンの、絶縁基板とは反対側の面に接合材を介して固着された半導体素子と、半導体素子基板の周辺部であって、表面電極パターン側に設けられた内枠と、内枠の内部を封止する第１の封止樹脂と、半導体素子基板の裏面電極パターンに接合され、内枠の外周よりも広い放熱板と、放熱板の周辺部であって、半導体素子基板側に設けられた外枠と、外枠の内部を、第１の封止樹脂と内枠と半導体素子基板とを覆うように封止する第２の封止樹脂と、を備えたパワーモジュールにおいて、内枠と第１の封止樹脂との間に間隙が形成され、この間隙に第２の封止樹脂が充填されており、第２の封止樹脂の弾性率が第１の封止樹脂の弾性率よりも小さくしたものである。   The present invention provides a semiconductor element substrate having a surface electrode pattern on one surface of an insulating substrate and a back electrode pattern on the other surface of the insulating substrate, and a surface electrode pattern on the surface opposite to the insulating substrate. A semiconductor element fixed through a bonding material, a peripheral portion of the semiconductor element substrate, an inner frame provided on the surface electrode pattern side, a first sealing resin for sealing the inside of the inner frame, A heat sink bonded to the back electrode pattern of the semiconductor element substrate and wider than the outer periphery of the inner frame, an outer frame provided on the semiconductor element substrate side at the periphery of the heat sink, and an inner portion of the outer frame. In a power module comprising a first sealing resin, a second sealing resin for sealing so as to cover the inner frame and the semiconductor element substrate, there is a gap between the inner frame and the first sealing resin. Formed and filled with the second sealing resin in the gap, In which the elastic modulus of the sealing resin is smaller than the elastic modulus of the first sealing resin.

この発明により、高温で動作するパワーモジュールにおいても、第１の封止樹脂に発生する応力が少なく、第１の封止樹脂の剥離や、第１封止樹脂や半導体素子基板のクラックが発生し難く、信頼性の高いパワーモジュールを、少ない製造工程で得ることができる。   According to the present invention, even in a power module operating at a high temperature, the stress generated in the first sealing resin is small, and the first sealing resin is peeled off and the first sealing resin and the semiconductor element substrate are cracked. A difficult and highly reliable power module can be obtained with few manufacturing steps.

この発明の実施の形態１によるパワーモジュールの構成を示す側面断面図である。It is side surface sectional drawing which shows the structure of the power module by Embodiment 1 of this invention. この発明の実施の形態１によるパワーモジュールの別の構成を示す側面断面図である。It is side surface sectional drawing which shows another structure of the power module by Embodiment 1 of this invention. この発明の実施の形態１によるパワーモジュールの要部を示す拡大断面図である。It is an expanded sectional view which shows the principal part of the power module by Embodiment 1 of this invention. この発明の実施の形態２によるパワーモジュールの製造工程を説明する一番目の図である。It is the first figure explaining the manufacturing process of the power module by Embodiment 2 of this invention. この発明の実施の形態２によるパワーモジュールの製造工程を説明する二番目の図である。It is a 2nd figure explaining the manufacturing process of the power module by Embodiment 2 of this invention. この発明の実施の形態２によるパワーモジュールの製造工程を説明する三番目の図である。It is a 3rd figure explaining the manufacturing process of the power module by Embodiment 2 of this invention.

実施の形態１．
図１は、本発明の実施の形態１によるパワーモジュールの構成を示す側面断面図である。はじめに、本発明の実施の形態１によるパワーモジュールの全体構成について説明する。実施の形態１によるパワーモジュール１００は、セラミックスなどの絶縁材料で形成されている絶縁基板３の回路面には、複数の表面電極パターン４ａが形成され、表面電極パターン４ａのうちの所定の表面電極パターンに半導体素子１が導電性の接合材を用いて固定されるとともに電気的に接続される。また、表面電極パターン４ａとの接合面との反対側の半導体素子１の面である表面に形成された電極は、金属ワイヤ５により、他の表面電極パターン４ａと電気的に接続される。そして、金属ワイヤ５が接続された表面電極パターン４ａには、外部との電気的な接続を行うための配線部材である配線電極６が接合されている。 Embodiment 1 FIG.
FIG. 1 is a side sectional view showing a configuration of a power module according to Embodiment 1 of the present invention. First, the overall configuration of the power module according to Embodiment 1 of the present invention will be described. In the power module 100 according to the first embodiment, a plurality of surface electrode patterns 4a are formed on a circuit surface of an insulating substrate 3 formed of an insulating material such as ceramics, and predetermined surface electrodes of the surface electrode patterns 4a are formed. The semiconductor element 1 is fixed and electrically connected to the pattern using a conductive bonding material. In addition, the electrode formed on the surface that is the surface of the semiconductor element 1 opposite to the bonding surface with the surface electrode pattern 4 a is electrically connected to the other surface electrode pattern 4 a by the metal wire 5. And the wiring electrode 6 which is a wiring member for making an electrical connection with the exterior is joined to the surface electrode pattern 4a to which the metal wire 5 is connected.

一方、絶縁基板３の回路面と反対側の面には、裏面電極パターン４ｂがべた状に形成されており、伝熱性の接合材を介して金属製の放熱板１０が張り合わせられている。絶縁基板３に表面電極パターン４ａおよび裏面電極パターン４ｂが形成されている基板全体を半導体素子基板３４と呼ぶことにする。   On the other hand, the back electrode pattern 4b is formed in a solid shape on the surface of the insulating substrate 3 opposite to the circuit surface, and a metal heat radiating plate 10 is bonded to the surface of the insulating substrate 3 via a heat conductive bonding material. The entire substrate on which the front electrode pattern 4a and the back electrode pattern 4b are formed on the insulating substrate 3 will be referred to as a semiconductor element substrate 34.

半導体素子基板３４の回路面側の外周には内枠７が形成され、半導体素子１や配線部材である金属ワイヤ５や配線電極６を含めて、内枠７の内部が第１の封止樹脂８で封止されている。ただし、配線部材のうち配線電極６は、外部との電気的接続を行うために上部が第１の封止樹脂８から露出している。内枠７は第１の封止樹脂８が漏れるのを防止するために用い、第１の封止樹脂８を硬化する際に内枠７と第１の封止樹脂８とが遊離するように構成されている。すなわち、内枠７の内部を第１の封止樹脂８で封止する際には、内枠７と第１の封止樹脂８との間には間隙が生じる。   An inner frame 7 is formed on the outer periphery of the semiconductor element substrate 34 on the circuit surface side, and the inside of the inner frame 7 including the semiconductor element 1 and the metal wires 5 and the wiring electrodes 6 that are wiring members is a first sealing resin. 8 is sealed. However, the upper part of the wiring electrode 6 of the wiring member is exposed from the first sealing resin 8 in order to make electrical connection with the outside. The inner frame 7 is used to prevent the first sealing resin 8 from leaking, and the inner frame 7 and the first sealing resin 8 are released when the first sealing resin 8 is cured. It is configured. That is, when the inside of the inner frame 7 is sealed with the first sealing resin 8, a gap is generated between the inner frame 7 and the first sealing resin 8.

放熱板１０上には、複数の半導体素子基板３４が接合材を介して張り合わせられている。放熱板１０は半導体素子基板３４よりも広く、放熱板１０の外周には、外枠１１が設けられており、外枠１１の内部は第２の封止樹脂１２で封止されている。第２の封止樹脂１２は、内枠７と第１の封止樹脂８との間の隙間にも充填される。第２の封止樹脂の上部には蓋１３が設けられている。   On the heat sink 10, a plurality of semiconductor element substrates 34 are bonded together with a bonding material. The heat sink 10 is wider than the semiconductor element substrate 34, and an outer frame 11 is provided on the outer periphery of the heat sink 10, and the inside of the outer frame 11 is sealed with a second sealing resin 12. The second sealing resin 12 is also filled in the gap between the inner frame 7 and the first sealing resin 8. A lid 13 is provided on the upper part of the second sealing resin.

つぎに、各部材の詳細について説明する。半導体素子１は、シリコン（Ｓｉ）を基材とした一般的な素子でも良いが、本発明は、より高温で動作する半導体素子に適用したときに好適な構造を目指している。半導体素子１が、例えば炭化ケイ素（ＳｉＣ）や窒化ガリウム（ＧａＮ）、またはダイヤモンドといったシリコンと較べてバンドギャップが広い、いわゆるワイドバンドギャップ半導体材料の半導体素子、特に炭化ケイ素を用いた半導体素子に本発明は好適である。デバイス種類としては、特に限定しないが、ＩＧＢＴ（Insulated Gate Bipolar Transistor）やＭＯＳＦＥＴ（Metal Oxide Semiconductor Field-Effect-Transistor）のようなスイッチング素子、またはダイオードのような整流素子が考えられる。   Next, details of each member will be described. The semiconductor element 1 may be a general element based on silicon (Si), but the present invention aims at a structure suitable when applied to a semiconductor element operating at a higher temperature. The semiconductor element 1 is a semiconductor element of a so-called wide band gap semiconductor material having a wider band gap than silicon such as silicon carbide (SiC), gallium nitride (GaN), or diamond, for example, particularly a semiconductor element using silicon carbide. The invention is preferred. Although it does not specifically limit as a device kind, Switching elements, such as IGBT (Insulated Gate Bipolar Transistor) and MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor), or a rectifier element like a diode can be considered.

半導体素子１がＭＯＳＦＥＴの場合、半導体素子１の表面電極パターン４ａ側の面にはドレイン電極が形成されている。ドレイン電極と反対側（図１では上側）の面には、ゲート電極やソース電極が、領域を分けて形成されている。ただし、ここでは説明を簡単にするため、上側の面には、例えば大電流が流れるソース電極のみが形成されているとして説明する。なお、ドレイン電極の表面には接合材との接合を良好とするための複合金属膜が形成されている。ソース電極の表面にも、厚さ数μｍの薄いアルミニウムなどの電極膜やチタン、モリブデン、ニッケル、金などの薄膜層が形成されている。   When the semiconductor element 1 is a MOSFET, a drain electrode is formed on the surface of the semiconductor element 1 on the surface electrode pattern 4a side. On the surface opposite to the drain electrode (upper side in FIG. 1), a gate electrode and a source electrode are formed in divided regions. However, in order to simplify the description here, it is assumed that only the source electrode through which a large current flows is formed on the upper surface, for example. Note that a composite metal film is formed on the surface of the drain electrode to improve the bonding with the bonding material. On the surface of the source electrode, a thin electrode film such as aluminum having a thickness of several μm and a thin film layer such as titanium, molybdenum, nickel, and gold are formed.

接合材としては、はんだや、例えば銀を主成分とする焼結性フィラーやろう材、錫中に銅を分散した材料といった、熱伝導性が良く導電性の接合材料が適用できる。配線部材としての金属ワイヤ５の材質として、アルミニウム、銅、金などがあげられる。配線部材は、金属ワイヤの他、図２に示すように、導電性のよい金属、例えば銅からなるリード１４を用い、半導体素子１と接合材１５を用いて接合してもよく、ワイヤボンディング以外の接合方法で接合しても構わない。接合材１５は半導体素子１の電極と表面電極パターン４ａとを接合する接合材と同じく、はんだや、例えば銀を主成分とする焼結性フィラーやろう材、錫中に銅を分散した材料といった接合材料が適用できる。配線電極６には、銅、鉄、アルミニウム等の金属からなる円柱、円筒状またはＬ字状の板材等が適用できる。   As the bonding material, a conductive bonding material having good thermal conductivity, such as solder, a sinter filler or brazing material containing silver as a main component, or a material in which copper is dispersed in tin, can be applied. Examples of the material of the metal wire 5 as the wiring member include aluminum, copper, and gold. As shown in FIG. 2, the wiring member may use a lead 14 made of a highly conductive metal, for example, copper, and may be bonded using the semiconductor element 1 and the bonding material 15 as shown in FIG. 2. You may join by the joining method of. Similar to the bonding material for bonding the electrode of the semiconductor element 1 and the surface electrode pattern 4a, the bonding material 15 is solder, for example, a sinter filler or brazing material mainly composed of silver, or a material in which copper is dispersed in tin. Bonding material can be applied. The wiring electrode 6 may be a columnar, cylindrical or L-shaped plate made of a metal such as copper, iron, or aluminum.

絶縁基板３には、伝熱性に優れた窒化アルミニウム、窒化ケイ素、窒化ホウ素、酸化アルミニウム（アルミナ）などのセラミックス材料を用いることができる。表面電極パターン４ａおよび裏面電極パターン４ｂは、銅、アルミニウムなどの導電性材料またはそれらを主成分とする合金材料からなり、ろう材などで絶縁基板３に対して接合されている。そして表面電極パターン４ａおよび裏面電極パターン４ｂの表面には、酸化防止や接合材料の濡れ性を考慮して、ニッケルなどのめっき被膜が形成されている場合がある。   For the insulating substrate 3, a ceramic material such as aluminum nitride, silicon nitride, boron nitride, aluminum oxide (alumina) having excellent heat conductivity can be used. The front electrode pattern 4a and the back electrode pattern 4b are made of a conductive material such as copper or aluminum or an alloy material containing them as a main component, and are bonded to the insulating substrate 3 with a brazing material or the like. A plating film such as nickel may be formed on the surfaces of the front electrode pattern 4a and the back electrode pattern 4b in consideration of oxidation prevention and wettability of the bonding material.

内枠７は、第１の封止樹脂８を形成するため硬化前の樹脂を注入する際に樹脂漏れを防止するために設ける。硬化前の樹脂を内枠７の内部に注入し、硬化して第１の封止樹脂８を形成した後に異種材料間に発生する応力を低減するために、第１の封止樹脂８と内枠７とは容易に剥がれるようにする。容易に剥がれるようにするため、内枠７の材料として、第１の封止樹脂８の硬化温度以上の融点を有する材料でフッ素系のプラスチック材、例えばポリテトラフルオロエチレン樹脂（ＰＴＦＥ）、ポリフッ化ビニリデン樹脂（ＰＶｄＦ）、テトラフルオロエチレンとエチレンとの共重合体樹脂（ＥＴＦＥ）や、一般に型取り用シリコンと呼ばれている樹脂を用いる。第１の封止樹脂８を、後述のようにエポキシ樹脂にセラミックスを混入した材料として、内枠７を上記のように接着性が弱い材料とすることで、内枠７と第１の封止樹脂８とは、遊離し両材料間には間隙が発生する。遊離することで、界面に発生する応力を低減できることができる。ただし、内枠７と第１の封止樹脂８との間が完全に遊離していなくても良く、一部が遊離することでも、全体が接着されている場合に比較して、発生する応力が低減するという本発明の効果を奏する。   The inner frame 7 is provided in order to prevent resin leakage when injecting a resin before curing to form the first sealing resin 8. In order to reduce the stress generated between different materials after injecting the resin before curing into the inner frame 7 and curing to form the first sealing resin 8, The frame 7 is easily peeled off. In order to make it easy to peel off, the material of the inner frame 7 is a material having a melting point equal to or higher than the curing temperature of the first sealing resin 8 and a fluorine-based plastic material such as polytetrafluoroethylene resin (PTFE), polyfluoride. A vinylidene resin (PVdF), a copolymer resin of tetrafluoroethylene and ethylene (ETFE), or a resin generally referred to as mold making silicon is used. The first sealing resin 8 is made of a material in which ceramics are mixed in an epoxy resin as will be described later, and the inner frame 7 is made of a material having low adhesiveness as described above. The resin 8 is released and a gap is generated between the two materials. By separating, the stress generated at the interface can be reduced. However, the stress generated between the inner frame 7 and the first sealing resin 8 does not have to be completely separated. The effect of the present invention is reduced.

第１の封止樹脂８を形成する硬化前の樹脂は室温で流動性を示す樹脂で、エポキシ樹脂のような熱硬化性樹脂に、溶融シリカなどのセラミックス粒子・繊維等のフィラーを混入し、硬化後の熱膨張係数や弾性率を調整した材料を用いる。注入の際は、硬化反応が起こらない温度範囲で、加温して流動性を良くして注入することができる。硬化後の第１の封止樹脂８の熱膨張係数を、半導体素子基板３４の熱膨張係数に近い熱膨張係数とすることで、界面に発生する応力を低減でき界面剥離や樹脂破断を防止でき、モジュールの信頼性を向上させることができる。絶縁基板３の熱膨張係数は、窒化アルミニウムが４．５ｐｐｍ／Ｋ、窒化ケイ素が３ｐｐｍ／Ｋ、酸化アルミニウムが７．３ｐｐｍ／Ｋであり、表面電極パターン４ａや裏面電極パターン４ｂの熱膨張係数は、銅が１７ｐｐｍ／Ｋ、アルミニウムが２４ｐｐｍ／Ｋである。したがって、セラミックスと電極パターンの厚み構成によるが、絶縁基板３に表面電極パターン４ａおよび裏面電極パターン４ｂが接合された半導体素子基板３４全体としての熱膨張係数は、７〜１５ｐｐｍ／Ｋとなる。したがって、第１の封止樹脂８のガラス転移温度以下の熱膨張係数も７〜１５ｐｐｍ／Ｋであることが望ましい。第１の封止樹脂８の熱膨張係数は、半導体素子基板３４の熱膨張係数と等しくするのが最も好ましいが、後述のように、第１の封止樹脂８の熱膨張係数と半導体素子基板３４の熱膨張係数の差が５ｐｐｍ／Ｋ以下であれば、剥離やクラックが発生し難いことがわかった。   The resin before curing that forms the first sealing resin 8 is a resin that exhibits fluidity at room temperature, and a ceramic particle such as fused silica or a filler such as fiber is mixed into a thermosetting resin such as an epoxy resin, A material with adjusted thermal expansion coefficient and elastic modulus after curing is used. At the time of injection, it can be injected in a temperature range in which a curing reaction does not occur with heating to improve fluidity. By setting the thermal expansion coefficient of the first sealing resin 8 after curing to a thermal expansion coefficient close to the thermal expansion coefficient of the semiconductor element substrate 34, it is possible to reduce stress generated at the interface and prevent interface peeling and resin breakage. , Module reliability can be improved. The thermal expansion coefficients of the insulating substrate 3 are 4.5 ppm / K for aluminum nitride, 3 ppm / K for silicon nitride, and 7.3 ppm / K for aluminum oxide. The thermal expansion coefficients of the front electrode pattern 4a and the back electrode pattern 4b are Copper is 17 ppm / K and aluminum is 24 ppm / K. Therefore, depending on the thickness configuration of the ceramics and the electrode pattern, the thermal expansion coefficient of the entire semiconductor element substrate 34 in which the front electrode pattern 4a and the back electrode pattern 4b are joined to the insulating substrate 3 is 7 to 15 ppm / K. Therefore, it is desirable that the thermal expansion coefficient of the first sealing resin 8 not higher than the glass transition temperature is also 7 to 15 ppm / K. The thermal expansion coefficient of the first sealing resin 8 is most preferably equal to the thermal expansion coefficient of the semiconductor element substrate 34, but as will be described later, the thermal expansion coefficient of the first sealing resin 8 and the semiconductor element substrate It was found that if the difference in thermal expansion coefficient of 34 is 5 ppm / K or less, peeling and cracks are difficult to occur.

金属製の放熱板１０は、熱伝導性の良い金属材料、例えば銅の板材で構成されている。銅が主成分であれば良く、銅以外の金属を含有していても構わない。また、軽量で熱伝導性の高いアルミニウムまたはその合金でもよい。放熱板１０は接合材を介して半導体素子基板３４の裏面電極パターン４ｂと接合している。放熱板１０と裏面電極パターン４ｂとの接合材は半導体素子１と表面電極パターン４ａとの接合材と同様に熱伝導性の良いはんだや、例えば銀を主成分とする焼結性フィラーやろう材を用いることもできる。さらに、熱伝導性の良い絶縁性の接着剤でも構わない。   The metal heat sink 10 is made of a metal material having good thermal conductivity, for example, a copper plate. It suffices if copper is a main component, and a metal other than copper may be contained. Also, aluminum or an alloy thereof having light weight and high thermal conductivity may be used. The heat sink 10 is bonded to the back electrode pattern 4b of the semiconductor element substrate 34 through a bonding material. The bonding material between the heat radiating plate 10 and the back surface electrode pattern 4b is a solder having good thermal conductivity, for example, a sinterable filler or brazing material mainly composed of silver, like the bonding material between the semiconductor element 1 and the front surface electrode pattern 4a. Can also be used. Furthermore, an insulating adhesive having good thermal conductivity may be used.

外枠１１は、放熱板１０と接着剤等で固定されている。外枠１１は硬化前の第２の封止樹脂１２を注入する際に樹脂漏れを防止するために設けている。外枠１１の材料としては、少なくとも樹脂の硬化温度や、半導体素子１が動作する際のパワーモジュールの温度以上の融点を有する樹脂材であれば良い。この条件を満足する材料として、通常枠体として良く用いられるポリｐ−フェニレンサルファイド樹脂（ＰＰＳ）やポリブチレンテレフタレート樹脂（ＰＢＴ）、ナイロン樹脂などがある。   The outer frame 11 is fixed to the heat radiating plate 10 with an adhesive or the like. The outer frame 11 is provided to prevent resin leakage when injecting the second sealing resin 12 before curing. The material of the outer frame 11 may be a resin material having a melting point equal to or higher than the curing temperature of the resin and the temperature of the power module when the semiconductor element 1 operates. Examples of the material that satisfies this condition include poly p-phenylene sulfide resin (PPS), polybutylene terephthalate resin (PBT), and nylon resin that are often used as frames.

第２の封止樹脂１２は、硬化前に室温で流動性を示す樹脂であれば良いが、大型のモジュール全体を封止するとともに、硬化後、発生応力が大きくならないよう、シリコン系やウレタン系の柔らかい樹脂が良い。第２の封止樹脂１２は、第１の封止樹脂８に比較して樹脂硬化後の弾性率が小さい。図３に、図１の破線で囲んだ領域Ａの部分拡大図を示す。図３に示すように、第２の封止樹脂１２は内枠７と第１の封止樹脂８間の間隙７８にも充填される。内枠７と第１の封止樹脂８間の間隙７８が第１の封止樹脂よりも弾性率が小さい、すなわち柔らかい樹脂で充填されるため、半導体素子１が高温で動作し、高温となった場合でも、第１の封止樹脂８と内枠７との間で発生する応力が、柔らかい第２の封止樹脂で緩和される。ただし、前述のように、内枠７と第１の封止樹脂８との間が完全に遊離していなくても良く、一部が遊離し、遊離している部分に第２の封止樹脂が充填されている構成でも、内枠７と第１の封止樹脂８との間全体が接着されている場合に比較して、発生する応力が低減するという本発明の効果を奏する。   The second sealing resin 12 may be any resin that exhibits fluidity at room temperature before curing, but seals the entire large-sized module and, after curing, a silicon-based or urethane-based resin so that generated stress does not increase. Soft resin is good. The second sealing resin 12 has a smaller elastic modulus after resin curing than the first sealing resin 8. FIG. 3 shows a partially enlarged view of a region A surrounded by a broken line in FIG. As shown in FIG. 3, the second sealing resin 12 is also filled in the gap 78 between the inner frame 7 and the first sealing resin 8. Since the gap 78 between the inner frame 7 and the first sealing resin 8 has a lower elastic modulus than the first sealing resin, that is, is filled with a soft resin, the semiconductor element 1 operates at a high temperature and becomes a high temperature. Even in this case, the stress generated between the first sealing resin 8 and the inner frame 7 is relaxed by the soft second sealing resin. However, as described above, the space between the inner frame 7 and the first sealing resin 8 may not be completely separated, and a part of the inner frame 7 and the first sealing resin 8 are separated. Even when the structure is filled, the effect of the present invention that the generated stress is reduced as compared with the case where the whole between the inner frame 7 and the first sealing resin 8 is bonded.

蓋１３は配線電極６の端部をモジュールの最外層に露出させ、第２の封止樹脂１２を覆うように固定する。蓋１３の材質は、特に規定されないが外枠１１と同じ材質であることが望ましい。同じ材質であることにより、外枠１１との間に発生する応力を低減できる。   The lid 13 is fixed so that the end of the wiring electrode 6 is exposed to the outermost layer of the module and covers the second sealing resin 12. The material of the lid 13 is not particularly specified, but is preferably the same material as the outer frame 11. By using the same material, stress generated between the outer frame 11 and the outer frame 11 can be reduced.

実施の形態２．
実施の形態２では、本実施の形態１によるパワーモジュール１００の製造方法について、製造方法の工程を図示する図４〜図６を参照して説明する。図４のＳＴ１に示すように、絶縁基板３の回路面となる上面に互いに電気的に独立した複数の電極パターンからなる表面電極パターン４ａを、下面にべた状の裏面電極パターン４ｂを形成して半導体素子基板３４とする。次に図４のＳＴ２に示すように、半導体素子基板３４の表面電極パターン４ａに半導体素子１を導電性の接合材を用いて固定する。そして、図４のＳＴ３に示すように、半導体素子１の表面に形成された電極と、他の表面電極パターン４ａ間を金属ワイヤ５により、電気的に接続する。さらに図４のＳＴ４に示すように、半導体素子１が直接接合された表面電極パターン４ａおよび金属ワイヤ５を介して半導体素子１と電気的に接続された表面電極パターン４ａに、外部との電気的な接続を行うための配線電極６を接合する。 Embodiment 2. FIG.
In the second embodiment, a method for manufacturing the power module 100 according to the first embodiment will be described with reference to FIGS. 4 to 6 illustrating the steps of the manufacturing method. As shown in ST1 of FIG. 4, a surface electrode pattern 4a composed of a plurality of electrode patterns electrically independent from each other is formed on the upper surface, which is a circuit surface of the insulating substrate 3, and a solid back electrode pattern 4b is formed on the lower surface The semiconductor element substrate 34 is assumed. Next, as shown in ST2 of FIG. 4, the semiconductor element 1 is fixed to the surface electrode pattern 4a of the semiconductor element substrate 34 using a conductive bonding material. Then, as shown in ST3 of FIG. 4, the electrode formed on the surface of the semiconductor element 1 and the other surface electrode pattern 4a are electrically connected by a metal wire 5. Furthermore, as shown in ST4 of FIG. 4, the surface electrode pattern 4a to which the semiconductor element 1 is directly bonded and the surface electrode pattern 4a electrically connected to the semiconductor element 1 through the metal wire 5 are electrically connected to the outside. The wiring electrode 6 for making a proper connection is joined.

次に、図５のＳＴ５に示すように、半導体素子基板３４の外周部に樹脂との離型性の材質からなる内枠７を接合する。接合には接着剤等を用いる。図５のＳＴ６に示すように、第１の封止樹脂８を形成するための硬化前の樹脂を内枠７の内部に注入する。この際、室温で流動性を示す硬化前の樹脂の注入作業を良くするために、樹脂の硬化反応が進行しない範囲で加温してもよい。樹脂の注入量は、内枠７を超えない範囲であればよい。第１の封止樹脂８を形成するための硬化前の樹脂を注入後に、樹脂の硬化を行う。内枠７が離型性の材質のため、樹脂硬化後は、容易に内枠７と第１の封止樹脂８は剥がれ、間隙が生ずる。   Next, as shown in ST5 of FIG. 5, the inner frame 7 made of a releasable material from the resin is joined to the outer periphery of the semiconductor element substrate 34. An adhesive or the like is used for bonding. As shown in ST6 of FIG. 5, a resin before curing for forming the first sealing resin 8 is injected into the inner frame 7. At this time, in order to improve the injection operation of the resin before curing that exhibits fluidity at room temperature, the resin may be heated in a range in which the resin curing reaction does not proceed. The amount of resin injected may be in a range not exceeding the inner frame 7. The resin is cured after the uncured resin for forming the first sealing resin 8 is injected. Since the inner frame 7 is a releasable material, the inner frame 7 and the first sealing resin 8 are easily peeled off after the resin is cured, resulting in a gap.

次に、図５のＳＴ７に示すように、第１の封止樹脂８の硬化後の複数の半導体素子基板３４を放熱板１０の所定位置に、半導体素子基板３４の裏面電極パターン４ｂの面と接合材を介して接合する。さらに、図６のＳＴ８に示すように、放熱板１０の外周部に外枠１１を接合する。接合には接着剤等を用いる。図６のＳＴ９に示すように、外枠１１の内部に第２の封止樹脂１２を形成する硬化前の樹脂を注入する。最後に図６のＳＴ１０に示すように、第２の封止樹脂１２の硬化を行った後に、蓋１３を配線電極６が外に取り出せるようにして接合し、配線電極６を曲げ加工する。   Next, as shown in ST7 of FIG. 5, the plurality of semiconductor element substrates 34 after the first sealing resin 8 is cured are placed at predetermined positions on the heat radiating plate 10 and the surface of the back electrode pattern 4b of the semiconductor element substrate 34. Joining via a joining material. Furthermore, as shown in ST8 of FIG. 6, the outer frame 11 is joined to the outer peripheral part of the heat sink 10. An adhesive or the like is used for bonding. As shown in ST9 of FIG. 6, a resin before curing that forms the second sealing resin 12 is injected into the outer frame 11. Finally, as shown in ST10 of FIG. 6, after the second sealing resin 12 is cured, the lid 13 is joined so that the wiring electrode 6 can be taken out, and the wiring electrode 6 is bent.

次に動作について説明する。パワーモジュール１００を駆動させると、半導体素子１をはじめとするパワーモジュール１００内の様々な素子に電流が流れ、その際に電気抵抗成分やスイッチングによる電力ロスが熱に変換され発熱する。半導体素子１で発生した熱は半導体素子基板３４を経由して、放熱板１０を介して外部に放熱されることになるが、パワーモジュール１００全体の温度も上昇する。このとき半導体素子１として、ＳｉＣのような高温動作が可能な半導体材料の半導体素子を用いると、電流が大きく、動作時の温度は３００℃にまで達する。しかし、本発明によるパワーモジュール１００では、半導体素子１や配線部材である金属ワイヤ５や配線電極６等の回路部材を含む半導体素子基板３４の回路面側を第１の封止樹脂８により拘束し、しかも、第１の封止樹脂８の熱膨張係数を半導体素子基板３４の熱膨張係数に近くなるように調整しているので、半導体素子基板３４や回路部材に対する熱応力の発生を抑えることができる。この際、熱膨張係数が大きな内枠７と第１の封止樹脂８は遊離しているので、温度変化に対するヒートサイクルにおいて、半導体素子基板３４と第１の封止樹脂８との界面での剥離やセラミックス材からなる
絶縁基板３の割れが発生するようなことがない。また、放熱板１０に固定された複数の第１の封止樹脂８で覆われた半導体素子基板３４の露出部は、柔らかい第２の封止樹脂１２で覆われていることから、ヒートサイクル時の発生応力は小さく、パワーモジュール１００としての信頼性も非常に高い。 Next, the operation will be described. When the power module 100 is driven, a current flows through various elements in the power module 100 such as the semiconductor element 1, and at that time, an electric resistance component and a power loss due to switching are converted into heat to generate heat. The heat generated in the semiconductor element 1 is radiated to the outside via the semiconductor element substrate 34 and the heat radiating plate 10, but the temperature of the entire power module 100 also rises. At this time, when a semiconductor element made of a semiconductor material capable of high-temperature operation such as SiC is used as the semiconductor element 1, the current is large and the operating temperature reaches 300 ° C. However, in the power module 100 according to the present invention, the first sealing resin 8 restrains the circuit surface side of the semiconductor element substrate 34 including circuit elements such as the semiconductor element 1 and the metal wires 5 and wiring electrodes 6 that are wiring members. In addition, since the thermal expansion coefficient of the first sealing resin 8 is adjusted to be close to the thermal expansion coefficient of the semiconductor element substrate 34, generation of thermal stress on the semiconductor element substrate 34 and circuit members can be suppressed. it can. At this time, since the inner frame 7 and the first sealing resin 8 having a large thermal expansion coefficient are separated, in the heat cycle against the temperature change, at the interface between the semiconductor element substrate 34 and the first sealing resin 8. Peeling or cracking of the insulating substrate 3 made of a ceramic material does not occur. Further, since the exposed portion of the semiconductor element substrate 34 covered with the plurality of first sealing resins 8 fixed to the heat radiating plate 10 is covered with the soft second sealing resin 12, during the heat cycle, The generated stress is small and the reliability as the power module 100 is very high.

したがって、絶縁基板３に、脆性のある材料を使用しても信頼性を低下させることがないので、脆性があるが、伝熱性に優れるセラミックス材を絶縁基板３に用いることにより、放熱特性に優れ、信頼性の高いパワーモジュール１００を得ることが可能となる。   Therefore, even if a brittle material is used for the insulating substrate 3, the reliability is not lowered. Therefore, the insulating substrate 3 is made of a ceramic material that is brittle but has excellent heat conductivity. Thus, it becomes possible to obtain the power module 100 with high reliability.

実施の形態３．
本実施の形態３では、実施の形態２とは別のパワーモジュールの製造方法について説明する。ただし、パワーモジュールの構造図や製造工程を説明する図は、図１や図４〜図６と同様である。本実施の形態３は、実施の形態１および２で説明したパワーモジュールに対して、内枠７の材質を変更したものである。内枠７の材質として、通常枠体として良く用いられるポリｐ−フェニレンサルファイド樹脂（ＰＰＳ）やポリブチレンテレフタレート樹脂（ＰＢＴ）、ナイロン樹脂を用いる。このままの状態では、第１の封止樹脂８を硬化した後に、内枠７と第１の封止樹脂８とは遊離しない。そのため、図５のＳＴ６の工程時に、内枠７の少なくとも第１の封止樹脂８が接する面にフッ素系またはシリコン系の離型剤を塗布して、第１の封止樹脂８の樹脂硬化後の遊離を容易にする。硬化後、離型剤は除去しても良い。その他の製造方法については、実施の形態２と同様であるので説明を省略する。 Embodiment 3 FIG.
In the third embodiment, a method for manufacturing a power module different from the second embodiment will be described. However, the structural diagram of the power module and the diagram for explaining the manufacturing process are the same as those in FIG. 1 and FIGS. In the third embodiment, the material of the inner frame 7 is changed with respect to the power modules described in the first and second embodiments. As the material of the inner frame 7, poly p-phenylene sulfide resin (PPS), polybutylene terephthalate resin (PBT), and nylon resin, which are often used as a normal frame, are used. In this state, the inner frame 7 and the first sealing resin 8 are not released after the first sealing resin 8 is cured. Therefore, at the time of step ST6 in FIG. 5, a fluorine-based or silicon-based release agent is applied to at least the surface of the inner frame 7 in contact with the first sealing resin 8, so that the resin hardening of the first sealing resin 8 is performed. Facilitates later release. After curing, the release agent may be removed. Since other manufacturing methods are the same as those in the second embodiment, description thereof will be omitted.

本実施の形態３によれば、内枠７の材質に、枠材として実績の高い材料を適用することが可能であり、比較的高価なフッ素系の樹脂を使用しなくてよい。また、第１の封止樹脂８が接する面にのみ離型剤を塗布することで、内枠７と第１の封止樹脂８の遊離が必要とされる部分以外の接着性が確保でき、信頼性が向上する。   According to the third embodiment, it is possible to apply a material with a proven track record as the material of the inner frame 7, and it is not necessary to use a relatively expensive fluorine-based resin. In addition, by applying the release agent only to the surface in contact with the first sealing resin 8, it is possible to ensure the adhesiveness other than the portion where the inner frame 7 and the first sealing resin 8 need to be released, Reliability is improved.

実施例．
実施の形態１の構造のパワーモジュールを作製し、ヒートサイクル信頼性試験に投入した。まず、パワーモジュール１００の具体的な構成について説明する。 Example.
A power module having the structure of the first embodiment was manufactured and put into a heat cycle reliability test. First, a specific configuration of the power module 100 will be described.

窒化ケイ素からなる絶縁基板３（４０ｍｍ×２０ｍｍ、０．９２ｍｍ厚）表面に０．３ｍｍ厚の表面電極パターン４ａおよび裏面電極パターン４ｂを形成して半導体素子基板３４とする。半導体素子１として、１５ｍｍ角のＩＧＢＴチップと１５ｍｍ角のダイオードチップ各１個を、錫中に銅粒子を分散させた接合材を用いて、半導体素子基板３４に接合する。また、同時に配線電極６も接合材を用いて半導体素子基板３４上に接合する。   A surface electrode pattern 4a and a back electrode pattern 4b having a thickness of 0.3 mm are formed on the surface of an insulating substrate 3 (40 mm × 20 mm, 0.92 mm thickness) made of silicon nitride to form a semiconductor element substrate 34. As the semiconductor element 1, one 15 mm square IGBT chip and one 15 mm square diode chip are bonded to the semiconductor element substrate 34 using a bonding material in which copper particles are dispersed in tin. At the same time, the wiring electrode 6 is also bonded onto the semiconductor element substrate 34 using a bonding material.

アルミニウムからなる金属ワイヤ５で電気配線を行い、ポリテトラフルオロエチレン樹脂からなる内枠７を、接着剤を介して、半導体素子基板３４の外周部に固定する。内枠７の内部に表１に示す物性を有する第１の封止樹脂８を形成する硬化前の樹脂を注入し、樹脂を硬化させる。   Electrical wiring is performed with the metal wire 5 made of aluminum, and the inner frame 7 made of polytetrafluoroethylene resin is fixed to the outer peripheral portion of the semiconductor element substrate 34 via an adhesive. An uncured resin for forming the first sealing resin 8 having the physical properties shown in Table 1 is injected into the inner frame 7 to cure the resin.

その後、２個の上記半導体素子基板３４を放熱板１０の所定位置に錫中に銅粒子を分散させた接合材を用いて接合する。ポリｐ−フェニレンサルファイド樹脂からなる外枠１１を放熱板１０の周囲に接着剤を用いて固定し、第２の封止樹脂を形成するシリコン樹脂からなる硬化前の樹脂を注入する。樹脂硬化後に蓋１３を接着剤で固定し、蓋１３から飛び出している配線電極６を曲げ加工してパワーモジュール１００を完成させる。   Thereafter, the two semiconductor element substrates 34 are bonded to predetermined positions of the heat sink 10 using a bonding material in which copper particles are dispersed in tin. The outer frame 11 made of poly-p-phenylene sulfide resin is fixed around the heat radiating plate 10 with an adhesive, and an uncured resin made of silicon resin forming the second sealing resin is injected. After the resin is cured, the lid 13 is fixed with an adhesive, and the wiring electrode 6 protruding from the lid 13 is bent to complete the power module 100.

このパワーモジュール１００を−４０℃から１２５℃（各３０分間保持）のヒートサイクル信頼性試験に投入し、５００サイクル毎に取り出し、外観上の損傷、半導体素子１の動作、半導体素子基板３４の絶縁試験（２．５ｋＶ、１分間印加）を実施して問題ないかを確認した。   The power module 100 is put into a heat cycle reliability test of −40 ° C. to 125 ° C. (held for 30 minutes each), taken out every 500 cycles, damaged in appearance, operation of the semiconductor element 1, insulation of the semiconductor element substrate 34. A test (applied at 2.5 kV for 1 minute) was carried out to confirm whether there was any problem.

表１に、５００サイクル毎の信頼性試験の結果を示す。信頼性試験の目標として１０００サイクルとした場合、樹脂Ａから樹脂Ｄは目標を満足することになる。ここで、半導体素子基板３４の熱膨張係数は１０ｐｐｍ／Ｋであるので、半導体素子基板３４の熱膨張係数と第１の封止樹脂の熱膨張係数の差が５ｐｐｍ／Ｋ以下であれば目標を満足する。   Table 1 shows the results of reliability tests every 500 cycles. When the reliability test target is 1000 cycles, the resin A to the resin D satisfy the target. Here, since the thermal expansion coefficient of the semiconductor element substrate 34 is 10 ppm / K, if the difference between the thermal expansion coefficient of the semiconductor element substrate 34 and the thermal expansion coefficient of the first sealing resin is 5 ppm / K or less, the target is set. Satisfied.

Figure 2014150203
Figure 2014150203

なお、本発明は、その発明の範囲内において、各実施の形態を組み合わせたり、各実施の形態を適宜、変形、省略したりすることが可能である。   It should be noted that the present invention can be combined with each other within the scope of the invention, or can be appropriately modified or omitted from each embodiment.

１：半導体素子、３：絶縁基板、４ａ：表面電極パターン、４ｂ：裏面電極パターン、５：金属ワイヤ、６：配線電極、７：内枠、８：第１の封止樹脂、１０：放熱板、１１：外枠、１２：第２の封止樹脂、１３：蓋、３４：半導体素子基板、７８：間隙 1: Semiconductor element, 3: Insulating substrate, 4a: Front electrode pattern, 4b: Back electrode pattern, 5: Metal wire, 6: Wiring electrode, 7: Inner frame, 8: First sealing resin, 10: Heat dissipation plate , 11: outer frame, 12: second sealing resin, 13: lid, 34: semiconductor element substrate, 78: gap

Claims (7)

絶縁基板の片面に表面電極パターンが、および前記絶縁基板の他の面に裏面電極パターンが、それぞれ形成された半導体素子基板と、
前記表面電極パターンの、前記絶縁基板とは反対側の面に接合材を介して固着された半導体素子と、
前記半導体素子基板の周辺部であって、前記表面電極パターン側に設けられた内枠と、
前記内枠の内部を、前記半導体素子と前記半導体素子基板とを覆うように封止する第１の封止樹脂と、
前記半導体素子基板の前記裏面電極パターンに接合され、前記半導体素子基板よりも広い放熱板と、
前記放熱板の周辺部であって、前記半導体素子基板側に設けられた外枠と、
前記外枠の内部を、前記第１の封止樹脂と前記内枠と前記半導体素子基板とを覆うように封止する第２の封止樹脂と、を備えたパワーモジュールにおいて、
前記内枠と前記第１の封止樹脂との間に間隙が形成され、この間隙に前記第２の封止樹脂が充填されており、前記第２の封止樹脂の弾性率が前記第１の封止樹脂の弾性率よりも小さいことを特徴とするパワーモジュール。 A semiconductor element substrate in which a front surface electrode pattern is formed on one side of the insulating substrate and a back surface electrode pattern is formed on the other surface of the insulating substrate;
A semiconductor element fixed to a surface of the surface electrode pattern opposite to the insulating substrate via a bonding material;
A peripheral portion of the semiconductor element substrate, and an inner frame provided on the surface electrode pattern side;
A first sealing resin that seals the inside of the inner frame so as to cover the semiconductor element and the semiconductor element substrate;
Bonded to the back electrode pattern of the semiconductor element substrate, a heat sink wider than the semiconductor element substrate,
An outer frame provided on the semiconductor element substrate side in the periphery of the heat sink;
In the power module comprising the second sealing resin that seals the inside of the outer frame so as to cover the first sealing resin, the inner frame, and the semiconductor element substrate,
A gap is formed between the inner frame and the first sealing resin, and the gap is filled with the second sealing resin, and the elastic modulus of the second sealing resin is the first sealing resin. A power module characterized by being smaller than the elastic modulus of the sealing resin. 前記第１の封止樹脂の熱膨張係数と、前記半導体素子基板の熱膨張係数との差が、５ｐｐｍ／ｋ以下であることを特徴とする請求項１に記載のパワーモジュール。   The power module according to claim 1, wherein a difference between a thermal expansion coefficient of the first sealing resin and a thermal expansion coefficient of the semiconductor element substrate is 5 ppm / k or less. 前記内枠の材料が、離形性の材料であることを特徴とする請求項１または２に記載のパワーモジュール。   The power module according to claim 1 or 2, wherein the material of the inner frame is a releasable material. 前記内枠の材料が、フッ素を含有する樹脂材料であることを特徴とする請求項３に記載のパワーモジュール。   The power module according to claim 3, wherein the material of the inner frame is a resin material containing fluorine. 前記半導体素子がワイドバンドギャップ半導体により形成されていることを特徴とする請求項１〜４のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor element is formed of a wide band gap semiconductor. 前記ワイドバンドギャップ半導体は、炭化珪素、窒化ガリウム系材料、ダイヤモンドのいずれかの半導体であることを特徴とする請求項５に記載の半導体装置。   6. The semiconductor device according to claim 5, wherein the wide band gap semiconductor is one of silicon carbide, a gallium nitride-based material, and diamond. 請求項１に記載のパワーモジュールの製造方法において、
前記内枠の前記第１の封止樹脂に対向する面となる面に離型剤を塗布して、前記内枠の内部に硬化前の樹脂を注入し、その後前記硬化前の樹脂を硬化させて前記第１の封止樹脂を形成することを特徴とするパワーモジュールの製造方法。 In the manufacturing method of the power module of Claim 1,
A release agent is applied to the surface of the inner frame that faces the first sealing resin, and a resin before curing is injected into the inner frame, and then the resin before curing is cured. And forming the first sealing resin.
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Publication number Priority date Publication date Assignee Title
JP2016171269A (en) * 2015-03-16 2016-09-23 三菱電機株式会社 Power semiconductor device
JP2016207910A (en) * 2015-04-27 2016-12-08 三菱電機株式会社 Semiconductor device
JP2017028159A (en) * 2015-07-24 2017-02-02 富士電機株式会社 Semiconductor device and method of manufacturing the same
JPWO2017168756A1 (en) * 2016-04-01 2018-11-29 三菱電機株式会社 Semiconductor device
US11011442B2 (en) 2015-03-27 2021-05-18 Mitsubishi Electric Corporation Power module
CN113841237A (en) * 2019-05-30 2021-12-24 三菱电机株式会社 Power semiconductor module and power conversion device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016171269A (en) * 2015-03-16 2016-09-23 三菱電機株式会社 Power semiconductor device
US11011442B2 (en) 2015-03-27 2021-05-18 Mitsubishi Electric Corporation Power module
JP2016207910A (en) * 2015-04-27 2016-12-08 三菱電機株式会社 Semiconductor device
JP2017028159A (en) * 2015-07-24 2017-02-02 富士電機株式会社 Semiconductor device and method of manufacturing the same
JPWO2017168756A1 (en) * 2016-04-01 2018-11-29 三菱電機株式会社 Semiconductor device
US10825751B2 (en) 2016-04-01 2020-11-03 Mitsubishi Electric Corporation Semiconductor device
CN113841237A (en) * 2019-05-30 2021-12-24 三菱电机株式会社 Power semiconductor module and power conversion device

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