JP2012015222A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2012015222A
JP2012015222A JP2010148439A JP2010148439A JP2012015222A JP 2012015222 A JP2012015222 A JP 2012015222A JP 2010148439 A JP2010148439 A JP 2010148439A JP 2010148439 A JP2010148439 A JP 2010148439A JP 2012015222 A JP2012015222 A JP 2012015222A
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resin
metal
circuit foil
metal circuit
semiconductor device
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Tatsuya Matsumoto
達也 松本
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Hitachi Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can ensure long service life of joint between a semiconductor element 1 and an insulation substrate 4.SOLUTION: The semiconductor device comprises: a first metal circuit foil 5c bonded to each top face of a plurality of insulation substrates 4; a semiconductor element 1 with a bottom face bonded to the first metal circuit foil 5c by solder; a second metal circuit foil 5a bonded to each top face of the insulation substrates 4 away from the first metal circuit foil 5c and connected to the top face of the semiconductor element 1 via a metallic wire 3; a first insulative resin 17c for coating a joint part between the metallic wire 3 and the semiconductor element 1; second insulative resins 17a and 17b for coating side faces of the first metal circuit foil 5c and the second metal circuit foil 5a; and a third insulative resin 18 for coating the first metal circuit foil 5c, the semiconductor element 1, the metallic wire 3, the second metal circuit foil 5a, the first resin 17c and the second resins 17a and 17b. The third resin 18 is harder than the first resin 17c and the second resins 17a and 17b and has a linear expansion coefficient substantially equal to that of solder and provided on each of the plurality of insulation substrates 4 away from each other.

Description

本発明は、半導体素子が樹脂封止されている半導体装置に関する。   The present invention relates to a semiconductor device in which a semiconductor element is resin-sealed.

半導体装置には、モータ等の電気機器を制御するために大電力のスイッチングの制御が可能な、いわゆるパワー半導体装置がある。パワー半導体装置は、その耐圧、電流容量に応じて家電用、産業用、電鉄用などの各種インバータ装置に用いられている。パワー半導体装置では、従来から、半導体素子（半導体スイッチング素子）が樹脂パッケージ内に密封されている。パワー半導体装置内部では、半導体素子の絶縁性を確保する為、半導体素子をシリコーンゲルでコーティングするのが一般的である。   As the semiconductor device, there is a so-called power semiconductor device capable of controlling high-power switching in order to control an electric device such as a motor. Power semiconductor devices are used in various inverter devices for home appliances, industrial use, electric railways, etc., depending on their withstand voltage and current capacity. Conventionally, in a power semiconductor device, a semiconductor element (semiconductor switching element) is sealed in a resin package. In the power semiconductor device, in order to ensure the insulation of the semiconductor element, it is common to coat the semiconductor element with silicone gel.

近年、家電、産業システム、電鉄などの用途に用いられるパワー半導体装置において、半導体素子の高耐圧化、電流容量の増大化が進んでおり、パワー半導体装置内部のより高度な絶縁性の確保とともに、パワー半導体装置の長寿命化による信頼性の向上が要求されている。   In recent years, in power semiconductor devices used for applications such as home appliances, industrial systems, electric railways, etc., with increasing breakdown voltage of semiconductor elements and increasing current capacity, along with ensuring higher insulation inside the power semiconductor device, There is a demand for improved reliability by extending the life of power semiconductor devices.

これらの絶縁性、信頼性向上（長寿命化）の技術として、半導体素子と金属ワイヤの接合部と、半導体素子等が接合される絶縁基板上の金属回路箔の側面部とに、電気絶縁性樹脂を被覆し、その電気絶縁性樹脂の上をシリコーンゲルで被覆する構造が提案されている（特許文献１等参照）。具体的に、電気絶縁性樹脂としては、シリコーンゲルより膨張係数が小さく、ヤング率が大きく、絶縁耐量が高いポリアミド系又はポリアミドイミド系樹脂を用いる。これによりパワー半導体装置内部の金属ワイヤと半導体素子間の接合の長寿命化、及び、絶縁基板の絶縁耐量を向上させている。   As a technology for improving the insulation and reliability (prolonging the service life), there is electrical insulation between the joint portion of the semiconductor element and the metal wire and the side surface portion of the metal circuit foil on the insulating substrate to which the semiconductor element is joined. A structure in which a resin is coated and the electrically insulating resin is coated with a silicone gel has been proposed (see Patent Document 1). Specifically, as the electrically insulating resin, a polyamide-based or polyamide-imide-based resin having a smaller expansion coefficient than a silicone gel, a larger Young's modulus, and a higher insulation resistance is used. As a result, the life of the junction between the metal wire inside the power semiconductor device and the semiconductor element is increased, and the dielectric strength of the insulating substrate is improved.

特開２００７−１２８３１号公報JP 2007-12831 A

パワー半導体装置の動作時には、半導体素子の電気的スイッチング動作により、半導体素子、及び、半導体素子に接合された金属ワイヤは、スイッチング・オンの際の発熱による昇温とオフの際の降温を繰り返すが、その際、各部材の接合部には熱応力が発生する。しかし、ポリアミドイミド系樹脂によって被覆されていない半導体素子と絶縁基板間の半田接合部は、ポリアミドイミド系樹脂による寿命向上の効果が働いていないため、熱応力によりクラックが入り、熱抵抗が上昇する可能性がある。   During the operation of the power semiconductor device, due to the electrical switching operation of the semiconductor element, the semiconductor element and the metal wire bonded to the semiconductor element repeatedly rise in temperature due to heat generation at the time of switching on and cool down at the time of off. At that time, thermal stress is generated at the joint portion of each member. However, the solder joint between the semiconductor element and the insulating substrate that is not covered with the polyamideimide resin does not have the effect of improving the service life due to the polyamideimide resin, and therefore cracks occur due to thermal stress and the thermal resistance increases. there is a possibility.

そこで、本発明の目的は、半導体素子と絶縁基板間の半田接合を長寿命化できる半導体装置を提供することである。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of extending the life of a solder joint between a semiconductor element and an insulating substrate.

前記目的を達成するために、本発明は、
金属基板の一方の面に接合した複数の絶縁基板と、
前記絶縁基板毎に上面に接合した第１金属回路箔と、
前記第１金属回路箔に半田で下面が接合した半導体素子と、
前記第１金属回路箔から離れて前記絶縁基板毎の上面に接合し、金属ワイヤを介して前記半導体素子の上面に接続する第２金属回路箔と、
前記金属ワイヤと前記半導体素子との接続部を被覆する絶縁性の第１樹脂と、
前記第１金属回路箔と前記第２金属回路箔の側面を被覆する絶縁性の第２樹脂とを有する半導体装置において、
前記第１金属回路箔と、前記半導体素子と、前記金属ワイヤと、前記第２金属回路箔と、前記第１樹脂と、前記第２樹脂を被覆し、前記第１樹脂と前記第２樹脂より硬く、線膨張係数が前記半田と略等しい絶縁性の第３樹脂を有し、
前記第３樹脂が、複数の前記絶縁基板毎に設けられ、互いに離れていることを特徴としている。 In order to achieve the above object, the present invention provides:
A plurality of insulating substrates bonded to one side of the metal substrate;
A first metal circuit foil bonded to the upper surface for each insulating substrate;
A semiconductor element having a lower surface bonded to the first metal circuit foil with solder;
A second metal circuit foil which is bonded to the upper surface of each of the insulating substrates apart from the first metal circuit foil and connected to the upper surface of the semiconductor element via a metal wire;
An insulative first resin that covers a connecting portion between the metal wire and the semiconductor element;
In the semiconductor device having the first metal circuit foil and an insulating second resin that covers a side surface of the second metal circuit foil,
Covering the first metal circuit foil, the semiconductor element, the metal wire, the second metal circuit foil, the first resin, and the second resin, and from the first resin and the second resin A hard, insulating third resin having a linear expansion coefficient substantially equal to that of the solder;
The third resin is provided for each of the plurality of insulating substrates and is separated from each other.

本発明によれば、半導体素子と絶縁基板間の半田接合を長寿命化できる半導体装置を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can prolong the lifetime of the solder joint between a semiconductor element and an insulated substrate can be provided.

本発明の実施形態に係る半導体装置を上から透視した平面図である。It is the top view which saw through the semiconductor device concerning the embodiment of the present invention from the top. 図１のＡ−Ａ方向の矢視断面図である。It is arrow sectional drawing of the AA direction of FIG. 図１のＢ−Ｂ方向の矢視断面図である。It is arrow sectional drawing of the BB direction of FIG.

次に、本発明の実施形態について、適宜図面を参照しながら詳細に説明する。なお、各図において、共通する部分には同一の符号を付し重複した説明を省略している。   Next, embodiments of the present invention will be described in detail with reference to the drawings as appropriate. In each figure, common portions are denoted by the same reference numerals, and redundant description is omitted.

図１に、本発明の実施形態に係る半導体装置（パワー半導体装置）１００を上から透視した平面図を示す。図１では、パワー半導体装置１００の一例として、ＩＧＢＴ（Insulated Gate Bipolar Transistor）モジュールを示している。なお、本実施形態では、ＩＧＢＴモジュールを例に説明するが、本発明は、ＩＧＢＴモジュール以外のパワー半導体装置、例えば、パワーＭＯＳＦＥＴ（Metal-Oxide Semiconductor Field Effect Transistor）モジュールや、ダイオードモジュールにも適用できるのである。   FIG. 1 shows a plan view of a semiconductor device (power semiconductor device) 100 according to an embodiment of the present invention as seen through from above. In FIG. 1, an IGBT (Insulated Gate Bipolar Transistor) module is shown as an example of the power semiconductor device 100. In the present embodiment, an IGBT module will be described as an example, but the present invention can also be applied to a power semiconductor device other than the IGBT module, for example, a power MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) module or a diode module. It is.

パワー半導体装置１００の最外周には、樹脂ケース１０が設けられている。樹脂ケース１０は、ベース（金属基板）８に固定されている。ベース（金属基板）８を土台として、ベース（金属基板）８の上にパワー半導体装置１００が構築されている。ベース（金属基板）８には、アルミニウムと炭化珪素（Al-SiC）や、銅とモリブデン（Cu-Mo）からなる複合材を用いることができる。ベース（金属基板）８の上には、電流定格を増大させるための複数の（図１では２つの）分割板（分割壁）２０が、互いに離れて設けられている。分割板（分割壁）２０同士の間には、シリコーンゲル系樹脂（第４樹脂）１９が設けられている。   A resin case 10 is provided on the outermost periphery of the power semiconductor device 100. The resin case 10 is fixed to a base (metal substrate) 8. The power semiconductor device 100 is constructed on the base (metal substrate) 8 using the base (metal substrate) 8 as a base. For the base (metal substrate) 8, a composite material made of aluminum and silicon carbide (Al—SiC) or copper and molybdenum (Cu—Mo) can be used. On the base (metal substrate) 8, a plurality of (two in FIG. 1) dividing plates (dividing walls) 20 for increasing the current rating are provided apart from each other. A silicone gel resin (fourth resin) 19 is provided between the dividing plates (dividing walls) 20.

個々の分割板（分割壁）２０の内側には、窒化アルミニウム（ＡｌＮ）や窒化シリコン（ＳｉＮ）等のセラミック製の絶縁基板４（絶縁回路基板７）が設けられている。絶縁基板４はベース（金属基板）８に固定されている。分割板（分割壁）２０は、絶縁基板４（絶縁回路基板７）を取り囲んでいる。絶縁基板４上には、複数の金属回路箔５が、設けられている。複数の金属回路箔５は互いに離れている。複数の金属回路箔５は、エミッタ回路箔（第２金属回路箔）５ａ（５）と、ゲート回路箔５ｂ（５）と、コレクタ回路箔（第１金属回路箔）５ｃ（５）とを含んでいる。   Inside each individual dividing plate (dividing wall) 20, an insulating substrate 4 (insulating circuit substrate 7) made of ceramic such as aluminum nitride (AlN) or silicon nitride (SiN) is provided. The insulating substrate 4 is fixed to a base (metal substrate) 8. The dividing plate (dividing wall) 20 surrounds the insulating substrate 4 (insulating circuit substrate 7). A plurality of metal circuit foils 5 are provided on the insulating substrate 4. The plurality of metal circuit foils 5 are separated from each other. The plurality of metal circuit foils 5 include an emitter circuit foil (second metal circuit foil) 5a (5), a gate circuit foil 5b (5), and a collector circuit foil (first metal circuit foil) 5c (5). It is out.

コレクタ回路箔（第１金属回路箔）５ｃ上には、電流定格を増大させるための複数の半導体素子（半導体スイッチング素子）１の下面が、半田１５によって接合されている。また、コレクタ回路箔（第１金属回路箔）５ｃ上には、コレクタ端子（主端子、第１金属端子）１２ｃが、半田１５によって接合されている。複数の半導体素子１には、ＩＧＢＴチップやダイオードチップ等が含まれている。   On the collector circuit foil (first metal circuit foil) 5 c, the lower surfaces of a plurality of semiconductor elements (semiconductor switching elements) 1 for increasing the current rating are joined by solder 15. A collector terminal (main terminal, first metal terminal) 12 c is joined by solder 15 on the collector circuit foil (first metal circuit foil) 5 c. The plurality of semiconductor elements 1 include an IGBT chip, a diode chip, and the like.

エミッタ回路箔（第２金属回路箔）５ａは、複数のアルミワイヤ（金属ワイヤ）３を介して、複数の半導体素子（半導体スイッチング素子）１の上面に接続している。エミッタ回路箔（第２金属回路箔）５ａ上には、エミッタ端子（主端子、第２金属端子）１２ａが、半田１５によって接合されている。ゲート回路箔５ｂは、複数のアルミワイヤ（金属ワイヤ）３を介して、複数の半導体素子（半導体スイッチング素子）１の上面に接続している。コレクタ回路箔（第１金属回路箔）５ｃとエミッタ端子（主端子、第２金属端子）１２ａには、電気抵抗が小さく、熱伝導率が大きいニッケル（Ni）メッキされた無酸素銅や銅合金などを使用することができる。   The emitter circuit foil (second metal circuit foil) 5 a is connected to the upper surfaces of the plurality of semiconductor elements (semiconductor switching elements) 1 via the plurality of aluminum wires (metal wires) 3. On the emitter circuit foil (second metal circuit foil) 5 a, an emitter terminal (main terminal, second metal terminal) 12 a is joined by solder 15. The gate circuit foil 5 b is connected to the upper surfaces of a plurality of semiconductor elements (semiconductor switching elements) 1 via a plurality of aluminum wires (metal wires) 3. The collector circuit foil (first metal circuit foil) 5c and the emitter terminal (main terminal, second metal terminal) 12a are nickel (Ni) plated oxygen-free copper or copper alloy having low electrical resistance and high thermal conductivity. Etc. can be used.

複数のアルミワイヤ（金属ワイヤ）３の、半導体素子１との接続部は、絶縁性であるポリアミドイミド系樹脂（第１樹脂）１７ｃで被覆されている。   Connection portions of the plurality of aluminum wires (metal wires) 3 with the semiconductor element 1 are covered with an insulating polyamideimide resin (first resin) 17c.

複数の金属回路箔５（エミッタ回路箔（第２金属回路箔）５ａと、ゲート回路箔５ｂと、コレクタ回路箔（第１金属回路箔）５ｃ）の側面を被覆するように、金属回路箔５の縁に沿った絶縁基板４上に、絶縁性であるポリアミドイミド系樹脂（第２樹脂）１７ａ、１７ｂが設けられている。ポリアミドイミド系樹脂（第２樹脂）１７ａは、絶縁基板４の外周部に沿って設けられ、分割板（分割壁）２０に対向する複数の金属回路箔５の側面を被覆している。ポリアミドイミド系樹脂（第２樹脂）１７ｂは、複数の金属回路箔５の側面が互いに対向している、その側面間の絶縁基板４上に設けられている。なお、ポリアミドイミド系樹脂（第２樹脂）１７ａ、１７ｂと、ポリアミドイミド系樹脂（第１樹脂）１７ｃには、ポリアミドイミド系樹脂に替えて、ポリアミド系樹脂を用いてもよい。   A plurality of metal circuit foils 5 (emitter circuit foil (second metal circuit foil) 5a, gate circuit foil 5b, collector circuit foil (first metal circuit foil) 5c) are coated so as to cover the side surfaces thereof. Insulating polyamideimide resins (second resins) 17a and 17b are provided on the insulating substrate 4 along the edges. The polyamideimide resin (second resin) 17 a is provided along the outer peripheral portion of the insulating substrate 4 and covers the side surfaces of the plurality of metal circuit foils 5 facing the dividing plate (dividing wall) 20. The polyamideimide resin (second resin) 17b is provided on the insulating substrate 4 between the side surfaces of the plurality of metal circuit foils 5 facing each other. The polyamide-imide resins (second resins) 17a and 17b and the polyamide-imide resin (first resin) 17c may be polyamide resins instead of the polyamide-imide resins.

絶縁基板４の上方には、複数の金属回路箔５の上方や、ポリアミドイミド系樹脂（第１樹脂）１７ｃの上方や、ポリアミドイミド系樹脂（第２樹脂）１７ａ、１７ｂの上方や、半導体素子１の上方や、半田１５の上方や、アルミワイヤ（金属ワイヤ）３の上方を含めて、分割板（分割壁）２０で囲まれた領域から溢れない程度に、エポキシ系樹脂（第３樹脂）１８が充填されている。   Above the insulating substrate 4, above the plurality of metal circuit foils 5, above the polyamideimide resin (first resin) 17c, above the polyamideimide resins (second resins) 17a and 17b, and semiconductor elements Epoxy resin (third resin) to the extent that it does not overflow from the area surrounded by the dividing plate (dividing wall) 20 including the area above 1, the area above the solder 15, and the area above the aluminum wire (metal wire) 3. 18 is filled.

図２に、図１のＡ−Ａ方向の矢視断面図を示す。パワー半導体装置１００は、ベース（金属基板）８の上面に、電流定格を増大させるために複数（図２では２つ）の絶縁回路基板７が設けられている。絶縁回路基板７は、３層構造をしており、絶縁基板４の上面と下面にそれぞれ金属回路箔５と金属回路箔６が設けられている。金属回路箔５と金属回路箔６は、絶縁基板４に接合している。金属回路箔６は、基板下半田９によって、ベース（金属基板）８の上面に接合されている。これにより、絶縁基板４はベース（金属基板）８の上面に接合している。   FIG. 2 is a cross-sectional view taken along the line AA in FIG. In the power semiconductor device 100, a plurality (two in FIG. 2) of insulating circuit substrates 7 are provided on the upper surface of a base (metal substrate) 8 in order to increase the current rating. The insulating circuit board 7 has a three-layer structure, and a metal circuit foil 5 and a metal circuit foil 6 are provided on the upper surface and the lower surface of the insulating substrate 4, respectively. The metal circuit foil 5 and the metal circuit foil 6 are bonded to the insulating substrate 4. The metal circuit foil 6 is bonded to the upper surface of the base (metal substrate) 8 by a substrate lower solder 9. Thereby, the insulating substrate 4 is bonded to the upper surface of the base (metal substrate) 8.

絶縁基板４の上面には、金属回路箔５のエミッタ回路箔（第２金属回路箔）５ａとコレクタ回路箔（第１金属回路箔）５ｃが、接合されている。エミッタ回路箔（第２金属回路箔）５ａとコレクタ回路箔（第１金属回路箔）５ｃとは、離れている。   On the upper surface of the insulating substrate 4, an emitter circuit foil (second metal circuit foil) 5 a and a collector circuit foil (first metal circuit foil) 5 c of the metal circuit foil 5 are joined. The emitter circuit foil (second metal circuit foil) 5a and the collector circuit foil (first metal circuit foil) 5c are separated from each other.

コレクタ回路箔（第１金属回路箔）５ｃには、半導体素子１の下面が、チップ下半田２によって接合されている。また、コレクタ回路箔（第１金属回路箔）５ｃには、コレクタ端子（主端子、第１金属端子）１２ｃが、半田１５によって接合されている。コレクタ端子（主端子、第１金属端子）１２ｃは、パワー半導体装置１００の外部に引き出されている。   The lower surface of the semiconductor element 1 is bonded to the collector circuit foil (first metal circuit foil) 5 c by the under-chip solder 2. A collector terminal (main terminal, first metal terminal) 12 c is joined to the collector circuit foil (first metal circuit foil) 5 c by solder 15. The collector terminal (main terminal, first metal terminal) 12 c is drawn out of the power semiconductor device 100.

エミッタ回路箔（第２金属回路箔）５ａには、エミッタ端子（主端子、第２金属端子）１２ａが、半田１５によって接合されている。エミッタ端子（主端子、第２金属端子）１２ａは、パワー半導体装置１００の外部に引き出されている。   An emitter terminal (main terminal, second metal terminal) 12 a is joined to the emitter circuit foil (second metal circuit foil) 5 a by solder 15. The emitter terminal (main terminal, second metal terminal) 12 a is drawn out of the power semiconductor device 100.

アルミワイヤ（金属ワイヤ）３は、エミッタ回路箔（第２金属回路箔）５ａの上面と、半導体素子１の上面とを接続している。エミッタ回路箔（第２金属回路箔）５ａの上面と、半導体素子１の上面とは、アルミワイヤ（金属ワイヤ）３を介して接続している。アルミワイヤ（金属ワイヤ）３と半導体素子１との接続部は、絶縁性であるポリアミドイミド系樹脂（第１樹脂）１７ｃによって、被覆されている。ポリアミドイミド系樹脂（第１樹脂）１７ｃの厚さは、２０〜２００μｍでよい。半導体素子１とアルミワイヤ（金属ワイヤ）３との接合部に働く応力を緩和し、接合部でのせん断強度を向上させることができる。なお、図２では、ポリアミドイミド系樹脂（第１樹脂）１７ｃは、半導体素子１の上面の一部（接合部）に設けているが、これに限らず、半導体素子１の上面の全面に設けてもよい。   The aluminum wire (metal wire) 3 connects the upper surface of the emitter circuit foil (second metal circuit foil) 5 a and the upper surface of the semiconductor element 1. The upper surface of the emitter circuit foil (second metal circuit foil) 5 a and the upper surface of the semiconductor element 1 are connected via an aluminum wire (metal wire) 3. A connecting portion between the aluminum wire (metal wire) 3 and the semiconductor element 1 is covered with an insulating polyamideimide resin (first resin) 17c. The thickness of the polyamideimide resin (first resin) 17c may be 20 to 200 μm. The stress acting on the junction between the semiconductor element 1 and the aluminum wire (metal wire) 3 can be relaxed, and the shear strength at the junction can be improved. In FIG. 2, the polyamideimide resin (first resin) 17 c is provided on a part (joint part) of the upper surface of the semiconductor element 1, but is not limited thereto, and is provided on the entire upper surface of the semiconductor element 1. May be.

エミッタ回路箔（第２金属回路箔）５ａとコレクタ回路箔（第１金属回路箔）５ｃの側面は、絶縁性であるポリアミドイミド系樹脂（第２樹脂）１７ａ、１７ｂによって被覆されている。この被覆により、絶縁基板４の絶縁耐量を向上させることができる。   Side surfaces of the emitter circuit foil (second metal circuit foil) 5a and the collector circuit foil (first metal circuit foil) 5c are covered with polyamideimide resins (second resins) 17a and 17b which are insulating. With this coating, the dielectric strength of the insulating substrate 4 can be improved.

複数の絶縁基板４毎の周囲には、分割板（分割壁）２０が設けられている。分割板（分割壁）２０は、接着剤１１によって、ベース（金属基板）８に固定されている。分割板（分割壁）２０の上面の高さは、半導体素子１の上面の高さより高く、エミッタ端子（主端子、第２金属端子）１２ａとコレクタ端子（主端子、第１金属端子）１２ｃの半田１５との接合部の高さより高くなっている。また、分割板（分割壁）２０の上面の高さは、アルミワイヤ（金属ワイヤ）３の最も高い場所より高くなっている。   A dividing plate (dividing wall) 20 is provided around each of the plurality of insulating substrates 4. The dividing plate (dividing wall) 20 is fixed to the base (metal substrate) 8 with an adhesive 11. The height of the upper surface of the dividing plate (dividing wall) 20 is higher than the height of the upper surface of the semiconductor element 1, and the emitter terminal (main terminal, second metal terminal) 12a and the collector terminal (main terminal, first metal terminal) 12c. The height of the joint with the solder 15 is higher. Further, the height of the upper surface of the dividing plate (dividing wall) 20 is higher than the highest place of the aluminum wire (metal wire) 3.

分割板（分割壁）２０の内側には、エポキシ系樹脂（第３樹脂）１８が充填されている。エポキシ系樹脂（第３樹脂）１８は、絶縁基板４（絶縁回路基板７）の上方の全領域を被覆するように、分割板（分割壁）２０で囲まれた領域内に注入されている。エポキシ系樹脂（第３樹脂）１８は、複数の分割板（分割壁）２０毎、すなわち、複数の絶縁基板４毎に設けられ、複数のエポキシ系樹脂（第３樹脂）１８は、互いに離れている。分割板（分割壁）２０の上面の高さは、エポキシ系樹脂（第３樹脂）１８の上面の高さより高くなっている。   An epoxy resin (third resin) 18 is filled inside the dividing plate (dividing wall) 20. The epoxy resin (third resin) 18 is injected into a region surrounded by the dividing plate (dividing wall) 20 so as to cover the entire region above the insulating substrate 4 (insulating circuit substrate 7). The epoxy resin (third resin) 18 is provided for each of a plurality of dividing plates (dividing walls) 20, that is, for each of the plurality of insulating substrates 4, and the plurality of epoxy resins (third resin) 18 are separated from each other. Yes. The height of the upper surface of the dividing plate (dividing wall) 20 is higher than the height of the upper surface of the epoxy resin (third resin) 18.

エポキシ系樹脂（第３樹脂）１８は、絶縁基板４と、金属回路箔５（エミッタ回路箔（第２金属回路箔）５ａ、ゲート回路箔５ｂ（図示省略）、コレクタ回路箔（第１金属回路箔）５ｃ）と、ポリアミドイミド系樹脂（第２樹脂）１７ａ、１７ｂと、ポリアミドイミド系樹脂（第１樹脂）１７ｃと、半導体素子１と、チップ下半田２と、エミッタ端子（主端子、第２金属端子）１２ａとコレクタ端子（主端子、第１金属端子）１２ｃの半田１５による接合部と、アルミワイヤ（金属ワイヤ）３とを、被覆し封止している。エポキシ系樹脂（第３樹脂）１８の上面の高さは、アルミワイヤ（金属ワイヤ）３が形成するループの高さよりも高く、分割板（分割壁）２０の上面の高さより低くなっている。   The epoxy resin (third resin) 18 includes an insulating substrate 4, a metal circuit foil 5 (emitter circuit foil (second metal circuit foil) 5 a, a gate circuit foil 5 b (not shown), a collector circuit foil (first metal circuit). Foil) 5c), polyamideimide resin (second resin) 17a, 17b, polyamideimide resin (first resin) 17c, semiconductor element 1, under-chip solder 2, emitter terminal (main terminal, second resin) (2 metal terminal) 12a and collector terminal (main terminal, first metal terminal) 12c are joined by solder 15 and aluminum wire (metal wire) 3 are covered and sealed. The height of the upper surface of the epoxy resin (third resin) 18 is higher than the height of the loop formed by the aluminum wire (metal wire) 3 and is lower than the height of the upper surface of the dividing plate (dividing wall) 20.

エポキシ系樹脂（第３樹脂）１８は、ポリアミドイミド系樹脂（第２樹脂）１７ａ、１７ｂと、ポリアミドイミド系樹脂（第１樹脂）１７ｃより硬い。また、エポキシ系樹脂（第３樹脂）１８の線膨張係数は、チップ下半田２や半田１５の線膨張係数と略等しくなっている。   The epoxy resin (third resin) 18 is harder than the polyamideimide resin (second resin) 17a, 17b and the polyamideimide resin (first resin) 17c. Further, the linear expansion coefficient of the epoxy resin (third resin) 18 is substantially equal to the linear expansion coefficient of the under-chip solder 2 and the solder 15.

ポリアミドイミド系樹脂（第１樹脂）１７ｃによって、アルミワイヤ（金属ワイヤ）３の接合部は長寿命化し、ポリアミドイミド系樹脂（第２樹脂）１７ａ、１７ｂによって、絶縁基板４における絶縁耐量は向上している。さらに、エポキシ系樹脂（第３樹脂）１８によって、絶縁基板４（絶縁回路基板７）の上方の全領域を被覆することによって、半導体素子１、金属回路箔５、金属端子１２ａ、１２ｃを、エポキシ系樹脂（第３樹脂）１８によって拘束し、チップ下半田２や半田１５に働く熱応力を緩和している。チップ下半田２や半田１５には、熱応力による膨張、収縮によりクラックが入るのを抑制することができ、半田接合を長寿命化できるので、放熱性、及び電気伝導性の劣化を抑えることができる。   The bonded portion of the aluminum wire (metal wire) 3 has a longer life due to the polyamideimide resin (first resin) 17c, and the insulation resistance in the insulating substrate 4 is improved by the polyamideimide resin (second resin) 17a, 17b. ing. Further, by covering the entire area above the insulating substrate 4 (insulating circuit substrate 7) with an epoxy resin (third resin) 18, the semiconductor element 1, the metal circuit foil 5, and the metal terminals 12a and 12c are bonded to the epoxy. Restrained by the system resin (third resin) 18, the thermal stress acting on the under-chip solder 2 and the solder 15 is relaxed. The under-chip solder 2 and the solder 15 can be prevented from cracking due to expansion and contraction due to thermal stress, and the life of the solder joint can be extended, so that deterioration of heat dissipation and electrical conductivity can be suppressed. it can.

また、エポキシ系樹脂（第３樹脂）１８によって、アルミワイヤ（金属ワイヤ）３のループ全体を被覆することで、アルミワイヤ（金属ワイヤ）３全体を強力に拘束し、アルミワイヤ（金属ワイヤ）３の接合部の寿命を更に向上することができる。   Further, the entire loop of the aluminum wire (metal wire) 3 is covered with the epoxy resin (third resin) 18, so that the entire aluminum wire (metal wire) 3 is strongly restrained, and the aluminum wire (metal wire) 3. The life of the joint can be further improved.

更に、エポキシ系樹脂（第３樹脂）１８は、パワー半導体装置１００内部に一様に注入するのではなく、分割板（分割壁）２０を用いて絶縁回路基板７上のみを被覆し、隣接する絶縁回路基板７の間には設けていない。これにより、エポキシ系樹脂（第３樹脂）１８内の歪（内部応力）を緩和し、絶縁回路基板７とエポキシ系樹脂（第３樹脂）１８間の界面における応力を小さくすることができる。   Further, the epoxy resin (third resin) 18 is not uniformly injected into the power semiconductor device 100 but covers only the insulating circuit board 7 using the dividing plate (dividing wall) 20 and is adjacent thereto. It is not provided between the insulating circuit boards 7. Thereby, the strain (internal stress) in the epoxy resin (third resin) 18 can be relaxed, and the stress at the interface between the insulating circuit board 7 and the epoxy resin (third resin) 18 can be reduced.

複数のエポキシ系樹脂（第３樹脂）１８の間、すなわち、複数の分割板（分割壁）２０の間のベース（金属基板）８には、シリコーンゲル系樹脂（第４樹脂）１９が設けられている。シリコーンゲル系樹脂（第４樹脂）１９は、分割板（分割壁）２０の周囲に配置されている。シリコーンゲル系樹脂（第４樹脂）１９は、エポキシ系樹脂（第３樹脂）１８の上と、分割板（分割壁）２０の上にも設けられている。   A silicone gel resin (fourth resin) 19 is provided on the base (metal substrate) 8 between the plurality of epoxy resins (third resin) 18, that is, between the plurality of divided plates (dividing walls) 20. ing. The silicone gel resin (fourth resin) 19 is arranged around the dividing plate (dividing wall) 20. The silicone gel resin (fourth resin) 19 is also provided on the epoxy resin (third resin) 18 and on the dividing plate (dividing wall) 20.

樹脂ケース１０は、ベース（金属基板）８の周縁部に沿って設けられている。樹脂ケース１０は、接着剤２３によって、ベース（金属基板）８に固定されている。シリコーンゲル系樹脂（第４樹脂）１９の上面の高さは、エポキシ系樹脂（第３樹脂）１８の上面の高さや、分割板（分割壁）２０の上面の高さより高く、樹脂ケース１０の上面の高さより低くなっている。シリコーンゲル系樹脂（第４樹脂）１９は、樹脂ケース１０で仕切られた領域に充填されている。   The resin case 10 is provided along the peripheral edge of the base (metal substrate) 8. The resin case 10 is fixed to the base (metal substrate) 8 with an adhesive 23. The height of the upper surface of the silicone gel resin (fourth resin) 19 is higher than the height of the upper surface of the epoxy resin (third resin) 18 and the height of the upper surface of the dividing plate (dividing wall) 20. It is lower than the height of the top surface. The silicone gel resin (fourth resin) 19 is filled in a region partitioned by the resin case 10.

シリコーンゲル系樹脂（第４樹脂）１９を、エミッタ端子（主端子、第２金属端子）１２ａとコレクタ端子（主端子、第１金属端子）１２ｃは、貫通している。シリコーンゲル系樹脂（第４樹脂）１９中には、エミッタ端子（主端子、第２金属端子）１２ａとコレクタ端子（主端子、第１金属端子）１２ｃの応力緩和ベンド部２２が埋め込まれている。応力緩和ベンド部２２によれば、応力緩和ベンド部２２の上側の金属端子１２ａ、１２ｃで生じた内部応力を、応力緩和ベンド部２２の下側の金属端子１２ａ、１２ｃに緩和して伝達したり、遮断したりすることができる。シリコーンゲル系樹脂（第４樹脂）１９は、エポキシ系樹脂（第３樹脂）１８より柔らかくなっている。   Through the silicone gel resin (fourth resin) 19, the emitter terminal (main terminal, second metal terminal) 12a and the collector terminal (main terminal, first metal terminal) 12c penetrate. In the silicone gel resin (fourth resin) 19, the stress relaxation bend portion 22 of the emitter terminal (main terminal, second metal terminal) 12a and the collector terminal (main terminal, first metal terminal) 12c is embedded. . According to the stress relaxation bend part 22, internal stress generated in the metal terminals 12 a and 12 c on the upper side of the stress relaxation bend part 22 is relaxed and transmitted to the metal terminals 12 a and 12 c on the lower side of the stress relaxation bend part 22. Can be shut off. The silicone gel resin (fourth resin) 19 is softer than the epoxy resin (third resin) 18.

シリコーンゲル系樹脂（第４樹脂）１９の上方には、空間２１を空けて、樹脂ケースフタ１３が設けられている。樹脂ケースフタ１３は、接着剤１６で、樹脂ケース１０の上部に固定されている。樹脂ケースフタ１３を、エミッタ端子（主端子、第２金属端子）１２ａとコレクタ端子（主端子、第１金属端子）１２ｃは、貫通し、外部に引き出されている。エミッタ端子（主端子、第２金属端子）１２ａとコレクタ端子（主端子、第１金属端子）１２ｃは、接着剤１６で固定された端子ブロック１４によって、樹脂ケースフタ１３に固定されている。なお、製造方法としては、接着剤１６、２３で、樹脂ケース１０と樹脂ケースフタ１３を固定した後に、シリコーンゲル系樹脂（第４樹脂）１９を、空間２１が残るように、パワー半導体装置１００の内部に注入し硬化させている。   Above the silicone gel resin (fourth resin) 19, a resin case lid 13 is provided with a space 21 therebetween. The resin case lid 13 is fixed to the upper part of the resin case 10 with an adhesive 16. An emitter terminal (main terminal, second metal terminal) 12a and a collector terminal (main terminal, first metal terminal) 12c penetrate through the resin case cover 13 and are drawn out to the outside. An emitter terminal (main terminal, second metal terminal) 12 a and a collector terminal (main terminal, first metal terminal) 12 c are fixed to the resin case cover 13 by a terminal block 14 fixed with an adhesive 16. As a manufacturing method, after fixing the resin case 10 and the resin case lid 13 with the adhesives 16 and 23, the silicone gel resin (fourth resin) 19 is removed from the power semiconductor device 100 so that the space 21 remains. It is injected and cured inside.

表１に、本発明の実施形態に係るパワー半導体装置１００で使用したポリアミドイミド系樹脂（第２樹脂、第１樹脂）１７ａ、１７ｂ、１７ｃ、エポキシ系樹脂（第３樹脂）１８、シリコーンゲル系樹脂（第４樹脂）１９の物性値を示す。

Figure 2012015222
Table 1 shows polyamideimide resins (second resin, first resin) 17a, 17b, 17c, epoxy resin (third resin) 18, and silicone gel used in the power semiconductor device 100 according to the embodiment of the present invention. The physical property values of the resin (fourth resin) 19 are shown.
Figure 2012015222

エポキシ系樹脂（第３樹脂）１８は、チップ下半田２と半田１５の接合部における半田のクラック発生を抑えるために、線膨張係数が半田の線膨張係数(２１ｐｐｍ／℃)、及びアルミニウムの線膨張係数(２４ｐｐｍ／℃)とほぼ等しい、２４ｐｐｍ／℃に設定しているが、２０〜３０ｐｐｍ／℃の範囲であれば、本実施形態と同様の効果が得られる。また、半導体素子１と金属回路箔５の間と、金属回路箔５と金属端子１２ａ、１２ｃの間の線膨張係数差による歪を押さえ込むために、ヤング率（硬さ）を５ＧＰａに設定しているが、５〜１０ＧＰａの範囲であれば、本実施形態と同様の効果が得られる。また、エポキシ系樹脂（第３樹脂）１８の絶縁耐量としては、高電界の発生する部位を直接被覆することがないため、３０ｋＶ／ｍｍ程度に設定している。そして、本実施形態と同様の効果を得るためには、その絶縁耐量を１０〜３０ｋＶ／ｍｍの範囲に設定すればよい。   The epoxy-based resin (third resin) 18 has a linear expansion coefficient of the solder linear expansion coefficient (21 ppm / ° C.) and an aluminum wire in order to suppress the occurrence of solder cracks at the joint between the under-chip solder 2 and the solder 15. Although it is set to 24 ppm / ° C., which is substantially equal to the expansion coefficient (24 ppm / ° C.), the same effect as this embodiment can be obtained if it is in the range of 20 to 30 ppm / ° C. Further, in order to suppress the distortion caused by the difference in linear expansion coefficient between the semiconductor element 1 and the metal circuit foil 5 and between the metal circuit foil 5 and the metal terminals 12a and 12c, the Young's modulus (hardness) is set to 5 GPa. However, if it is in the range of 5 to 10 GPa, the same effect as the present embodiment can be obtained. The dielectric strength of the epoxy resin (third resin) 18 is set to about 30 kV / mm because it does not directly cover a portion where a high electric field is generated. And in order to acquire the effect similar to this embodiment, what is necessary is just to set the dielectric strength to the range of 10-30 kV / mm.

ポリアミドイミド系樹脂（第２樹脂、第１樹脂）１７ａ、１７ｂ、１７ｃのヤング率は、半導体素子１とアルミワイヤ（金属ワイヤ）３との線膨張係数差による歪を抑制するために、３ＧＰａに設定しているが、１．５〜５ＧＰａの範囲であれば、本実施形態と同様の効果が得られる。また、ポリアミドイミド系樹脂（第２樹脂、第１樹脂）１７ａ、１７ｂ、１７ｃの線膨張係数は、半導体素子１やアルミワイヤ（金属ワイヤ）３の線膨張係数に近づけるため、ポリアミドイミド系樹脂としては低い５０ｐｐｍ／℃に設定している。なお、本実施形態と同様の効果を得るためには、線膨張係数を５０〜６０ｐｐｍ／℃の範囲に設定すればよい。また、ポリアミドイミド系樹脂（第２樹脂、第１樹脂）１７ａ、１７ｂ、１７ｃは、半導体素子１とアルミワイヤ（金属ワイヤ）３との接合部や、絶縁回路基板７の沿面及び隣り合った金属回路箔５の間隙といった、電界集中の発生しやすい部位を被覆するため、その絶縁耐量は２３０ｋＶ／ｍｍに設定している。そして、本実施形態と同様の効果を得るためには、その絶縁耐量を１００ｋＶ／ｍｍ以上に設定すればよい。   The Young's modulus of the polyamideimide resin (second resin, first resin) 17a, 17b, 17c is 3 GPa in order to suppress distortion due to the difference in linear expansion coefficient between the semiconductor element 1 and the aluminum wire (metal wire) 3. Although set, if it is in the range of 1.5 to 5 GPa, the same effect as this embodiment can be obtained. Further, since the linear expansion coefficients of the polyamideimide resins (second resin, first resin) 17a, 17b, and 17c are close to the linear expansion coefficients of the semiconductor element 1 and the aluminum wire (metal wire) 3, the polyamideimide resin is used. Is set to a low 50 ppm / ° C. In addition, what is necessary is just to set a linear expansion coefficient in the range of 50-60 ppm / degrees C in order to acquire the effect similar to this embodiment. Polyamideimide resins (second resin, first resin) 17a, 17b, and 17c are metal parts adjacent to the junction between the semiconductor element 1 and the aluminum wire (metal wire) 3, the creeping surface of the insulating circuit board 7, and the adjacent metal. In order to cover a portion where electric field concentration is likely to occur, such as a gap between the circuit foils 5, the dielectric strength is set to 230 kV / mm. And in order to acquire the effect similar to this embodiment, what is necessary is just to set the dielectric strength to 100 kV / mm or more.

シリコーンゲル系樹脂（第４樹脂）１９は、エポキシ系樹脂（第３樹脂）１８との界面における歪を小さくするため、線膨張係数は３００ｐｐｍ／℃、ヤング率は０．００４ＭＰａに設定している。そして、本実施形態と同様の効果を得るためには、線膨張係数を２００〜４００ｐｐｍ／℃の範囲に、ヤング率を１ＭＰａ以下の範囲に設定すればよい。また、シリコーンゲル系樹脂１９の絶縁耐量としては、高電界の発生する部位を直接被覆することがないため、１５ｋＶ／ｍｍ程度に設定している。そして、本実施形態と同様の効果を得るためには、その絶縁耐量を１０〜３０ｋＶ／ｍｍの範囲に設定すればよい。   The silicone gel resin (fourth resin) 19 is set to have a linear expansion coefficient of 300 ppm / ° C. and a Young's modulus of 0.004 MPa in order to reduce strain at the interface with the epoxy resin (third resin) 18. . And in order to acquire the effect similar to this embodiment, what is necessary is just to set a linear expansion coefficient in the range of 200-400 ppm / degrees C, and a Young's modulus in the range below 1 MPa. In addition, the dielectric strength of the silicone gel resin 19 is set to about 15 kV / mm because it does not directly cover a portion where a high electric field is generated. And in order to acquire the effect similar to this embodiment, what is necessary is just to set the dielectric strength to the range of 10-30 kV / mm.

図３に、図１のＢ−Ｂ方向の矢視断面図を示す。アルミワイヤ（金属ワイヤ）３を覆うようにエポキシ系樹脂（第３樹脂）１８を塗布し封止すると、アルミワイヤ（金属ワイヤ）３が形成するワイヤループの内側（下側）と外側（上側）でエポキシ系樹脂１８の厚みが異なった場合、ワイヤループの内側と外側でエポキシ系樹脂１８の歪に差が生じるためアルミワイヤ３にループの外向き、或いは内向きの応力が加わり、エポキシ系樹脂１８とアルミワイヤ３との界面で剥離破壊や、アルミワイヤ３と金属回路箔５の接合部での剪断などを引き起こす可能性がある。よって、エポキシ系樹脂１８の厚さ（塗布量）としては、図３に示すように金属回路箔５の表面からエポキシ系樹脂１８の表面までの直線距離が、アルミワイヤ３のループ高さｔに対して２倍（２ｔ）となるように調節している。これにより、エポキシ系樹脂１８からアルミワイヤ３の外側と内側にかかる応力を等しくし、エポキシ系樹脂１８の応力に起因した破壊を防止できる。   FIG. 3 shows a cross-sectional view in the direction of arrows BB in FIG. When an epoxy resin (third resin) 18 is applied and sealed so as to cover the aluminum wire (metal wire) 3, the inner side (lower side) and the outer side (upper side) of the wire loop formed by the aluminum wire (metal wire) 3 When the epoxy resin 18 has a different thickness, a difference in the strain of the epoxy resin 18 occurs between the inside and the outside of the wire loop, so that the outward or inward stress of the loop is applied to the aluminum wire 3, and the epoxy resin There is a possibility of causing delamination breakage at the interface between the aluminum wire 3 and the aluminum wire 3 and shearing at the joint between the aluminum wire 3 and the metal circuit foil 5. Therefore, as the thickness (coating amount) of the epoxy resin 18, the linear distance from the surface of the metal circuit foil 5 to the surface of the epoxy resin 18 is the loop height t of the aluminum wire 3 as shown in FIG. On the other hand, it is adjusted to be twice (2t). Thereby, the stress applied to the outer side and the inner side of the aluminum wire 3 from the epoxy resin 18 can be made equal, and breakage due to the stress of the epoxy resin 18 can be prevented.

１ 半導体素子（半導体スイッチング素子）
２ チップ下半田
３ アルミワイヤ（金属ワイヤ）
４ （セラミック製）絶縁基板
５、６ 金属回路箔
５ａ エミッタ回路箔（第２金属回路箔）
５ｂ ゲート回路箔
５ｃ コレクタ回路箔（第１金属回路箔）
７ 絶縁回路基板
８ ベース（金属基板）
９ 基板下半田
１０ 樹脂ケース
１１、１６、２３ 接着剤
１２ａ エミッタ端子（主端子、第２金属端子）
１２ｃ コレクタ端子（主端子、第１金属端子）
１３ 樹脂ケースフタ
１４ 端子ブロック
１５ （主端子）半田
１７ａ ポリアミドイミド系樹脂（第２樹脂）
１７ｂ ポリアミドイミド系樹脂（第２樹脂）
１７ｃ ポリアミドイミド系樹脂（第１樹脂）
１８ エポキシ系樹脂（第３樹脂）
１９ シリコーンゲル系樹脂（第４樹脂）
２０ 分割板（分割壁）
２１ モジュール内の空間
２２ 応力緩和ベンド部
１００ パワー半導体装置（半導体装置） 1 Semiconductor element (semiconductor switching element)
2 Solder under chip 3 Aluminum wire (metal wire)
4 (Ceramic) insulating substrate 5, 6 Metal circuit foil 5a Emitter circuit foil (second metal circuit foil)
5b Gate circuit foil 5c Collector circuit foil (first metal circuit foil)
7 Insulated circuit board 8 Base (metal board)
9 Substrate solder 10 Resin case 11, 16, 23 Adhesive 12a Emitter terminal (main terminal, second metal terminal)
12c Collector terminal (main terminal, first metal terminal)
13 Resin case cover 14 Terminal block 15 (Main terminal) Solder 17a Polyamideimide resin (second resin)
17b Polyamideimide resin (second resin)
17c Polyamideimide resin (first resin)
18 Epoxy resin (third resin)
19 Silicone gel resin (4th resin)
20 Dividing plate (dividing wall)
21 Space in Module 22 Stress Relieving Bend 100 Power Semiconductor Device (Semiconductor Device)

Claims (9)

金属基板の一方の面に接合した複数の絶縁基板と、
前記絶縁基板毎に上面に接合した第１金属回路箔と、
前記第１金属回路箔に半田で下面が接合した半導体素子と、
前記第１金属回路箔から離れて前記絶縁基板毎の上面に接合し、金属ワイヤを介して前記半導体素子の上面に接続する第２金属回路箔と、
前記金属ワイヤと前記半導体素子との接続部を被覆する絶縁性の第１樹脂と、
前記第１金属回路箔と前記第２金属回路箔の側面を被覆する絶縁性の第２樹脂とを有する半導体装置において、
前記第１金属回路箔と、前記半導体素子と、前記金属ワイヤと、前記第２金属回路箔と、前記第１樹脂と、前記第２樹脂を被覆し、前記第１樹脂と前記第２樹脂より硬く、線膨張係数が前記半田と略等しい絶縁性の第３樹脂を有し、
前記第３樹脂が、複数の前記絶縁基板毎に設けられ、互いに離れていることを特徴とする半導体装置。 A plurality of insulating substrates bonded to one side of the metal substrate;
A first metal circuit foil bonded to the upper surface for each insulating substrate;
A semiconductor element having a lower surface bonded to the first metal circuit foil with solder;
A second metal circuit foil which is bonded to the upper surface of each of the insulating substrates apart from the first metal circuit foil and connected to the upper surface of the semiconductor element via a metal wire;
An insulative first resin that covers a connecting portion between the metal wire and the semiconductor element;
In the semiconductor device having the first metal circuit foil and an insulating second resin that covers a side surface of the second metal circuit foil,
Covering the first metal circuit foil, the semiconductor element, the metal wire, the second metal circuit foil, the first resin, and the second resin, and from the first resin and the second resin A hard, insulating third resin having a linear expansion coefficient substantially equal to that of the solder;
The semiconductor device, wherein the third resin is provided for each of the plurality of insulating substrates and is separated from each other. 複数の前記第３樹脂の間に、前記第３樹脂より柔らかい絶縁性の第４樹脂が設けられていることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein an insulating fourth resin that is softer than the third resin is provided between the plurality of third resins. 前記第１金属回路箔に半田で接合し外部に引き出された第１金属端子と、
前記第２金属回路箔に半田で接合し外部に引き出された第２金属端子とを有し、
前記第１金属回路箔と前記第１金属端子との接合部と、前記第２金属回路箔と前記第２金属端子との接合部は、前記第３樹脂で被覆され、
前記第１金属端子と前記第２金属端子にそれぞれ設けられる応力緩和ベンド部は、前記第４樹脂内に埋め込まれていることを特徴とする請求項１又は請求項２に記載の半導体装置。 A first metal terminal joined to the first metal circuit foil with solder and drawn to the outside;
A second metal terminal joined to the second metal circuit foil with solder and drawn to the outside;
The joint between the first metal circuit foil and the first metal terminal, and the joint between the second metal circuit foil and the second metal terminal are covered with the third resin,
3. The semiconductor device according to claim 1, wherein stress relaxation bend portions respectively provided in the first metal terminal and the second metal terminal are embedded in the fourth resin. 4. 複数の前記絶縁基板毎の周囲には、上面の高さが、前記第３樹脂の上面の高さより高い分割壁が設けられていることを特徴とする請求項１乃至請求項３のいずれか１項に記載の半導体装置。   4. The partition wall according to claim 1, wherein a partition wall having a top surface higher than a height of the top surface of the third resin is provided around each of the plurality of insulating substrates. The semiconductor device according to item. 前記第１樹脂と前記第２樹脂のヤング率が、１．５〜５．０ＧＰａであり、
前記第１樹脂と前記第２樹脂の線膨張係数が、５０〜６０ｐｐｍ／℃であり、
前記第１樹脂と前記第２樹脂の絶縁耐量が、１００ｋＶ／ｍｍ以上であることを特徴とする請求項１乃至請求項４のいずれか１項に記載の半導体装置。 The Young's modulus of the first resin and the second resin is 1.5 to 5.0 GPa,
The linear expansion coefficient of the first resin and the second resin is 50 to 60 ppm / ° C;
5. The semiconductor device according to claim 1, wherein an insulation resistance between the first resin and the second resin is 100 kV / mm or more. 6. 前記第１樹脂と前記第２樹脂が、ポリアミド系或いはポリアミドイミド系樹脂であることを特徴とする請求項１乃至請求項５のいずれか１項に記載の半導体装置。   6. The semiconductor device according to claim 1, wherein the first resin and the second resin are polyamide-based or polyamide-imide-based resins. 前記第３樹脂の線膨張係数が、２０〜３０ｐｐｍ／℃であり、
前記第３樹脂のヤング率が、５〜１０ＧＰａであることを特徴とする請求項１乃至請求項６のいずれか１項に記載の半導体装置。 The linear expansion coefficient of the third resin is 20 to 30 ppm / ° C;
The semiconductor device according to any one of claims 1 to 6, wherein the third resin has a Young's modulus of 5 to 10 GPa. 前記第３樹脂が、エポキシ系樹脂であることを特徴とする請求項１乃至請求項７のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the third resin is an epoxy resin. 前記第４樹脂が、シリコーンゲル系樹脂であることを特徴とする請求項１乃至請求項８のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the fourth resin is a silicone gel resin.
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