JP5826443B1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP5826443B1
JP5826443B1 JP2015529366A JP2015529366A JP5826443B1 JP 5826443 B1 JP5826443 B1 JP 5826443B1 JP 2015529366 A JP2015529366 A JP 2015529366A JP 2015529366 A JP2015529366 A JP 2015529366A JP 5826443 B1 JP5826443 B1 JP 5826443B1
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semiconductor device
insulator
electrode
insulating substrate
circuit electrode
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JPWO2015170488A1 (en
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厚 山竹
厚 山竹
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Mitsubishi Electric Corp
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Abstract

本発明は、部分放電を抑制する構造を有する半導体装置において、従来に比べて絶縁信頼性がより高い半導体装置、及びその製造方法を提供する。本発明は、回路電極（２）を接合した絶縁基板（３）と、回路電極に隣接して形成したベース用絶縁物（１０ａ）と、ベース用絶縁物上に形成され上記回路電極と同電位とした導電物（１３）と、導電物における反回路電極側端部（３５）を覆う放電防止用絶縁物（１０ｂ）と、を有する。The present invention provides a semiconductor device having a higher insulation reliability than a conventional semiconductor device having a structure for suppressing partial discharge, and a method for manufacturing the same. The present invention includes an insulating substrate (3) to which a circuit electrode (2) is bonded, a base insulator (10a) formed adjacent to the circuit electrode, and the same potential as the circuit electrode formed on the base insulator. A conductive material (13), and an anti-discharge insulator (10b) covering the opposite end (35) of the conductive material on the side opposite to the circuit electrode.

Description

本発明は、半導体モジュールを用いた半導体装置及びその製造方法に関し、詳しくは部分放電を抑制する構造を有する半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device using a semiconductor module and a manufacturing method thereof, and more particularly to a semiconductor device having a structure for suppressing partial discharge and a manufacturing method thereof.

半導体素子を有する半導体モジュールは電力変換機器等に広く用いられている。また数ｋＶもの高電圧を印加して運転される機種に使用される高電圧半導体モジュールでは、半導体素子を載置する絶縁回路基板における電極端部にて、電界集中による局所放電が発生しやすい。このような局所放電は、当該機器の故障あるいは破壊を引き起こす要因となる。したがって絶縁信頼性を確保するため放電発生を抑制する必要があり、その一例として絶縁物を電極端部に設ける構造が提案されている（例えば特許文献１）。   Semiconductor modules having semiconductor elements are widely used in power conversion equipment and the like. Further, in a high voltage semiconductor module used in a model operated by applying a high voltage of several kV, local discharge due to electric field concentration tends to occur at the electrode end portion of the insulating circuit board on which the semiconductor element is placed. Such a local discharge becomes a factor causing failure or destruction of the device. Therefore, it is necessary to suppress the occurrence of discharge in order to ensure insulation reliability. As an example, a structure in which an insulator is provided at the end of the electrode has been proposed (for example, Patent Document 1).

特開２０００−３４０７１９号公報JP 2000-340719 A

しかしながら電極端部に絶縁物を設ける場合、電極端部と絶縁物との間に隙間、いわゆるボイドが形成されてしまう可能性がある。このようなボイドの存在により、依然として放電発生は防ぎきれない。   However, when an insulator is provided at the electrode end, a gap, a so-called void, may be formed between the electrode end and the insulator. Due to the presence of such voids, the occurrence of discharge still cannot be prevented.

本発明はこのような問題点を解決するためになされたもので、部分放電を抑制する構造を有する半導体装置において、従来に比べて絶縁信頼性がより高い半導体装置、及びその製造方法を提供することを目的とする。   The present invention has been made to solve the above-described problems, and provides a semiconductor device having a structure that suppresses partial discharge and has higher insulation reliability than conventional semiconductor devices and a method for manufacturing the same. For the purpose.

上記目的を達成するため、本発明は以下のように構成する。
即ち、本発明の一態様における半導体装置は、回路電極を主面に接合した絶縁基板と、上記回路電極に隣接して上記主面に形成したベース用絶縁物と、上記ベース用絶縁物上に形成され上記回路電極と同電位とした導電物と、上記導電物において上記回路電極とは反対側に位置する反回路電極側端部を覆う放電防止用絶縁物と、を備えたことを特徴とする。In order to achieve the above object, the present invention is configured as follows.
That is, a semiconductor device according to one embodiment of the present invention includes an insulating substrate having a circuit electrode bonded to a main surface, a base insulator formed on the main surface adjacent to the circuit electrode, and the base insulator. A conductive material formed at the same potential as the circuit electrode; and a discharge preventing insulator that covers the opposite end of the conductive material on the side opposite to the circuit electrode. To do.

本発明の一態様における半導体装置によれば、絶縁基板における回路電極と同電位とした導電物を備えたことで、回路電極端部における電界集中が緩和される。さらに放電防止用絶縁物を備えたことで、設置した導電物の端部からの電界集中による放電を抑制することができる。よって、従来に比べて絶縁信頼性がより高い半導体装置を提供することが可能となる。また、従来に比べて半導体装置の長寿命化を図ることも可能となる。   According to the semiconductor device of one embodiment of the present invention, the electric field concentration at the end of the circuit electrode is reduced by including the conductive material having the same potential as the circuit electrode in the insulating substrate. Furthermore, by providing the insulator for preventing discharge, discharge due to electric field concentration from the end of the installed conductor can be suppressed. Therefore, it is possible to provide a semiconductor device with higher insulation reliability than conventional. In addition, it is possible to extend the life of the semiconductor device as compared with the prior art.

本発明の実施の形態１における半導体装置の概略構造を示し放電を抑制する構造部分を示した断面図である。It is sectional drawing which showed the schematic structure of the semiconductor device in Embodiment 1 of this invention, and showed the structure part which suppresses discharge. 図１に示す構造の作製途中を示す図であり、電極から隙間を空けた位置にベース用絶縁物と導電物を設けた構造を示した図である。It is a figure which shows the preparation process of the structure shown in FIG. 1, and is the figure which showed the structure which provided the insulator for bases, and the electrically conductive material in the position which left the clearance gap from the electrode. 図１に示す構造の作製途中を示す図であり、図２に示す段階よりも前段階であって電極から隙間を空けた位置にベース用絶縁物を配置した状態を示す図である。FIG. 3 is a diagram illustrating the process of manufacturing the structure illustrated in FIG. 1, and is a diagram illustrating a state in which a base insulator is arranged at a position before the stage illustrated in FIG. 図２に示す構造において導電物からベース用絶縁物の界面に沿って放電する状態を表す図である。It is a figure showing the state discharged along the interface of the insulator for bases from a conductor in the structure shown in FIG. 図１に示す構造において導電物からベース用絶縁物を貫通する方向に放電する状態を表す図である。It is a figure showing the state discharged in the direction which penetrates the insulator for bases from a conductor in the structure shown in FIG. （ａ）から（ｅ）は図１に示す構造の製造方法を説明した図である。(A)-(e) is the figure explaining the manufacturing method of the structure shown in FIG. 本発明の実施の形態２における半導体装置の概略構造を示し放電を抑制する構造部分を示した断面図である。It is sectional drawing which showed the schematic structure of the semiconductor device in Embodiment 2 of this invention, and showed the structure part which suppresses discharge. 本発明の実施の形態３における半導体装置の概略構造を示す断面図である。It is sectional drawing which shows schematic structure of the semiconductor device in Embodiment 3 of this invention. 図８に示すＢ部の拡大図である。It is an enlarged view of the B section shown in FIG. 図９に示す放電を抑制する構造部分の作製方法を説明するための図である。It is a figure for demonstrating the preparation methods of the structure part which suppresses the discharge shown in FIG. 本発明の実施の形態４における半導体装置の概略構造を示し、図８に示す実施の形態３における半導体装置の変形例を示す図である。FIG. 10 is a diagram illustrating a schematic structure of a semiconductor device according to a fourth embodiment of the present invention, and illustrates a modification of the semiconductor device according to the third embodiment illustrated in FIG. 8. 本発明の実施の形態５における半導体装置の概略構造を示し放電を抑制する構造部分を示した断面図である。It is sectional drawing which showed the schematic structure of the semiconductor device in Embodiment 5 of this invention, and showed the structure part which suppresses discharge. 本発明の実施の形態６における半導体装置の概略構造を示し放電を抑制する構造部分を示した断面図である。It is sectional drawing which showed the schematic structure of the semiconductor device in Embodiment 6 of this invention, and showed the structure part which suppresses discharge. 図１３に示す電界緩和部材の拡大図である。It is an enlarged view of the electric field relaxation member shown in FIG. 本発明の実施の形態７における半導体装置の概略構造を示す図である。It is a figure which shows schematic structure of the semiconductor device in Embodiment 7 of this invention. 図１５に示す構造において絶縁破壊経路を説明する図である。It is a figure explaining a dielectric breakdown path | route in the structure shown in FIG. 半導体モジュール全体の構造を示す断面図である。It is sectional drawing which shows the structure of the whole semiconductor module. 図１７に示すＡ部の拡大図であり、放電発生箇所を説明する図である。It is an enlarged view of the A section shown in FIG. 17, and is a diagram for explaining a discharge occurrence location. 半導体モジュールにおいて電極に対する固体絶縁物の塗布によるボイド残留を説明するための図である。It is a figure for demonstrating the void residue by application | coating of the solid insulator with respect to an electrode in a semiconductor module. 半導体モジュールにおいて電極に対して導電物を設けた形態を示す図である。It is a figure which shows the form which provided the electrically conductive material with respect to the electrode in a semiconductor module.

本発明の実施形態である半導体装置について、図を参照しながら以下に説明する。尚、各図において、同一又は同様の構成部分については同じ符号を付している。また、以下の説明が不必要に冗長になるのを避け当業者の理解を容易にするため、既によく知られた事項の詳細説明及び実質的に同一の構成に対する重複説明を省略する場合がある。また、以下の説明及び添付図面の内容は、請求の範囲に記載の主題を限定することを意図するものではない。   A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In each figure, the same or similar components are denoted by the same reference numerals. In addition, in order to avoid the following description from becoming unnecessarily redundant and to facilitate understanding by those skilled in the art, a detailed description of already well-known matters and a duplicate description of substantially the same configuration may be omitted. . Also, the contents of the following description and the accompanying drawings are not intended to limit the subject matter described in the claims.

本発明の実施の形態における半導体装置を説明する前に、特にパワーモジュールと呼ばれる高電圧半導体モジュールにおいて部分放電を抑制するための構造について、まず説明を行う。
図１７には、一般的な高電圧半導体モジュールの断面概略図を示す。この高電圧半導体モジュールは、半導体チップ１と、電極２と、絶縁基板３と、下部電極４と、はんだ５と、放熱板６と、絶縁封止材７と、ケース８とを備える。絶縁基板３の表、裏面には、それぞれ電極２及び下部電極４が接合されており、電極２には高電圧が印加される。電極２にはパワー半導体デバイスとしての半導体チップ１が接合されている。このような絶縁基板３は下部電極４が放熱板６にはんだ５で接合される。また、半導体チップ１が実装された絶縁基板３の周囲を含めてケース８内は、シリコーンゲルを代表とする絶縁封止材７によって封止され絶縁される。Before describing the semiconductor device according to the embodiment of the present invention, a structure for suppressing partial discharge in a high voltage semiconductor module called a power module will be described first.
FIG. 17 shows a schematic cross-sectional view of a general high-voltage semiconductor module. This high voltage semiconductor module includes a semiconductor chip 1, an electrode 2, an insulating substrate 3, a lower electrode 4, solder 5, a heat sink 6, an insulating sealing material 7, and a case 8. The electrode 2 and the lower electrode 4 are joined to the front and back surfaces of the insulating substrate 3, respectively, and a high voltage is applied to the electrode 2. A semiconductor chip 1 as a power semiconductor device is joined to the electrode 2. In such an insulating substrate 3, the lower electrode 4 is joined to the heat sink 6 with solder 5. The inside of the case 8 including the periphery of the insulating substrate 3 on which the semiconductor chip 1 is mounted is sealed and insulated by an insulating sealing material 7 typified by silicone gel.

図１７において、電極２の端部に相当する、点線で示すＡ部の領域は、最も電界が集中しやすい部分であり、Ａ部を拡大したものを図１８に示す。
電極２と絶縁基板３と絶縁封止材７との接点（３重点）が電界集中部９ａとなり、放電の起点となる。放電が発生する際には、起点となる電界集中部９ａから絶縁基板３と絶縁封止材７との界面に沿うように放電１７が発生する。放電１７の発生は、当該高電圧半導体モジュールの絶縁信頼性を損なうと共に、上述したように機器の故障あるいは破壊を引き起こす要因となる。In FIG. 17, a region A indicated by a dotted line corresponding to the end of the electrode 2 is a portion where the electric field is most easily concentrated, and an enlarged view of the portion A is shown in FIG. 18.
A contact point (three points) of the electrode 2, the insulating substrate 3, and the insulating sealing material 7 serves as an electric field concentration portion 9 a and serves as a starting point of discharge. When the discharge occurs, a discharge 17 is generated along the interface between the insulating substrate 3 and the insulating sealing material 7 from the electric field concentration portion 9a that is the starting point. The occurrence of the discharge 17 impairs the insulation reliability of the high-voltage semiconductor module and causes a failure or destruction of the equipment as described above.

放電１７の起因となる電界集中を緩和するために、絶縁基板３の厚さを大きくする手法も取られているが、半導体チップ１からの放熱性が低下するという問題が生じる。よって絶縁基板３の厚さを大きくすることなく放電１７を抑制する方法として、電界が集中する絶縁基板３上の電極２の端部へ、耐圧の高い絶縁物を充填、塗布する方法がある。この絶縁物としては、例えば無機系ガラス材あるいはエポキシ樹脂が用いられる。   A method of increasing the thickness of the insulating substrate 3 is also taken in order to alleviate the electric field concentration that causes the discharge 17, but there is a problem that heat dissipation from the semiconductor chip 1 is lowered. Therefore, as a method of suppressing the discharge 17 without increasing the thickness of the insulating substrate 3, there is a method of filling and applying an insulating material having a high withstand voltage to the end portion of the electrode 2 on the insulating substrate 3 where the electric field is concentrated. As this insulator, for example, an inorganic glass material or an epoxy resin is used.

しかしながらこのような絶縁物の充填、塗布する方法は、既に説明したように、電極２の端部とこの絶縁物との間に隙間つまりボイドを形成する可能性がある。詳しく説明すると、図１７に示すように、電極２の端部を含めて半導体モジュールは、シリコーンゲルからなる絶縁封止材７によって封止されるが、このシリコーンゲルは、性質上、他の絶縁樹脂に比べると気泡が抜けやすい特徴がある。一方、電極２の端部を被覆する絶縁物としてのエポキシ樹脂あるいはシリコン樹脂は、絶縁封止材７のシリコーンゲルに比べるとボイド（空隙）が残留しやすい。よってエポキシ樹脂等の絶縁物を電極２の端部に塗布する際に電極２の端部を完全に封止できずに隙間が生じた場合には、エポキシ樹脂等の絶縁物は、ボイドを含んだまま硬化してしまう可能性がある。   However, such a method of filling and applying the insulator may cause a gap, that is, a void, between the end portion of the electrode 2 and the insulator, as already described. More specifically, as shown in FIG. 17, the semiconductor module including the end portion of the electrode 2 is sealed with an insulating sealing material 7 made of silicone gel. Compared with resin, there is a feature that bubbles are easily removed. On the other hand, the epoxy resin or silicon resin as an insulator covering the end of the electrode 2 tends to have voids (voids) remaining as compared with the silicone gel of the insulating sealing material 7. Therefore, when an insulating material such as an epoxy resin is applied to the end portion of the electrode 2 and the end portion of the electrode 2 cannot be completely sealed and a gap is generated, the insulating material such as the epoxy resin contains a void. There is a possibility of curing.

電極２の端部側面が絶縁基板３に対して垂直である場合、あるいは絶縁基板３に電極２を接合する接合材（図１９に示す「１２」）が電極２の端部側面３０よりも外側へ突出している場合には、電極２の端部に絶縁物を塗布する際のボイド形成は発生し難い。一方、例えば製造時における電極２のエッチング量が大きくなり、図１９に示すように、絶縁基板３に電極２を接合する接合材１２が電極２の端部側面３０よりも内側へ凹んだ状態において絶縁物１０を塗布した場合には、この凹み部分にボイド１１が形成され易い。   When the end side surface of the electrode 2 is perpendicular to the insulating substrate 3, or the bonding material ("12" shown in FIG. 19) for bonding the electrode 2 to the insulating substrate 3 is outside the end side surface 30 of the electrode 2. In the case of protruding to the end, void formation is hardly generated when an insulator is applied to the end of the electrode 2. On the other hand, for example, the etching amount of the electrode 2 at the time of manufacture increases, and the bonding material 12 for bonding the electrode 2 to the insulating substrate 3 is recessed inward from the end side surface 30 of the electrode 2 as shown in FIG. When the insulator 10 is applied, the void 11 is easily formed in the recessed portion.

このように、電極２の端部側面３０も含めて単に絶縁封止材７によって封止する代わりに、高耐圧の絶縁物１０を、電界集中部となる電極２の端部側面３０に充填する場合には、電極の端部側面３０の形状によっては、絶縁封止材７の封入に比べて逆に、ボイド１１の残留可能性を高めてしまう。その結果、ボイド１１部分で放電が発生する恐れがある。   In this way, instead of simply sealing with the insulating sealing material 7 including the end side surface 30 of the electrode 2, the high withstand voltage insulator 10 is filled in the end side surface 30 of the electrode 2 that becomes the electric field concentration portion. In some cases, depending on the shape of the end side surface 30 of the electrode, the possibility that the void 11 remains is increased as compared with the case where the insulating sealing material 7 is sealed. As a result, there is a possibility that discharge occurs in the void 11 portion.

また、上述の例では、電極２の端部側面３０に塗布されるものは絶縁物１０であるが、図２０に示すように、電極２の端部側面３０における電界集中部に対して導電物１３を被覆することで、電界を緩和する構造もある。この導電物１３は、金属または導電性樹脂、あるいはＮｉメッキ等が使用可能である。   In the above-described example, the insulator 10 is applied to the end side surface 30 of the electrode 2, but as shown in FIG. There is also a structure that relaxes the electric field by covering 13. The conductive material 13 can be made of metal, conductive resin, Ni plating, or the like.

このような構造は、図２０に示すように、電極端部のエッジを導電物１３によって緩やかにすることで電界を緩和している。しかしながらこの構成においても、絶縁基板３と導電物１３と絶縁封止材７との接点にて電界集中部９ｂが発生するため、放電の発生起点となり得る。   In such a structure, as shown in FIG. 20, the electric field is relaxed by making the edge of the electrode end gentle by the conductive material 13. However, even in this configuration, since the electric field concentration portion 9b is generated at the contact point between the insulating substrate 3, the conductive material 13, and the insulating sealing material 7, it can be a starting point of discharge.

したがって、以下に説明する本発明の実施形態である半導体装置は、半導体モジュールにおける上述したような問題点を解決するための構成を有し、その結果、従来に比べてより高い絶縁信頼性を有することができる。
また、具体的に以下で説明する各実施の形態における半導体装置は、特に高電圧が印加されるパワー半導体モジュールを例に採るが、これに限定されるものではない。つまり、パワー半導体モジュールよりも耐圧が低い通常の半導体素子を用いた半導体装置においても、以下に説明する構成を採ることができ、同様の効果を得ることができる。Therefore, the semiconductor device which is an embodiment of the present invention described below has a configuration for solving the above-described problems in the semiconductor module, and as a result, has higher insulation reliability than the conventional one. be able to.
Further, the semiconductor device in each of the embodiments specifically described below takes a power semiconductor module to which a high voltage is applied as an example, but is not limited thereto. That is, even in a semiconductor device using a normal semiconductor element having a withstand voltage lower than that of the power semiconductor module, the configuration described below can be adopted, and similar effects can be obtained.

実施の形態１．
図１から図３は、本発明の実施の形態１における半導体装置１０１の概略構造を示しており、上述した図１７に示すＡ部に相当する部分を示している。
本実施の形態１における半導体装置１０１も、図１７を参照して説明した半導体装置と同様に、半導体チップ１と、電極２と、絶縁基板３と、下部電極４と、はんだ５と、放熱板６と、絶縁封止材７と、ケース８とを備える。Embodiment 1 FIG.
1 to 3 show a schematic structure of the semiconductor device 101 according to the first embodiment of the present invention, and show a portion corresponding to the A portion shown in FIG. 17 described above.
Similarly to the semiconductor device described with reference to FIG. 17, the semiconductor device 101 according to the first embodiment also has the semiconductor chip 1, the electrode 2, the insulating substrate 3, the lower electrode 4, the solder 5, and the heat sink. 6, an insulating sealing material 7, and a case 8.

絶縁基板３は、アルミナ（Ａｌ２Ｏ３）、窒化アルミニウム（ＡｌＮ）、又は窒化珪素（Ｓｉ３Ｎ４）といったセラミック板である。絶縁基板３の主面３ａには、接合材（ロウ材）１２を介して回路電極（以下、単に「電極」と記す場合もある）２が接合されている。ここで電極２はアルミニウムあるいは銅で作製される。絶縁基板３に回路電極２を接合した後、電極２をエッチングすることによって、任意の形状の電極パターンが形成される。このとき、エッチング液との反応速度が電極２に比べて接合材１２の方が大きく、接合材１２が余分に削られてしまう場合がある。この場合、電極２に対する接合材１２の端部１２ａは、望む断面形状にはならずに、図３に示すように、電極２の端部側面３０よりも内側へ凹みが起こり得る。つまり、通常、接合材１２の端部１２ａは、絶縁基板３に対して垂直に近い状態か、電極２の端部側面３０よりも僅かに外側へ突出するように調整される。しかしながら処理状態にはバラつきがあるため、接合材１２の全体で一様にはなりにくく、内側へ凹み形状となることがあり得る。この場合、電極２及び接合材１２と絶縁基板３との接点で電界集中部９ａが存在する。よって、この凹み部分にボイドが残留すると放電の可能性が高くなる。The insulating substrate 3 is a ceramic plate such as alumina (Al 2 O 3 ), aluminum nitride (AlN), or silicon nitride (Si 3 N 4 ). A circuit electrode (hereinafter may be simply referred to as “electrode”) 2 is bonded to the main surface 3 a of the insulating substrate 3 via a bonding material (brazing material) 12. Here, the electrode 2 is made of aluminum or copper. After joining the circuit electrode 2 to the insulating substrate 3, the electrode 2 is etched to form an electrode pattern having an arbitrary shape. At this time, the bonding material 12 has a higher reaction rate with the etching solution than the electrode 2, and the bonding material 12 may be scraped excessively. In this case, the end 12a of the bonding material 12 with respect to the electrode 2 does not have a desired cross-sectional shape, but may be recessed more inwardly than the end side surface 30 of the electrode 2 as shown in FIG. In other words, the end 12 a of the bonding material 12 is usually adjusted so as to be almost perpendicular to the insulating substrate 3 or slightly outward from the end side surface 30 of the electrode 2. However, since the processing state varies, it is difficult for the entire bonding material 12 to be uniform, and a concave shape may be formed inside. In this case, the electric field concentration portion 9 a exists at the contact point between the electrode 2 and the bonding material 12 and the insulating substrate 3. Therefore, if a void remains in the recessed portion, the possibility of discharge increases.

電界集中部９ａの電界を緩和する構造として、図３に示すように、絶縁基板３の主面３ａに、電極２に隣接して電極２と同電位となる導電物１３を設置する方法がある。尚、導電物１３は、電極２と導線１８で接続して同電位を形成する。このように構成することで、導電物１３の電界シールドによって接合材１２部分における電界集中部９ａの電界を緩和することができる。しかしながら、このようにして電界集中部９ａの電界を緩和した場合でも、図３に示すように、導電物１３の端部に新たに電界集中部９ｂが発生する。この場合、絶縁基板３と絶縁封止材７の界面１４に沿う方向に放電が発生する。   As a structure for relaxing the electric field of the electric field concentration portion 9a, there is a method in which a conductor 13 having the same potential as that of the electrode 2 is provided on the main surface 3a of the insulating substrate 3 adjacent to the electrode 2 as shown in FIG. . The conductive material 13 is connected to the electrode 2 by the conductive wire 18 to form the same potential. With this configuration, the electric field of the electric field concentration portion 9a in the bonding material 12 portion can be relaxed by the electric field shield of the conductive material 13. However, even when the electric field of the electric field concentration portion 9a is relaxed in this way, a new electric field concentration portion 9b is generated at the end portion of the conductor 13, as shown in FIG. In this case, discharge occurs in a direction along the interface 14 between the insulating substrate 3 and the insulating sealing material 7.

そこで本発明の実施の形態１における半導体装置１０１の構造では、まず図２に示すように、絶縁基板３の主面３ａに回路電極２に隣接して第１固体絶縁物であるベース用絶縁物１０ａを塗布する。ベース用絶縁物１０ａとして、エポキシ系の樹脂あるいはシリコン系の樹脂など、硬化後に絶縁基板３に充分に接着でき、耐圧の高い材料であればよく、特に限定するものはない。   Therefore, in the structure of the semiconductor device 101 according to the first embodiment of the present invention, first, as shown in FIG. 2, the base insulator that is the first solid insulator adjacent to the circuit electrode 2 on the main surface 3 a of the insulating substrate 3. Apply 10a. The base insulator 10a is not particularly limited as long as it is a material that can sufficiently adhere to the insulating substrate 3 after curing and has a high withstand voltage, such as an epoxy resin or a silicon resin.

このとき本実施の形態１では、ベース用絶縁物１０ａは、電極２及び接合材１２に接触しないように隙間３２を設けている。これは、ベース用絶縁物１０ａを電極２及び接合材１２に接触させて形成する場合、接合材１２の端部１２ａが上述のように電極２の端部側面３０よりも凹んでいる状態では、図１９に示すようにボイドが残留し、その部分での放電の可能性が高まるためである。
一方、隙間３２を設けることで、隙間３２には絶縁封止材７としてシリコーンゲルが充填されることになる。シリコーンゲルは、上述したように気泡が比較的抜けやすいため、エポキシ樹脂あるいはシリコン樹脂などを塗布する場合に比べて、ボイド残留の可能性が低くなる。但し、隙間３２が非常に狭い場合には、シリコーンゲルが完全に充填するまでに要する時間が長くなるため、シリコーンゲルを加熱硬化させる前に十分に時間を置く必要がある。At this time, in the first embodiment, the base insulator 10 a is provided with a gap 32 so as not to contact the electrode 2 and the bonding material 12. This is because when the base insulator 10a is formed in contact with the electrode 2 and the bonding material 12, the end portion 12a of the bonding material 12 is recessed from the end side surface 30 of the electrode 2 as described above. This is because voids remain as shown in FIG. 19 and the possibility of discharge at that portion increases.
On the other hand, by providing the gap 32, the gap 32 is filled with silicone gel as the insulating sealing material 7. As described above, since the bubbles of the silicone gel are relatively easy to escape, the possibility of voids remaining is lower than when an epoxy resin or a silicone resin is applied. However, when the gap 32 is very narrow, it takes a long time to completely fill the silicone gel. Therefore, it is necessary to allow sufficient time before the silicone gel is heated and cured.

次に、ベース用絶縁物１０ａの上に導電物１３を形成する。導電物１３は、電極２と同電位となるように、いずれかの位置で導線１８を介して電極２と導通させる。これにより、電極２の端部付近における電界集中部９ａの電界を緩和することができる。導電物１３は、導電性の塗料を塗布し硬化させて形成してもよいし、金属ワイヤーなどの固形の導電物を設置してもよい。   Next, the conductor 13 is formed on the base insulator 10a. The conductive material 13 is electrically connected to the electrode 2 via the conductive wire 18 at any position so as to have the same potential as the electrode 2. Thereby, the electric field of the electric field concentration part 9a in the vicinity of the end part of the electrode 2 can be relaxed. The conductive material 13 may be formed by applying and curing a conductive paint, or may be provided with a solid conductive material such as a metal wire.

ここで、ベース用絶縁物１０ａ及び導電物１３の有無において、電界集中部９ａの電界値の比較結果の一例を示す。
例えば、絶縁基板３の材質を窒化アルミニウム（比誘電率：９）で厚さを０．５ｍｍ、絶縁封止材７をシリコーンゲル（比誘電率：３）、ベース用絶縁物１０ａをエポキシ樹脂（比誘電率：４）とし、ベース用絶縁物１０ａ及び導電物１３と電極２との隙間を０．１ｍｍ、ベース用絶縁物１０ａの高さ（厚み）を３０μｍ、導電物１３の高さ（厚み）を３０μｍ、接合材１２を含めた電極２の厚さを０．４ｍｍ、電極２と接合材１２の端部１２ａは、絶縁基板３に対して垂直であるとして、電界集中部９ａの電界値を計算して比較を行う。
その結果、ベース用絶縁物１０ａ及び導電物１３を設けた場合は、設けない場合に比べて電界が約３５％緩和された。ここでの電界緩和率は、導電物１３の位置によって変わり、電界集中部９ａに近いほど効果が高くなる。Here, an example of the comparison result of the electric field value of the electric field concentration portion 9a in the presence or absence of the base insulator 10a and the conductor 13 will be shown.
For example, the material of the insulating substrate 3 is aluminum nitride (relative permittivity: 9), the thickness is 0.5 mm, the insulating sealing material 7 is silicone gel (relative permittivity: 3), and the base insulator 10a is epoxy resin ( The dielectric constant is 4), the gap between the base insulator 10a and the conductor 13 and the electrode 2 is 0.1 mm, the height (thickness) of the base insulator 10a is 30 μm, and the height (thickness) of the conductor 13 ) Is 30 μm, the thickness of the electrode 2 including the bonding material 12 is 0.4 mm, and the end portion 12 a of the electrode 2 and the bonding material 12 is perpendicular to the insulating substrate 3. And compare.
As a result, when the base insulator 10a and the conductor 13 were provided, the electric field was reduced by about 35% compared to when the base insulator 10a and the conductor 13 were not provided. Here, the electric field relaxation rate varies depending on the position of the conductor 13, and the closer to the electric field concentration portion 9a, the higher the effect.

一方、導電物１３を設けたままの構造では、図２に示すように、導電物１３の端部に新たに電界集中部９ｂが発生する。この状態では、電界集中部９ｂを起点とし、ベース用絶縁物１０ａと絶縁封止材７の界面１５で放電が発生しやすくなる。   On the other hand, in the structure in which the conductor 13 is provided, an electric field concentration portion 9b is newly generated at the end of the conductor 13, as shown in FIG. In this state, electric discharge tends to occur at the interface 15 between the base insulator 10a and the insulating sealing material 7 starting from the electric field concentration portion 9b.

そこで実施の形態１の半導体装置１０１ではさらに、図１に示すように、導電物１３の端部、つまり導電物１３において回路電極２から遠い方に位置する、換言すると回路電極２とは反対側に位置する反回路電極側端部３５における電界集中部９ｂを覆うようにして、第２固体絶縁物である放電防止用絶縁物１０ｂを導電物１３の側面及び上面に塗布する。このとき、ベース用絶縁物１０ａが硬化する前に、放電防止用絶縁物１０ｂを塗布すれば、ベース用絶縁物１０ａと放電防止用絶縁物１０ｂとの間の接着界面１６を強固にすることができる。ここでベース用絶縁物１０ａと放電防止用絶縁物１０ｂとが同一材料であれば、硬化後、両者はほぼ一体化されて界面１６を無くすことができる。よって界面絶縁を強くすることができる。
ベース用絶縁物１０ａと放電防止用絶縁物１０ｂとが異なる材料の場合でも、硬化後の接着界面１６の界面絶縁耐圧が十分に高い場合には適用可能である。Therefore, in the semiconductor device 101 according to the first embodiment, as shown in FIG. 1, the end of the conductor 13, that is, the farther away from the circuit electrode 2 in the conductor 13, in other words, the opposite side of the circuit electrode 2. A discharge preventing insulator 10b, which is a second solid insulator, is applied to the side surface and the upper surface of the conductive material 13 so as to cover the electric field concentration portion 9b at the end portion 35 on the side opposite to the circuit electrode located at the top. At this time, if the discharge preventing insulator 10b is applied before the base insulator 10a is cured, the adhesion interface 16 between the base insulator 10a and the discharge preventing insulator 10b can be strengthened. it can. Here, if the base insulator 10a and the discharge preventing insulator 10b are made of the same material, they can be substantially integrated after curing to eliminate the interface 16. Therefore, interface insulation can be strengthened.
Even in the case where the base insulator 10a and the discharge preventing insulator 10b are made of different materials, it is applicable when the interface dielectric strength of the adhesive interface 16 after curing is sufficiently high.

放電は、材料を貫通する方向よりも、部材の界面に沿う方向の方が起こりやすい。そのため、図３及び図２の構造のように、電界集中部９ｂに対して絶縁基板３と絶縁封止材７との界面１４、及びベース用絶縁物１０ａと絶縁封止材７との界面１５が存在すると、図４に示すように界面１５に沿って放電１７が発生する。一方、図５に示すように電界集中部９ｂの周囲がベース用絶縁物１０ａ及び放電防止用絶縁物１０ｂで覆われていると、ベース用絶縁物１０ａと放電防止用絶縁物１０ｂとの間の接着界面１６の界面絶縁耐圧は大きい。よって、ベース用絶縁物１０ａを貫通する方向に放電１７が発生しようとする。このような理由から、放電防止用絶縁物１０ｂが存在しない場合に比べると、耐圧は高くなる。   Discharge is more likely to occur in the direction along the interface of the member than in the direction through the material. Therefore, as shown in FIGS. 3 and 2, the interface 14 between the insulating substrate 3 and the insulating sealing material 7 and the interface 15 between the base insulator 10a and the insulating sealing material 7 with respect to the electric field concentration portion 9b. As shown in FIG. 4, a discharge 17 is generated along the interface 15. On the other hand, when the periphery of the electric field concentration portion 9b is covered with the base insulator 10a and the discharge preventing insulator 10b as shown in FIG. 5, the gap between the base insulator 10a and the discharge preventing insulator 10b is between. The interface withstand voltage of the adhesive interface 16 is large. Therefore, the discharge 17 tends to occur in a direction penetrating the base insulator 10a. For this reason, the withstand voltage is higher than when the discharge preventing insulator 10b is not present.

以上説明した本実施の形態１における半導体装置１０１の構造を作製する手順について、図６を参照して説明する。尚、主面３ａには接合材１２を介して回路電極２が接合されている絶縁基板３を予め用意する。このとき接合材１２の端部１２ａは、電極２の端部側面３０よりも内側へ凹んでいるものとする。   A procedure for manufacturing the structure of the semiconductor device 101 according to the first embodiment described above will be described with reference to FIGS. An insulating substrate 3 to which the circuit electrode 2 is bonded via the bonding material 12 is prepared in advance on the main surface 3a. At this time, it is assumed that the end 12 a of the bonding material 12 is recessed inward from the end side surface 30 of the electrode 2.

図６の（ａ）に示すように、まず、電極２の端部側面３０に対して、隙間３２を形成するための、任意の厚さのスペーサ１９を絶縁基板３の主面３ａに設置する。スペーサ１９は、後で取り外すことになるため、絶縁封止材７と接着しにくい例えばテフロン（登録商標）などの素材を用いる。
次に、（ｂ）に示すように、絶縁基板３の主面３ａに未硬化のベース用絶縁物１０ａをスペーサ１９を介して塗布する。
次に、（ｃ）に示すように、ベース用絶縁物１０ａが硬化する前に、ベース用絶縁物１０ａの上に導電物１３を設置する。導電物１３は、導電性塗料を塗布するのでも、細い線状の金属物を設置するのでもよい。また、後からでは導電物１３へ導線１８を接続しにくくなる恐れがあるため、導電物１３を電極２と導通させるための導線１８を導電物１３に繋げておく。As shown in FIG. 6A, first, a spacer 19 having an arbitrary thickness is provided on the main surface 3 a of the insulating substrate 3 in order to form a gap 32 with respect to the end side surface 30 of the electrode 2. . Since the spacer 19 is removed later, a material such as Teflon (registered trademark) that is difficult to adhere to the insulating sealing material 7 is used.
Next, as shown in (b), an uncured base insulator 10 a is applied to the main surface 3 a of the insulating substrate 3 through a spacer 19.
Next, as shown in (c), before the base insulator 10a is cured, the conductor 13 is placed on the base insulator 10a. The conductive material 13 may be a conductive paint or a thin linear metal material. In addition, since there is a risk that it is difficult to connect the conductive wire 18 to the conductive material 13 later, the conductive wire 18 for connecting the conductive material 13 to the electrode 2 is connected to the conductive material 13.

次に、（ｄ）に示すように、ベース用絶縁物１０ａが硬化する前に、導電物１３においてスペーサ１９とは反対側、言い換えると導電物１３における反回路電極側端部３５に対して導電物１３の側面及び上面を覆うようにして、本実施の形態１ではベース用絶縁物１０ａと同じ材質の未硬化の放電防止用絶縁物１０ｂを塗布する。
次に、（ｅ）に示すように、スペーサ１９を取り外し、導線１８を電極２へと接続する。これにより、スペーサ１９による隙間３２がベース用絶縁物１０ａ及び導電層１３と電極２との間に形成される。Next, as shown in (d), before the base insulator 10a is cured, the conductive material 13 is electrically conductive with respect to the side opposite to the spacer 19, that is, with respect to the counter circuit electrode side end portion 35 of the conductive material 13. In the first embodiment, an uncured discharge preventing insulator 10b made of the same material as the base insulator 10a is applied so as to cover the side surface and the upper surface of the object 13.
Next, as shown in (e), the spacer 19 is removed and the conductor 18 is connected to the electrode 2. As a result, a gap 32 due to the spacer 19 is formed between the base insulator 10 a and the conductive layer 13 and the electrode 2.

以上説明したように、本実施の形態１に示す半導体装置１０１における構造によれば、電極２の電界集中部９ａの電界を緩和させることができ、かつ電界緩和のために設置した導電物１３からの放電も抑制する構造を得ることができる。したがって、従来に比べて半導体装置の長寿命化を図ることができるとともに、絶縁信頼性がより高い半導体装置、及びその製造方法を提供することが可能である。   As described above, according to the structure of the semiconductor device 101 shown in the first embodiment, the electric field of the electric field concentration portion 9a of the electrode 2 can be relaxed, and from the conductive material 13 installed for the electric field relaxation. It is possible to obtain a structure that suppresses the discharge. Therefore, it is possible to provide a semiconductor device having a longer lifetime than that of the conventional semiconductor device and having higher insulation reliability, and a method for manufacturing the same.

実施の形態２．
上述した実施の形態１では、ベース用絶縁物１０ａ及び導電物１３は、電極２との間に隙間３２を設けている。これは、上述したように、隙間３２を設けることで隙間３２へ絶縁封止材７を流入させ、ベース用絶縁物１０ａによるボイド生成及び残留のリスクを下げることを目的としたためである。一方、接合材１２の端部１２ａについて、電極２の下方側への凹みが存在しない、もしくは凹みが小さくボイド残留の可能性が高くないことが分かっている場合には、特に隙間３２を設けることのメリットは小さいと言える。本実施の形態２における半導体装置は、このような場合における構成を有する。Embodiment 2. FIG.
In the first embodiment described above, the base insulator 10 a and the conductor 13 are provided with the gap 32 between the electrode 2. This is because, as described above, by providing the gap 32, the insulating sealing material 7 is caused to flow into the gap 32, and the purpose is to reduce the risk of void generation and residual due to the base insulator 10a. On the other hand, when it is known that the end 12a of the bonding material 12 does not have a dent on the lower side of the electrode 2 or the dent is small and the possibility of voids remaining is not high, a gap 32 is provided. It can be said that the merit is small. The semiconductor device according to the second embodiment has a configuration in such a case.

図７に、本実施の形態２における半導体装置１０２の構造を示す。半導体装置１０２では、ベース用絶縁物１０ａは、電極２及び接合材１２による電界集中部９ａを覆うように、つまり隙間３２を設けることなく、塗布されている。導電物１３の周辺部については、実施の形態１と同様に、導電物１３の反回路電極側端部３５を覆うように放電防止用絶縁物１０ｂが塗布される。   FIG. 7 shows the structure of the semiconductor device 102 according to the second embodiment. In the semiconductor device 102, the base insulator 10 a is applied so as to cover the electric field concentration portion 9 a formed by the electrode 2 and the bonding material 12, that is, without providing the gap 32. As in the first embodiment, the discharge preventing insulator 10b is applied to the peripheral portion of the conductive material 13 so as to cover the counter circuit electrode side end portion 35 of the conductive material 13.

電極端部における電界集中部９ａは、上述のようにベース用絶縁物１０ａで覆われている。このベース用絶縁物１０ａの誘電率が絶縁封止材７の誘電率よりも高ければ、電界集中部９ａの電界はそれだけで緩和される。例えば、絶縁封止材７をシリコーンゲルとして比誘電率を３とし、ベース用絶縁物１０ａを例えばポリイミドとして厚さを３０μｍで比誘電率を３．７とする。絶縁基板３を厚さ０．５ｍｍの窒化アルミニウムで比誘電率を９、接合材１２を含めた電極２の厚さを０．４ｍｍ、電極２及び接合材１２の端部１２ａは、絶縁基板３に対して垂直であると仮定する。この条件でベース用絶縁物１０ａの有無に対して電界集中部９ａの電界を計算して比較を行う。
その結果、ベース用絶縁物１０ａを設けた場合には、設けない場合に比べて電界は約５％低減された。加えて、ベース用絶縁物１０ａの材料自体における絶縁破壊電圧もゲルに比べて高くなるため、ベース用絶縁物１０ａの設置によって、電界集中部９ａでの放電電圧を上げることができる。The electric field concentration portion 9a at the electrode end is covered with the base insulator 10a as described above. If the dielectric constant of the base insulator 10a is higher than the dielectric constant of the insulating sealing material 7, the electric field of the electric field concentration portion 9a is relaxed by itself. For example, the dielectric encapsulant 7 is made of silicone gel, the relative dielectric constant is 3, the base insulator 10a is made of polyimide, for example, and the thickness is 30 μm and the relative dielectric constant is 3.7. The insulating substrate 3 is made of aluminum nitride having a thickness of 0.5 mm, the relative dielectric constant is 9, the thickness of the electrode 2 including the bonding material 12 is 0.4 mm, and the end portion 12a of the electrode 2 and the bonding material 12 is the insulating substrate 3 Is assumed to be perpendicular to Under this condition, the electric field of the electric field concentration portion 9a is calculated and compared with or without the base insulator 10a.
As a result, when the base insulator 10a was provided, the electric field was reduced by about 5% compared to when the base insulator 10a was not provided. In addition, since the dielectric breakdown voltage of the material of the base insulator 10a itself is higher than that of the gel, the discharge voltage at the electric field concentration portion 9a can be increased by installing the base insulator 10a.

また、図７に示す半導体装置１０２の構造では、導電物１３は電極２に対して隙間を開けて配置しているが、直接接触させてもよい。   Further, in the structure of the semiconductor device 102 shown in FIG. 7, the conductor 13 is disposed with a gap with respect to the electrode 2, but may be in direct contact.

以上説明したように、本実施の形態２に示す半導体装置１０２における構造によれば、電極２の端部側面３０付近へのボイド残留のリスクが小さい場合には、実施の形態１の場合と同様に導電物１３を設けたことによる電界緩和効果に加えて、ベース用絶縁物１０ａの材料による放電抑制効果も得ることができる。さらにまた、隙間３２を設ける工程が不要となることから、実施の形態１における構造よりも、半導体装置の製造が簡略化できるという効果も得られる。   As described above, according to the structure of the semiconductor device 102 shown in the second embodiment, when the risk of void remaining near the end side surface 30 of the electrode 2 is small, the same as in the first embodiment. In addition to the effect of reducing the electric field due to the provision of the conductive material 13, the effect of suppressing the discharge by the material of the base insulator 10a can be obtained. Furthermore, since the step of providing the gap 32 is not necessary, the effect that the manufacturing of the semiconductor device can be simplified as compared with the structure in the first embodiment is also obtained.

実施の形態３．
実施の形態１及び実施の形態２では、電界集中部は、図１７の「Ａ」に示すように基板外周部に位置する場合を例にとっている。一方、実際の半導体モジュールで用いられる基板は、図８に示すように、絶縁基板３には複数の、電極２−半導体チップ１のセットがそれぞれ配置されており、複数の電極２ａ、電極２ｂが配置されている場合が多い。本実施の形態３における半導体装置１０３は、このような複数の電極２ａ、２ｂを有する構造である。以下には、図８において点線Ｂで示す電極２ａと電極２ｂとの間の領域の構造について説明する。尚、半導体装置１０３においても図１７に示され説明した各構成部分と同じ構成部分については、同じ符号を付している。Embodiment 3 FIG.
In the first embodiment and the second embodiment, the electric field concentration portion is taken as an example when it is located on the outer peripheral portion of the substrate as shown in “A” of FIG. 17. On the other hand, as shown in FIG. 8, the substrate used in the actual semiconductor module has a plurality of sets of electrode 2 -semiconductor chip 1 arranged on the insulating substrate 3, and a plurality of electrodes 2a and 2b are provided. It is often arranged. The semiconductor device 103 according to the third embodiment has such a structure having a plurality of electrodes 2a and 2b. Below, the structure of the area | region between the electrode 2a shown by the dotted line B in FIG. 8 and the electrode 2b is demonstrated. In the semiconductor device 103 as well, the same components as those illustrated and described in FIG.

図９は、図８に示す点線Ｂの領域を拡大した図である。構造としては、実施の形態１にて図１に示した構造を、電極２ａ、電極２ｂに対して、左右対称とした構造である。電極２ａ側に導電物１３ａを、電極２ｂ側に導電物１３ｂをそれぞれ配置している。但し、図１に示した構造がそれぞれ独立しているのではなく、ベース用絶縁物１０ａ及び放電防止用絶縁物１０ｂは両者に共通の構造を採る。ここで、導電物１３ａと導電物１３ｂとは、互いに接近しすぎると、絶縁上の問題が発生する。導電物１３ａ及び導電物１３ｂについては、電極２ａ及び電極２ｂとの間隔が重要であり、その沿面方向の長さについては、特に重要ではない。したがって、導電物１３ａ及び導電物１３ｂの沿面方向の長さは、導線１８の接続に支障がない程度の長さで十分である。導電物１３ａ及び導電物１３ｂの設置については、互いに接近しすぎないように、図１０に示すように、スペーサ１９ｃを間に置いて作製するとよい。   FIG. 9 is an enlarged view of a region indicated by a dotted line B shown in FIG. As the structure, the structure shown in FIG. 1 in the first embodiment is symmetrical with respect to the electrodes 2a and 2b. A conductor 13a is disposed on the electrode 2a side, and a conductor 13b is disposed on the electrode 2b side. However, the structure shown in FIG. 1 is not independent, and the base insulator 10a and the discharge preventing insulator 10b adopt a common structure. Here, if the conductor 13a and the conductor 13b are too close to each other, an insulation problem occurs. As for the conductor 13a and the conductor 13b, the distance between the electrode 2a and the electrode 2b is important, and the length in the creeping direction is not particularly important. Therefore, the length of the conductive material 13a and the conductive material 13b in the creeping direction is sufficient to prevent the connection of the conductor 18. About installation of the conductor 13a and the conductor 13b, as shown in FIG. 10, it is good to produce with the spacer 19c in between so that it may not come too close to each other.

尚、本実施の形態３では、電極２ａ、電極２ｂの２セットを設けた場合を例示したが、３セット以上を設けた場合も同様に適用可能である。
また、本実施の形態３における半導体装置１０３においても、実施の形態１の半導体装置１０１が奏する効果と同じ効果を得ることができる。In the third embodiment, the case where two sets of the electrode 2a and the electrode 2b are provided is illustrated, but the case where three sets or more are provided is also applicable.
Also in the semiconductor device 103 according to the third embodiment, the same effect as that obtained by the semiconductor device 101 according to the first embodiment can be obtained.

実施の形態４．
図１１に本実施の形態４における半導体装置１０４を示す。この半導体装置１０４に示す構造は、実施の形態３で示した電極間の構造において、実施の形態２で示した構造を適用するものである。即ち、実施の形態３で示した電極間の構造において、製造状態によっては実施の形態２の場合と同様に、接合材１２の端部１２ａも含めて電極２ａ，２ｂの端部側面３０付近におけるボイド残留のリスクが小さい場合には、半導体装置１０４に示す構造を適用することができる。Embodiment 4 FIG.
FIG. 11 shows a semiconductor device 104 according to the fourth embodiment. The structure shown in this semiconductor device 104 applies the structure shown in Embodiment 2 to the structure between the electrodes shown in Embodiment 3. That is, in the structure between the electrodes shown in the third embodiment, depending on the manufacturing state, in the vicinity of the end side surface 30 of the electrodes 2a and 2b including the end 12a of the bonding material 12, as in the case of the second embodiment. When the risk of remaining voids is small, the structure shown in the semiconductor device 104 can be applied.

本実施の形態４の構造を採ることで、実施の形態２にて得られる効果と同様の効果を得ることができる。つまり、実施の形態１の半導体装置１０１が奏する効果と同じ効果に加えて、各接合材１２と、電極２ａ及び電極２ｂとの間に隙間を設ける工程が不要となるため、製造を簡略化することができるという効果が得られる。
ここで導電物１３ａ及び導電物１３ｂは、それぞれ電極２ａ及び電極２ｂと接触させてもよい。By adopting the structure of the fourth embodiment, the same effect as that obtained in the second embodiment can be obtained. In other words, in addition to the same effect as the semiconductor device 101 of the first embodiment, a process of providing a gap between each bonding material 12 and the electrodes 2a and 2b is not necessary, thereby simplifying the manufacturing. The effect that it can be obtained.
Here, the conductive material 13a and the conductive material 13b may be brought into contact with the electrode 2a and the electrode 2b, respectively.

実施の形態５．
図１２に実施の形態５における半導体装置１０５の構造を示す。この半導体装置１０５は、実施の形態１における半導体装置１０１の変形例に相当する。
即ち、実施の形態１で示す構造では、導電物１３の端部における電界集中部９ｂに最も高い電界が発生する。各実施の形態の構造では、電界集中部９ｂに対して材料界面を設けないことにより、界面方向の放電を発生させないことで、放電自体を発生しにくくしている。このような構成にあっても、ベース用絶縁物１０ａの貫通方向（絶縁基板３の厚み方向）、あるいはベース用絶縁物１０ａと放電防止用絶縁物１０ｂの界面方向（界面に沿った方向）へ放電が生じる可能性はある。Embodiment 5 FIG.
FIG. 12 shows the structure of the semiconductor device 105 in the fifth embodiment. This semiconductor device 105 corresponds to a modification of the semiconductor device 101 in the first embodiment.
That is, in the structure shown in the first embodiment, the highest electric field is generated in the electric field concentration portion 9b at the end of the conductive material 13. In the structure of each embodiment, by not providing the material interface with respect to the electric field concentration portion 9b, the discharge in the interface direction is not generated, so that the discharge itself is hardly generated. Even in such a configuration, in the penetration direction of the base insulator 10a (the thickness direction of the insulating substrate 3) or the interface direction of the base insulator 10a and the discharge preventing insulator 10b (the direction along the interface). There is a possibility of discharge.

そこで本実施の形態５で示す構造では、図１２に示すように、導電物１３の端部における電界集中部９ｂの電界を低減するために、導電物１３の回路電極２に近い回路電極側端部３７に対して、導電物１３の回路電極２から遠い反回路電極側端部３５は、絶縁基板３の厚み方向３ｂにおいて、絶縁基板３から離れて上側に位置して高くしている。但し、導電物１３の回路電極側端部３７の位置も共に高くした場合には、接合材１２における電界集中部９ａの電界緩和効果が低減するとともに、電極２との間の隙間３２の深さが深くなり絶縁封止材７が充填しにくくなる。よって、回路電極側端部３７の高さは、実施の形態１の半導体装置１０１と同様に低いままとし、図１２に示すように全体的に導電物１３が傾斜するように構成する。   Therefore, in the structure shown in the fifth embodiment, as shown in FIG. 12, in order to reduce the electric field of the electric field concentration portion 9b at the end of the conductor 13, the end on the side of the circuit electrode near the circuit electrode 2 of the conductor 13. The anti-circuit electrode side end portion 35 of the conductive material 13 that is far from the circuit electrode 2 with respect to the portion 37 is located higher in the thickness direction 3 b of the insulating substrate 3 away from the insulating substrate 3. However, when the position of the circuit electrode side end portion 37 of the conductive material 13 is also increased, the electric field relaxation effect of the electric field concentration portion 9a in the bonding material 12 is reduced and the depth of the gap 32 between the electrodes 2 is reduced. Becomes deeper and it becomes difficult to fill the insulating sealing material 7. Therefore, the height of the circuit electrode side end portion 37 is kept low similarly to the semiconductor device 101 of the first embodiment, and the conductive material 13 is inclined as a whole as shown in FIG.

このように傾斜した導電物１３を形成する方法としては、ベース用絶縁物１０ａを塗布する際、図１２に示すように斜面となるよう塗布を行い、導電物１３の反回路電極側端部３５を規定の高さに位置させる。そしてベース用絶縁物１０ａが硬化する前に、電界集中部９ｂを覆って放電防止用絶縁物１０ｂを塗布する。   As a method of forming the conductive material 13 inclined in this way, when applying the base insulator 10a, it is applied so as to form a slope as shown in FIG. Is positioned at the specified height. Then, before the base insulator 10a is cured, the discharge preventing insulator 10b is applied so as to cover the electric field concentration portion 9b.

以上のように構成した本実施の形態５における半導体装置１０５によれば、実施の形態１の半導体装置１０１が奏する効果を得ることができるのは勿論であるが、半導体装置１０１に比べてさらに導電物１３からの放電を抑制でき、長寿命化及び絶縁信頼性の向上を図ることができる。   According to the semiconductor device 105 according to the fifth embodiment configured as described above, it is needless to say that the effect exhibited by the semiconductor device 101 according to the first embodiment can be obtained, but is more conductive than the semiconductor device 101. The discharge from the object 13 can be suppressed, and the life can be extended and the insulation reliability can be improved.

実施の形態６．
実施の形態１から実施の形態５までの構造では、説明したように、ベース用絶縁物１０ａ、導電物１３、放電防止用絶縁物１０ｂをこの順に重ねていく製造方法を採っている。しかしながら、ベース用絶縁物１０ａ及び放電防止用絶縁物１０ｂの塗布及び硬化を考慮した製造プロセスでは、工程が増すとともに、製造のバラつきが生じる可能性もある。
そこで本実施の形態６では、ベース用絶縁物１０ａ、放電防止用絶縁物１０ｂ、及び導電物１３の役割を有し、これらを一体的に形成した電界緩和部材を、絶縁基板３とは別に予め作製しておき、絶縁基板３に対して電界緩和部材を接着するだけで済むようにしている。Embodiment 6 FIG.
In the structures from the first embodiment to the fifth embodiment, as described, a manufacturing method is employed in which the base insulator 10a, the conductor 13, and the discharge preventing insulator 10b are stacked in this order. However, in the manufacturing process in which the application and curing of the base insulator 10a and the discharge preventing insulator 10b are taken into account, the number of steps may increase and manufacturing may vary.
Therefore, in the sixth embodiment, the electric field relaxation member having the role of the base insulator 10a, the discharge preventing insulator 10b, and the conductor 13 and integrally forming them is separately provided separately from the insulating substrate 3. The electric field relaxation member is simply bonded to the insulating substrate 3 in advance.

図１３には、そのような電界緩和部材２５を用いて作製した、本実施の形態６における半導体装置１０６を示している。また、図１４には、電界緩和部材２５の拡大断面を示している。電界緩和部材２５において、細長い金属導体２０が実施の形態１〜５にて説明した導電物１３に相当し、金属導体２０の周囲の絶縁被膜２１が実施の形態１〜５にて説明したベース用絶縁物１０ａ及び放電防止用絶縁物１０ｂに相当する。絶縁被膜２１は、高電界が加わるため、絶縁耐圧の高いエポキシ系樹脂などを用いる。また、金属導体２０に対しては、電極２との導通のための導線１８が繋がっている。図１４に示す形状では、設置の容易さを考慮して、絶縁被膜２１の表面は、平らに形成しているが、例えば円形状等でもよい。   FIG. 13 shows a semiconductor device 106 according to the sixth embodiment manufactured using such an electric field relaxation member 25. FIG. 14 shows an enlarged cross section of the electric field relaxation member 25. In the electric field relaxation member 25, the elongated metal conductor 20 corresponds to the conductor 13 described in the first to fifth embodiments, and the insulating coating 21 around the metal conductor 20 is for the base described in the first to fifth embodiments. It corresponds to the insulator 10a and the discharge preventing insulator 10b. Since the high electric field is applied to the insulating coating 21, an epoxy resin having a high withstand voltage is used. Further, a conductive wire 18 for conduction with the electrode 2 is connected to the metal conductor 20. In the shape shown in FIG. 14, the surface of the insulating coating 21 is formed flat in consideration of ease of installation, but may be a circular shape or the like, for example.

上述のように別途作製された電界緩和部材２５は、図１３に示すように、回路電極２に隣接させて絶縁基板３の主面３ａに、接着剤２３により接着される。接着剤２３には電界が加わるため、エポキシ系樹脂などの耐圧の高いものを用いる。接着後、あるいは接着と同時に、金属導体２０から延びる導線１８を回路電極２に接続する。その後、全体が絶縁封止材７にて封止される。   The electric field relaxation member 25 separately manufactured as described above is bonded to the main surface 3a of the insulating substrate 3 with an adhesive 23 adjacent to the circuit electrode 2 as shown in FIG. Since an electric field is applied to the adhesive 23, an adhesive having a high pressure resistance such as an epoxy resin is used. After bonding or simultaneously with bonding, the conductive wire 18 extending from the metal conductor 20 is connected to the circuit electrode 2. Thereafter, the whole is sealed with an insulating sealing material 7.

以上のように構成した本実施の形態６における半導体装置１０６によれば、実施の形態１の半導体装置１０１が奏する効果を得ることができるのは勿論であるが、電界緩和に必要な導電物を絶縁物で覆った電界緩和部材２５を予め作製しておくことで、半導体装置の製造を簡易化し、かつ製造のバラツキを低減することが可能となる。   According to the semiconductor device 106 in the sixth embodiment configured as described above, it is a matter of course that the effect exhibited by the semiconductor device 101 in the first embodiment can be obtained. By preparing the electric field relaxation member 25 covered with an insulator in advance, it becomes possible to simplify the manufacture of the semiconductor device and reduce the manufacturing variation.

実施の形態７．
図１５及び図１６に実施の形態７における半導体装置１０７の構造を示す。この半導体装置１０７は、実施の形態１における半導体装置１０１の変形例に相当する。
本実施の形態における半導体装置１０７では、絶縁基板３の主面３ａには電極２が接合されているが、主面３ａに対向する裏面は電極を介さずに直接に放熱板６に接合される構造を有する。このような半導体装置１０７においてベース用絶縁物１０ａは、実施の形態１の場合と同様に絶縁基板３の主面３ａに塗布され、さらに絶縁基板３の端部側面３ｃを覆い放熱板６の上面までも覆って塗布される。また、ベース用絶縁物１０ａには導電物１３が形成され、さらに放電防止用絶縁物１０ｂが導電物１３の反回路電極側端部３５を覆い塗布されている。Embodiment 7 FIG.
15 and 16 show the structure of the semiconductor device 107 according to the seventh embodiment. This semiconductor device 107 corresponds to a modification of the semiconductor device 101 in the first embodiment.
In the semiconductor device 107 in the present embodiment, the electrode 2 is bonded to the main surface 3a of the insulating substrate 3, but the back surface facing the main surface 3a is directly bonded to the heat sink 6 without passing through the electrode. It has a structure. In such a semiconductor device 107, the base insulator 10 a is applied to the main surface 3 a of the insulating substrate 3 as in the first embodiment, and further covers the end side surface 3 c of the insulating substrate 3 and the upper surface of the heat sink 6. It is also applied to cover. In addition, a conductive material 13 is formed on the base insulator 10 a, and a discharge preventing insulator 10 b is applied so as to cover the end portion 35 on the side opposite to the circuit electrode of the conductive material 13.

このように構成される本実施の形態の半導体装置１０７では、絶縁基板３と放熱板６との間には隙間がないため、ベース用絶縁物１０ａは、絶縁基板３から放熱板６に至るまで容易に塗布することが可能である。これにより導電物１３と放熱板６との間における絶縁破壊経路４０（図１６）に対して、放電を遮るようにベース用絶縁物１０ａを設置できるため、絶縁耐圧を向上することができる。   In the semiconductor device 107 of the present embodiment configured as described above, since there is no gap between the insulating substrate 3 and the heat sink 6, the base insulator 10 a extends from the insulating substrate 3 to the heat sink 6. It can be easily applied. Thereby, since the base insulator 10a can be installed so as to block the discharge with respect to the dielectric breakdown path 40 (FIG. 16) between the conductor 13 and the heat sink 6, the withstand voltage can be improved.

上述した各実施の形態を組み合わせた構成を採ることも可能であり、また、異なる実施の形態に示される構成部分同士を組み合わせることも可能である。   It is also possible to adopt a configuration in which the above-described embodiments are combined, and it is also possible to combine components shown in different embodiments.

本発明は、添付図面を参照しながら好ましい実施形態に関連して充分に記載されているが、この技術の熟練した人々にとっては種々の変形や修正は明白である。そのような変形や修正は、添付した請求の範囲による本発明の範囲から外れない限りにおいて、その中に含まれると理解されるべきである。
又、２０１４年５月８日に出願された、日本国特許出願Ｎｏ．特願２０１４−９６８０２号の明細書、図面、特許請求の範囲、及び要約書の開示内容の全ては、参考として本明細書中に編入されるものである。Although the present invention has been fully described in connection with preferred embodiments with reference to the accompanying drawings, various variations and modifications will be apparent to those skilled in the art. Such changes and modifications are to be understood as being included therein, so long as they do not depart from the scope of the present invention according to the appended claims.
In addition, Japanese Patent Application No. The entire contents of the specification, drawings, claims, and abstract of Japanese Patent Application No. 2014-96802 are incorporated herein by reference.

２ 回路電極、３ 絶縁基板、１０ａ ベース用絶縁物、１０ｂ 放電防止用絶縁物、 １３ 導電物、１７ 放電、２３ 接着剤、２５ 電界緩和部材、 ３２ 隙間、３５ 反回路電極側端部、３７ 回路電極側端部、４０ 絶縁破壊経路、 １０１〜１０６ 半導体装置。   2 Circuit electrodes, 3 Insulating substrate, 10a Base insulator, 10b Discharge prevention insulator, 13 Conductor, 17 Discharge, 23 Adhesive, 25 Electric field relaxation member, 32 Gap, 35 Anti-circuit electrode side end, 37 Circuit Electrode side end, 40 dielectric breakdown path, 101-106 semiconductor device.

Claims (9)

回路電極を主面に接合した絶縁基板と、
上記回路電極に隣接して上記主面に形成したベース用絶縁物と、
ベース用絶縁物上に形成され上記回路電極と同電位とした導電物と、
上記導電物において上記回路電極とは反対側に位置する反回路電極側端部を覆う放電防止用絶縁物と、
を備え、
上記ベース用絶縁物及び上記導電物と、上記回路電極との間には隙間を有する、
ことを特徴とする半導体装置。 An insulating substrate having a circuit electrode bonded to the main surface;
A base insulator formed on the main surface adjacent to the circuit electrode;
A conductor formed on the base insulator and having the same potential as the circuit electrode;
An insulator for preventing discharge covering the opposite end of the circuit electrode on the side opposite to the circuit electrode in the conductive material;
Equipped with a,
There is a gap between the base insulator and the conductive material and the circuit electrode.
A semiconductor device. 上記ベース用絶縁物と上記放電防止用絶縁物とは同一材料である、請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the base insulator and the discharge preventing insulator are made of the same material. 上記ベース用絶縁物と上記放電防止用絶縁物は樹脂である、請求項１又は２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the base insulator and the discharge preventing insulator are resin. 上記導電物において回路電極側に位置する回路電極側端部に対して上記反回路電極側端部は、上記絶縁基板の厚み方向において上記絶縁基板から離れて上側に位置する、請求項１から３のいずれか１項に記載の半導体装置。 The counter circuit electrode side end portion with respect to the circuit electrode-side end portion located on the circuit electrode side in the conductive material, located on the upper side away from the insulating substrate in the thickness direction of the insulating substrate, claims 1 to 3 The semiconductor device according to any one of the above. 上記絶縁基板の対向する両面に電極を構成し、その一方の電極は放熱板に接合材で接合されている、請求項１から４のいずれか１項に記載の半導体装置。 Constitute electrodes on opposite sides of the insulating substrate, while the electrodes are joined together through the bonding material to the heat dissipation plate, the semiconductor device according to any one of claims 1 4. 上記絶縁基板の一方面に電極を構成し、上記一方面に対向する上記絶縁基板の他方面は、放熱板に直接に接合されている、請求項１から４のいずれか１項に記載の半導体装置。 The semiconductor according to any one of claims 1 to 4 , wherein an electrode is formed on one surface of the insulating substrate, and the other surface of the insulating substrate facing the one surface is directly bonded to a heat sink. apparatus. 上記ベース用絶縁物は、上記一方面から上記絶縁基板の端部側面を覆いさらに上記放熱板までを覆う、請求項６に記載の半導体装置。 The semiconductor device according to claim 6 , wherein the base insulator covers the end surface of the insulating substrate from the one surface and further covers the heat radiating plate. 絶縁基板の主面に形成した回路電極に隣接して上記主面にベース用絶縁物を配置する工程と、
ベース用絶縁物上に上記回路電極と同電位となる導電物を形成する工程と、
上記導電物において上記回路電極とは反対側に位置する反回路電極側端部を覆って放電防止用絶縁物を配置する工程と、
を備えた半導体装置の製造方法であって、
上記ベース用絶縁物及び上記導電物と、上記回路電極との間には隙間を有する、
ことを特徴とする半導体装置の製造方法。 A step of disposing a base insulator on the main surface adjacent to a circuit electrode formed on the main surface of the insulating substrate;
Forming a conductive material serving as the circuit electrodes at the same potential on the base insulating material,
A step of covering the opposite end of the circuit electrode on the side opposite to the circuit electrode in the conductive material and disposing an insulator for preventing discharge;
A method for manufacturing a semiconductor device comprising:
There is a gap between the base insulator and the conductive material and the circuit electrode.
A method for manufacturing a semiconductor device. 上記ベース用絶縁物、上記導電物、及び上記放電防止用絶縁物を一体的に形成した電界緩和部材を上記絶縁基板とは別に作製し、
上記電界緩和部材を上記回路電極に隣接して上記絶縁基板に接着する、請求項８に記載の半導体装置の製造方法。 An electric field relaxation member formed integrally with the base insulator, the conductor, and the discharge preventing insulator is manufactured separately from the insulating substrate,
The method of manufacturing a semiconductor device according to claim 8 , wherein the electric field relaxation member is bonded to the insulating substrate adjacent to the circuit electrode.
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WO2017104159A1 (en) * 2015-12-16 2017-06-22 三菱電機株式会社 Semiconductor device and method for manufacturing same

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JP2013157598A (en) * 2012-01-06 2013-08-15 Mitsubishi Electric Corp Semiconductor module, semiconductor device using the same, and method for manufacturing semiconductor module

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JP2000340719A (en) * 1999-05-26 2000-12-08 Hitachi Ltd Power semiconductor device
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6081042B1 (en) * 2015-12-16 2017-02-15 三菱電機株式会社 Semiconductor device and manufacturing method thereof
WO2017104159A1 (en) * 2015-12-16 2017-06-22 三菱電機株式会社 Semiconductor device and method for manufacturing same

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