JP5766347B2 - Semiconductor module and manufacturing method thereof - Google Patents

Semiconductor module and manufacturing method thereof Download PDF

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JP5766347B2
JP5766347B2 JP2014505966A JP2014505966A JP5766347B2 JP 5766347 B2 JP5766347 B2 JP 5766347B2 JP 2014505966 A JP2014505966 A JP 2014505966A JP 2014505966 A JP2014505966 A JP 2014505966A JP 5766347 B2 JP5766347 B2 JP 5766347B2
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circuit electrode
semiconductor module
layer
insulating
dielectric layer
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JPWO2013140663A1 (en
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厚 山竹
厚 山竹
塩田　裕基
裕基 塩田
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

本発明は、半導体モジュール及びその製造方法に関し、特に高電圧で使用される半導体モジュールの電界緩和構造に関するものである。   The present invention relates to a semiconductor module and a manufacturing method thereof, and more particularly to an electric field relaxation structure of a semiconductor module used at a high voltage.

電力変換機器等に広く用いられているパワー半導体モジュールは、半導体モジュールの中でも印加電圧が高く、半導体基板端等において電界集中による局所放電が生じやすい。その結果、パワー半導体素子の破壊や誤動作を引き起こすことがあるため、電界集中を緩和し、局所放電を抑制する構造が求められている。   A power semiconductor module widely used in power conversion equipment or the like has a high applied voltage among the semiconductor modules, and local discharge due to electric field concentration tends to occur at the semiconductor substrate end or the like. As a result, the power semiconductor element may be destroyed or malfunctioned, so that a structure that reduces electric field concentration and suppresses local discharge is required.

先行技術では、電界集中による局所放電を抑制するための構造として、半導体基板端の近傍において最も電界集中が生じやすい回路電極の下端部分を削り込み、電界集中を抑制する手法が提案されている。例えば特許文献１では、絶縁基板上に設けられた電気回路パターンの導体層端部が緩やかな曲線となるように、Ｒ加工、Ｃ面加工、あるいは段差加工を施した回路基板が示されている。このような加工により、電気回路パターンの導体層と基板との接合面の端部が、その回路パターンの導体層の最外周端部より内側に入り込んだ断面構造となっている。   In the prior art, as a structure for suppressing local discharge due to electric field concentration, a technique for suppressing electric field concentration by cutting the lower end portion of a circuit electrode where electric field concentration is most likely to occur in the vicinity of the edge of a semiconductor substrate has been proposed. For example, Patent Document 1 discloses a circuit board that has been subjected to R processing, C surface processing, or step processing so that a conductor layer end portion of an electric circuit pattern provided on an insulating substrate has a gentle curve. . By such processing, the end portion of the joint surface between the conductor layer of the electric circuit pattern and the substrate has a cross-sectional structure in which it enters inside the outermost peripheral end portion of the conductor layer of the circuit pattern.

また、その他の電界緩和構造として、回路電極の上端部に導体を突出させるように付加することにより、電界緩和の効果を得る手法もある。この方法では、突出した高電位の導体端部に高電界が発生する。   As another electric field relaxation structure, there is a method of obtaining an electric field relaxation effect by adding a conductor so as to protrude from the upper end portion of the circuit electrode. In this method, a high electric field is generated at the protruding end portion of the high potential conductor.

特開平９−１３５０５７号公報Japanese Patent Laid-Open No. 9-135057

しかしながら、特許文献１に提示されたような回路電極の下端部分を削り込む方法では、高精度な微細加工を必要とし、工程が複雑になる。また、パワー半導体モジュールの絶縁封止材として使用されるシリコーンゲルは高温で欠陥が発生し易く、特に応力の集中する角部で剥離が起こり易い。このため、回路電極の上端部に導体を突出させる方法では、絶縁封止材の剥離が発生した場合、突出した高電位の導体端部で放電が発生する可能性が高い。   However, the method of cutting the lower end portion of the circuit electrode as disclosed in Patent Document 1 requires high-precision fine processing, and the process becomes complicated. Moreover, the silicone gel used as the insulating sealing material of the power semiconductor module is liable to generate defects at high temperatures, and is particularly susceptible to peeling at corners where stress is concentrated. For this reason, in the method in which the conductor protrudes from the upper end portion of the circuit electrode, when the insulating sealing material is peeled off, there is a high possibility that discharge occurs at the protruding high potential conductor end portion.

この発明は、上記問題点に鑑み、回路電極の電界集中を緩和し、局所放電を抑制することが可能な半導体モジュールを得ること目的とする。   In view of the above problems, an object of the present invention is to obtain a semiconductor module that can alleviate electric field concentration of a circuit electrode and suppress local discharge.

また、回路電極の電界集中を緩和し、局所放電を抑制することが可能な半導体モジュールの製造方法を提供することを目的とする。   It is another object of the present invention to provide a method for manufacturing a semiconductor module that can alleviate electric field concentration of circuit electrodes and suppress local discharge.

本発明に係る半導体モジュールは、絶縁基板上に設けられた回路電極と半導体素子、及びこれらを覆う絶縁封止材を備えた半導体モジュールであって、絶縁基板上に回路電極の周縁に沿って設けられ、回路電極の端部と同じ厚さを有し、その端部が回路電極の端部と段差なく接合された絶縁体層と、回路電極と絶縁体層の接合面に近接する回路電極上及び絶縁体層上のいずれか一方に設けられた誘電体層を備えたものである。 A semiconductor module according to the present invention is a semiconductor module provided with a circuit electrode and a semiconductor element provided on an insulating substrate, and an insulating sealing material covering them, and is provided on the insulating substrate along the periphery of the circuit electrode. An insulating layer having the same thickness as the end portion of the circuit electrode, the end portion being joined to the end portion of the circuit electrode without a step, and a circuit electrode adjacent to the joining surface of the circuit electrode and the insulating layer. And a dielectric layer provided on one of the insulator layers.

また、本発明に係る半導体モジュールの製造方法は、回路電極が形成された絶縁基板上に回路電極の端部を起点として絶縁性樹脂を塗布し、その端部が回路電極の端部と接合された絶縁体層を形成する第１の工程と、第１の工程に続いて、回路電極と絶縁体層の接合面を覆うように回路電極上及び絶縁体層上に跨る誘電体層を形成する第２の工程を含むものである。   Also, in the method for manufacturing a semiconductor module according to the present invention, an insulating resin is applied to an insulating substrate on which circuit electrodes are formed, starting from the ends of the circuit electrodes, and the ends are joined to the ends of the circuit electrodes. The first step of forming the insulating layer, and the dielectric layer straddling the circuit electrode and the insulating layer so as to cover the bonding surface of the circuit electrode and the insulating layer are formed following the first step. A second step is included.

本発明に係る半導体モジュールによれば、絶縁基板上に回路電極の周縁に沿って設けられた絶縁体層と、回路電極と絶縁体層の接合面に近接する回路電極上及び絶縁体層上のいずれか一方に設けられた誘電体層を備えることにより、回路電極端部における電界集中を緩和し、局所放電を抑制することが可能である。 According to the semiconductor module of the present invention, the insulating layer provided on the insulating substrate along the periphery of the circuit electrode, the circuit electrode adjacent to the bonding surface of the circuit electrode and the insulating layer, and the insulating layer By providing the dielectric layer provided on either one, it is possible to alleviate electric field concentration at the end of the circuit electrode and suppress local discharge.

また、本発明に係る半導体モジュールの製造方法によれば、回路電極端部における電界集中を緩和し、局所放電を抑制することが可能な半導体モジュールを、容易に製造することが可能である。
この発明の上記以外の目的、特徴、観点及び効果は、図面を参照する以下のこの発明の詳細な説明から、さらに明らかになるであろう。 Moreover, according to the manufacturing method of the semiconductor module which concerns on this invention, it is possible to manufacture easily the semiconductor module which can ease the electric field concentration in a circuit electrode edge part and can suppress a local discharge.
Other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention with reference to the drawings.

本発明の実施の形態１に係るパワー半導体基板を示す平面模式図である。It is a plane schematic diagram which shows the power semiconductor substrate which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係るパワー半導体モジュールを示す断面模式図である。It is a cross-sectional schematic diagram which shows the power semiconductor module which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係るパワー半導体モジュールの端部を示す拡大断面図である。It is an expanded sectional view which shows the edge part of the power semiconductor module which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係るパワー半導体モジュールの端部を示す拡大断面図である。It is an expanded sectional view which shows the edge part of the power semiconductor module which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係るパワー半導体モジュールの半導体基板端部における電界強度と誘電体層の長さｃの関係を示す図である。It is a figure which shows the relationship between the electric field strength in the semiconductor substrate edge part of the power semiconductor module which concerns on Embodiment 1 of this invention, and the length c of a dielectric material layer. 本発明の実施の形態１に係るパワー半導体モジュールの半導体基板端部における電界強度と誘電体層の長さａの関係を示す図である。It is a figure which shows the relationship between the electric field strength in the semiconductor substrate edge part of the power semiconductor module which concerns on Embodiment 1 of this invention, and the length a of a dielectric material layer. 本発明の実施の形態１に係るパワー半導体モジュールの半導体基板端部における電界強度と誘電体層の厚さの関係を示す図である。It is a figure which shows the relationship between the electric field strength in the semiconductor substrate edge part of the power semiconductor module which concerns on Embodiment 1 of this invention, and the thickness of a dielectric material layer. 本発明の実施の形態１に係るパワー半導体モジュールの半導体基板端部における電界強度と誘電体層の誘電率の関係を示す図である。It is a figure which shows the relationship between the electric field strength in the semiconductor substrate edge part of the power semiconductor module which concerns on Embodiment 1 of this invention, and the dielectric constant of a dielectric material layer. 本発明の実施の形態１に係るパワー半導体モジュールの半導体基板端部における電界強度と誘電体層の誘電率の関係を示す図である。It is a figure which shows the relationship between the electric field strength in the semiconductor substrate edge part of the power semiconductor module which concerns on Embodiment 1 of this invention, and the dielectric constant of a dielectric material layer. 本発明の実施の形態２に係るパワー半導体モジュールの端部を示す拡大断面図である。It is an expanded sectional view which shows the edge part of the power semiconductor module which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係るパワー半導体基板における回路電極の配置を示す平面模式図である。It is a plane schematic diagram which shows arrangement | positioning of the circuit electrode in the power semiconductor substrate which concerns on Embodiment 3 of this invention. 本発明の実施の形態３に係るパワー半導体モジュールにおける絶縁体層と誘電体層の配置を説明する図である。It is a figure explaining arrangement | positioning of the insulator layer and dielectric material layer in the power semiconductor module which concerns on Embodiment 3 of this invention.

以下に、本発明を実施するための実施の形態１〜３について、図面に基づいて説明する。なお、実施の形態１〜３において、半導体基板とは、絶縁基板上に回路電極を形成し、さらに１個または複数の半導体素子を実装したものである。また、半導体モジュールとは、半導体基板に接続端子、放熱板等を取り付け、単独で機能を有する電子部品の状態としたものである。   Embodiments 1 to 3 for carrying out the present invention will be described below with reference to the drawings. In the first to third embodiments, the semiconductor substrate is obtained by forming a circuit electrode on an insulating substrate and mounting one or more semiconductor elements. In addition, the semiconductor module is obtained by attaching a connection terminal, a heat radiating plate, and the like to a semiconductor substrate so as to be an electronic component having a function alone.

また、パワー半導体モジュールとは、絶縁基板上に回路電極を形成し、さらに１個または複数のパワー半導体素子を実装してパワー半導体基板を得て、このパワー半導体基板を封止樹脂に浸漬し、接続端子等を取り付け、パッケージした状態を示している。さらに、半導体モジュール、パワー半導体モジュールを、１個または複数個用いて単独で操作、使用できるようにしたものを、それぞれ、半導体装置、パワー半導体装置と呼ぶ。   In addition, the power semiconductor module is formed by forming circuit electrodes on an insulating substrate, and further mounting one or more power semiconductor elements to obtain a power semiconductor substrate, and immersing the power semiconductor substrate in a sealing resin, A connection terminal and the like are attached and packaged. Further, one or a plurality of semiconductor modules and power semiconductor modules that can be operated and used independently are referred to as a semiconductor device and a power semiconductor device, respectively.

以下の実施の形態１〜３では、半導体モジュールのうち特に高電圧を印加するパワー半導体モジュールについて説明するが、本発明は、パワー半導体モジュールよりも耐圧が低い通常の半導体素子を用いた半導体モジュールに適用した場合でも同様の効果を奏する。すなわち、通常の半導体素子を用いた半導体モジュールであっても、小型化により高電界となる場合があり、本発明の適用により基板端近傍での電界集中、局所放電を安定して抑制し、小型で信頼性の高い半導体モジュールが得られるものである。   In the following first to third embodiments, a power semiconductor module that applies a high voltage among semiconductor modules will be described. However, the present invention is applied to a semiconductor module using a normal semiconductor element having a lower withstand voltage than the power semiconductor module. Even when applied, the same effect is achieved. That is, even a semiconductor module using a normal semiconductor element may have a high electric field due to downsizing, and the application of the present invention stably suppresses electric field concentration and local discharge near the edge of the substrate. Thus, a highly reliable semiconductor module can be obtained.

実施の形態１．
図１は、本発明の実施の形態１に係るパワー半導体素子を実装したパワー半導体基板を示す平面模式図である。また、図２は、本実施の形態１に係るパワー半導体モジュールを示す断面模式図、図３は、本実施の形態１に係るパワー半導体モジュールの端部を示す拡大断面図である。なお、図中、同一部分には同一符号を付している。 Embodiment 1 FIG.
FIG. 1 is a schematic plan view showing a power semiconductor substrate on which the power semiconductor element according to Embodiment 1 of the present invention is mounted. 2 is a schematic cross-sectional view showing the power semiconductor module according to the first embodiment, and FIG. 3 is an enlarged cross-sectional view showing an end portion of the power semiconductor module according to the first embodiment. In addition, in the figure, the same code | symbol is attached | subjected to the same part.

図１に示すように、パワー半導体基板１は、回路パターンを形成した回路電極２ａが絶縁基板３の表面に形成されている。また、絶縁基板３の裏面には、回路電極２ｂ（図１では図示せず）が形成されている。回路電極２ａ上には、例えば４個のパワー半導体素子４が実装されている。本実施の形態１では、絶縁基板３は絶縁性セラミックである窒化アルミニウムからなり、回路電極２ａ、２ｂは銅箔によって形成されている。   As shown in FIG. 1, the power semiconductor substrate 1 has a circuit electrode 2 a on which a circuit pattern is formed on the surface of an insulating substrate 3. A circuit electrode 2b (not shown in FIG. 1) is formed on the back surface of the insulating substrate 3. For example, four power semiconductor elements 4 are mounted on the circuit electrode 2a. In the first embodiment, the insulating substrate 3 is made of aluminum nitride, which is an insulating ceramic, and the circuit electrodes 2a and 2b are formed of copper foil.

また、パワー半導体モジュール５は、図２に示すように、パワー半導体基板１の裏面をはんだ６によりアルミニウムからなる放熱用の金属ベース基板７に取り付け、さらに、樹脂からなるケース８でパワー半導体基板１の全面を覆い、シリコーンゲルからなる絶縁封止材９にパワー半導体基板１を浸漬して得られる。   In addition, as shown in FIG. 2, the power semiconductor module 5 is attached to the heat radiating metal base substrate 7 made of aluminum by solder 6 and the power semiconductor substrate 1 is covered with a case 8 made of resin. The power semiconductor substrate 1 is dipped in an insulating sealing material 9 made of silicone gel.

パワー半導体基板１を外部回路と接続する接続端子（図示せず）は、予めケース８の外部に取り出されており、この接続端子は他の電子回路等と接続される。なお、絶縁基板３の表面に形成された回路電極２ａ上には、パワー半導体素子４が実装されているので、パワー半導体素子４の動作に応じて高電圧が印加される。一方、絶縁基板３の裏面に形成された回路電極２ｂは、はんだ６を介して金属ベース基板７に接続されているので、金属ベース基板７と電気的に接続され同電位となっている。   A connection terminal (not shown) for connecting the power semiconductor substrate 1 to an external circuit is taken out of the case 8 in advance, and this connection terminal is connected to another electronic circuit or the like. Since the power semiconductor element 4 is mounted on the circuit electrode 2 a formed on the surface of the insulating substrate 3, a high voltage is applied according to the operation of the power semiconductor element 4. On the other hand, since the circuit electrode 2b formed on the back surface of the insulating substrate 3 is connected to the metal base substrate 7 via the solder 6, it is electrically connected to the metal base substrate 7 and has the same potential.

図２中、Ａで示す点線枠内の領域を拡大した拡大断面図を図３に示す。本実施の形態１では、絶縁基板３上に、回路電極２ａの周縁に沿って、シリコーンゴムからなる絶縁体層１０を設けている。また、絶縁体層１０の上には、絶縁体層１０よりも誘電率の高い無機材料からなる誘電体層１１を設けている。本実施の形態１では、誘電体層１１として、窒化アルミニウム等のセラミックを用いている（なお、図２では、絶縁体層１０及び誘電体層１１は図示を省略している）。   FIG. 3 shows an enlarged cross-sectional view in which a region within a dotted frame indicated by A in FIG. 2 is enlarged. In the first embodiment, the insulating layer 10 made of silicone rubber is provided on the insulating substrate 3 along the periphery of the circuit electrode 2a. A dielectric layer 11 made of an inorganic material having a dielectric constant higher than that of the insulator layer 10 is provided on the insulator layer 10. In the first embodiment, ceramic such as aluminum nitride is used as the dielectric layer 11 (note that the insulator layer 10 and the dielectric layer 11 are not shown in FIG. 2).

図３に示すように、絶縁体層１０は、回路電極２ａの端部と同じ厚さを有し、回路電極２ａの端部と段差なく接合されている。誘電体層１１は、回路電極２ａと絶縁体層１０の接合面を覆うように回路電極２ａ上及び絶縁体層１０上に跨って設けられている。なお、誘電体層１１は、回路電極２ａと絶縁体層１０の接合面に近接する回路電極２ａ上及び絶縁体層１０上のいずれか一方にのみ配置しても良い。ただし、回路電極２ａと絶縁体層１０の両方に跨って配置した方が、より高い電界緩和効果を得られるため望ましい。   As shown in FIG. 3, the insulator layer 10 has the same thickness as the end of the circuit electrode 2a, and is joined to the end of the circuit electrode 2a without a step. The dielectric layer 11 is provided across the circuit electrode 2a and the insulator layer 10 so as to cover the joint surface between the circuit electrode 2a and the insulator layer 10. The dielectric layer 11 may be disposed only on one of the circuit electrode 2a and the insulator layer 10 adjacent to the joint surface between the circuit electrode 2a and the insulator layer 10. However, it is desirable to arrange the circuit electrode 2a and the insulator layer 10 so as to obtain a higher electric field relaxation effect.

次に、本実施の形態１に係る半導体モジュールの製造方法について説明する。まず、回路電極２ａが形成された絶縁基板３上に、回路電極２ａの端部を起点として絶縁性樹脂を塗布し、その端部が回路電極２ａの端部と接合された絶縁体層１０を形成する（第１の工程）。絶縁体層１０を構成する絶縁性樹脂としては、シリコーン系樹脂、ウレタン系樹脂、アクリル系樹脂、エポキシ系樹脂等を用いることができる。   Next, a method for manufacturing the semiconductor module according to the first embodiment will be described. First, an insulating resin is applied on the insulating substrate 3 on which the circuit electrode 2a is formed, starting from the end of the circuit electrode 2a, and the insulating layer 10 is bonded to the end of the circuit electrode 2a. Form (first step). As the insulating resin constituting the insulator layer 10, a silicone resin, a urethane resin, an acrylic resin, an epoxy resin, or the like can be used.

第１の工程では、絶縁体層１０を形成する際に、部分放電劣化の原因となるボイドを含まないようにすることが信頼性の観点から重要である。本実施の形態１では、絶縁基板３上に回路電極２ａの端部を起点として絶縁性樹脂を塗布した後、誘電体層１１を形成するため、絶縁性樹脂の塗布に何ら支障がなく、ボイドを含まない絶縁体層１０を容易に形成することができる。   In the first step, when forming the insulator layer 10, it is important from the viewpoint of reliability not to include voids that cause partial discharge deterioration. In the first embodiment, since the dielectric layer 11 is formed after applying the insulating resin on the insulating substrate 3 starting from the end of the circuit electrode 2a, there is no problem in the application of the insulating resin, and there is no void. It is possible to easily form the insulator layer 10 that does not contain.

第１の工程に続いて、回路電極２ａと絶縁体層１０の接合面を覆うように回路電極２ａ上及び絶縁体層１０上に跨る誘電体層１１を形成する（第２の工程）。この第２の工程は、第１の工程で塗布した絶縁性樹脂が硬化する前に実施され、絶縁性樹脂が硬化することにより、誘電体層１１が絶縁体層１０に接着し、固定される。また、回路電極２ａと絶縁体層１０の接合面に段差を生じさせないように、硬化する前の絶縁性樹脂の高さを回路電極２ａの高さより若干高く形成しておき、さらに回路電極２ａ上の誘電体層１１が載る範囲まで絶縁性樹脂を塗布しておく。続いて誘電体層１１を上から押し付けるようにして接着させた後、絶縁性樹脂、すなわち絶縁体層１０を硬化させる。   Subsequent to the first step, the dielectric layer 11 straddling the circuit electrode 2a and the insulator layer 10 is formed so as to cover the bonding surface between the circuit electrode 2a and the insulator layer 10 (second step). This second step is performed before the insulating resin applied in the first step is cured, and the dielectric layer 11 is bonded and fixed to the insulating layer 10 by curing the insulating resin. . Further, the height of the insulating resin before curing is slightly higher than the height of the circuit electrode 2a so as not to cause a step on the joint surface between the circuit electrode 2a and the insulator layer 10, and further on the circuit electrode 2a. The insulating resin is applied to the extent that the dielectric layer 11 is placed. Subsequently, after the dielectric layer 11 is adhered by pressing from above, the insulating resin, that is, the insulating layer 10 is cured.

次に、本実施の形態１に係るパワー半導体モジュール５における回路電極２ａの電界集中緩和効果について、４つの解析、検討を行った結果を図３〜図９を用いて説明する。４つの解析は、半導体基板１の裏面側の回路電極２ｂをはんだ６及び金属ベース基板７を介してグランドに接地すると共に、回路電極２ａに１ｋＶの電圧を印加し、絶縁基板３、絶縁体層１０と接する回路電極２ａの端部である回路電極端部１２（図３及び図４中、白丸で示す）での電界強度を、電界解析により求めた。回路電極端部１２は、絶縁基板３、回路電極２ａ、及び絶縁体層１０が接する三重点であり、電界が最も集中する箇所である。   Next, the results of four analyzes and studies on the electric field concentration relaxation effect of the circuit electrode 2a in the power semiconductor module 5 according to the first embodiment will be described with reference to FIGS. In the four analyses, the circuit electrode 2b on the back surface side of the semiconductor substrate 1 is grounded via the solder 6 and the metal base substrate 7, and a voltage of 1 kV is applied to the circuit electrode 2a. The electric field strength at the circuit electrode end 12 (indicated by white circles in FIGS. 3 and 4), which is the end of the circuit electrode 2a in contact with 10, was obtained by electric field analysis. The circuit electrode end portion 12 is a triple point where the insulating substrate 3, the circuit electrode 2a, and the insulator layer 10 are in contact with each other, and is where the electric field is most concentrated.

また、絶縁基板３として、厚さ０．６ｍｍ、比誘電率が約９の窒化アルミニウムを用い、誘電体層１１として、厚さ０．５ｍｍ、比誘電率が約９の窒化アルミニウムを用いた。ただし、第３の解析では誘電体層１１の厚さを、第４の解析では誘電体層１１の材質を変えている。さらに、絶縁体層１０及び絶縁封止材９として、いずれも比誘電率が約３のシリコーン系樹脂を硬化したものを用いた。回路電極２ａ及び絶縁体層１０の厚さｄは、０．２ｍｍと０．４ｍｍの２種類を用意した。また、裏面側の回路電極２ｂの厚さは０．４ｍｍ、はんだ６の厚さは０．１ｍｍ、絶縁基板３の回路電極端部１２から絶縁基板３の端部までの沿面距離は２ｍｍとした。   In addition, aluminum nitride having a thickness of 0.6 mm and a relative dielectric constant of about 9 was used as the insulating substrate 3, and aluminum nitride having a thickness of 0.5 mm and a relative dielectric constant of about 9 was used as the dielectric layer 11. However, the thickness of the dielectric layer 11 is changed in the third analysis, and the material of the dielectric layer 11 is changed in the fourth analysis. Furthermore, as the insulator layer 10 and the insulating sealing material 9, those obtained by curing a silicone resin having a relative dielectric constant of about 3 were used. Two thicknesses of 0.2 mm and 0.4 mm were prepared for the thickness d of the circuit electrode 2 a and the insulator layer 10. The thickness of the circuit electrode 2b on the back surface side is 0.4 mm, the thickness of the solder 6 is 0.1 mm, and the creeping distance from the circuit electrode end 12 of the insulating substrate 3 to the end of the insulating substrate 3 is 2 mm. .

まず、第１の解析では、図４に示すように、誘電体層１１を、絶縁基板３の端部を基準として、回路電極２ａ方向へ長さｃに形成した場合の、回路電極端部１２の電界強度を計算した。すなわちｃ＝０ｍｍとは誘電体層１１がない状態であり、ｃ＝２ｍｍの時、誘電体層１１の端部が回路電極２ａと絶縁体層１０の接合面と同じ位置となる。   First, in the first analysis, as shown in FIG. 4, when the dielectric layer 11 is formed with a length c in the direction of the circuit electrode 2a with the end of the insulating substrate 3 as a reference, the circuit electrode end 12 is formed. The electric field strength of was calculated. That is, c = 0 mm is a state in which the dielectric layer 11 is not present, and when c = 2 mm, the end of the dielectric layer 11 is at the same position as the joint surface between the circuit electrode 2 a and the insulator layer 10.

第１の解析の結果を図５に示す。図５において、横軸は誘電体層１１の長さｃ（ｍｍ）、縦軸は回路電極端部１２の電界強度（ｋＶ／ｍｍ）であり、図中、黒丸はｄ＝０．２ｍｍ、白丸はｄ＝０．４ｍｍの時の電界強度を示している。   The result of the first analysis is shown in FIG. In FIG. 5, the horizontal axis represents the length c (mm) of the dielectric layer 11, and the vertical axis represents the electric field strength (kV / mm) of the circuit electrode end 12. In the figure, the black circle represents d = 0.2 mm and the white circle. Indicates the electric field strength when d = 0.4 mm.

図５に示すように、ｃ＝２ｍｍ付近において電界強度が急激に低下していることから、誘電体層１１が回路電極２ａの端部近傍まで接近した時に電界緩和効果が得られている。また、誘電体層１１は、絶縁体層１０上のみでなく、回路電極２ａ上まで跨って設けた方が電界緩和効果は高くなる。従って、誘電体層１１を配置する際には、回路電極２ａ上に少しでも載るようにすることが望ましい。   As shown in FIG. 5, since the electric field strength sharply decreases in the vicinity of c = 2 mm, the electric field relaxation effect is obtained when the dielectric layer 11 approaches the vicinity of the end of the circuit electrode 2a. Moreover, the electric field relaxation effect becomes higher when the dielectric layer 11 is provided not only on the insulator layer 10 but also on the circuit electrode 2a. Accordingly, when the dielectric layer 11 is disposed, it is desirable that the dielectric layer 11 be placed on the circuit electrode 2a even a little.

ただし、ｃ＞２．５ｍｍの領域では電界緩和効果にあまり変化がないことから、誘電体層１１は、回路電極２ａ端部より内側に配置するほど効果があるというものではなく、今回の解析では、回路電極２の端部より０．５ｍｍ内側に配置すると、全体の緩和効果の９５％ほど得られた。また、回路電極２ａ及び絶縁体層１０の厚さｄは、小さい方が電界緩和量は大きくなるという結果が得られた。   However, since there is not much change in the electric field relaxation effect in the region of c> 2.5 mm, the dielectric layer 11 is not so effective that it is arranged inside the end of the circuit electrode 2a. When arranged 0.5 mm inside the end of the circuit electrode 2, about 95% of the total relaxation effect was obtained. In addition, the smaller the thickness d of the circuit electrode 2a and the insulator layer 10, the larger the electric field relaxation amount.

次に、第２の解析では、図３に示すように、回路電極２ａの端部から誘電体層１１の内側端部までの長さｂを０．５ｍｍとし、回路電極２ａの端部から誘電体層１１の外側端部までの長さをａとした場合の、回路電極端部１２の電界強度を計算した。ただし、ａ＜０とは、誘電体層１１が全て回路電極２ａ上に配置されている状態を示している。その他の条件は上記第１の解析と同様である。   Next, in the second analysis, as shown in FIG. 3, the length b from the end of the circuit electrode 2a to the inner end of the dielectric layer 11 is 0.5 mm, and the dielectric from the end of the circuit electrode 2a. The electric field strength of the circuit electrode end 12 was calculated when the length to the outer end of the body layer 11 was a. However, a <0 indicates a state in which the dielectric layer 11 is entirely disposed on the circuit electrode 2a. Other conditions are the same as those in the first analysis.

第２の解析の結果を図６に示す。図６において、横軸は誘電体層１１の長さａ（ｍｍ）、縦軸は回路電極端部１２の電界強度（ｋＶ／ｍｍ）であり、図中、黒丸はｄ＝０．２ｍｍ、白丸はｄ＝０．４ｍｍの時の電界強度を示している。   The result of the second analysis is shown in FIG. In FIG. 6, the horizontal axis represents the length a (mm) of the dielectric layer 11, and the vertical axis represents the electric field strength (kV / mm) of the circuit electrode end portion 12. In the figure, the black circle represents d = 0.2 mm and the white circle. Indicates the electric field strength when d = 0.4 mm.

図６に示すように、ａ＜０であってもわずかに電界緩和効果が得られるが、ａ＞０とした方が電界緩和効果は高い。また、長さａは大きいほど効果があるというものではなく、今回の解析ではａ＝０．５ｍｍで十分な効果が得られた。ただし、電界強度が最小となる長さａの値は、条件によって変動する。   As shown in FIG. 6, even if a <0, a slight electric field relaxation effect can be obtained, but the electric field relaxation effect is higher when a> 0. Further, the larger the length a, the more effective the effect, and in this analysis, a sufficient effect was obtained with a = 0.5 mm. However, the value of the length a that minimizes the electric field strength varies depending on conditions.

第１及び第２の解析の結果から、これらの解析で用いたパワー半導体モジュール５の構造と条件の下では、誘電体層１１（厚さ０．５ｍｍの窒化アルミニウム）を、回路電極２ａ上に０．５ｍｍ、絶縁体層１０上に０．５ｍｍそれぞれ配置すればよく、全体として１．０ｍｍの長さ（幅）があれば良いことになる。従って、誘電体層１１を設置する際には、回路電極２ａの端部に対応する四角い枠状、もしくは４本の棒状の誘電体層１１を設置すればよい。   From the results of the first and second analyses, the dielectric layer 11 (aluminum nitride having a thickness of 0.5 mm) is placed on the circuit electrode 2a under the structure and conditions of the power semiconductor module 5 used in these analyses. It suffices to arrange 0.5 mm and 0.5 mm on the insulator layer 10, respectively, and it is sufficient if the length (width) is 1.0 mm as a whole. Therefore, when the dielectric layer 11 is installed, a rectangular frame shape or four rod-shaped dielectric layers 11 corresponding to the ends of the circuit electrode 2a may be installed.

なお、誘電体層１１の長さａは、最適長（ここでは０．５ｍｍ）より大きく形成されていても良いが、絶縁基板３の端部を越えると電界緩和効果が低下し、基板全体の寸法が大きくなるため、誘電体層１１は絶縁基板３の端部を越えない範囲で形成される。また、絶縁体層１０は、必ずしも絶縁基板３の端部まで形成されている必要はなく、誘電体層１１を設置する範囲に形成されていれば良い。   The length a of the dielectric layer 11 may be larger than the optimum length (here, 0.5 mm). However, if the length of the dielectric layer 11 exceeds the end of the insulating substrate 3, the electric field relaxation effect is reduced, and the entire substrate is reduced. Since the size is increased, the dielectric layer 11 is formed in a range not exceeding the end of the insulating substrate 3. Further, the insulating layer 10 does not necessarily have to be formed up to the end of the insulating substrate 3, and may be formed in a range where the dielectric layer 11 is provided.

次に第３の解析として、ａ＝２．０ｍｍ、ｂ＝０．５ｍｍ、ｄ＝０．４ｍｍとし、誘電体層１１の厚さを変えた場合の電界強度を計算した。その他の条件は上記第１の解析及び第２の解析と同様である。第３の解析の結果を図７に示す。図７において、横軸は誘電体層１１の厚さ（ｍｍ）、縦軸は回路電極端部１２の電界強度（ｋＶ／ｍｍ）である。誘電体層１１の厚さは、大きくなるほど電界分布に影響を与えるため、高い電界緩和効果が得られる。   Next, as a third analysis, electric field strength was calculated when a = 2.0 mm, b = 0.5 mm, and d = 0.4 mm, and the thickness of the dielectric layer 11 was changed. Other conditions are the same as those in the first analysis and the second analysis. The result of the third analysis is shown in FIG. In FIG. 7, the horizontal axis represents the thickness (mm) of the dielectric layer 11, and the vertical axis represents the electric field strength (kV / mm) at the circuit electrode end 12. Since the electric field distribution is affected as the thickness of the dielectric layer 11 increases, a high electric field relaxation effect is obtained.

絶縁封止材９と絶縁体層１０の誘電率は、特に限定するものではないが、半導体基板１近傍での電界集中を抑制する観点からは、絶縁体層１０の誘電率は、絶縁封止材９の誘電率よりも高いことが好ましい。さらに、誘電体層１１の誘電率は、絶縁体層１０よりも高い必要があり、誘電率が高いほど電界緩和効果が高くなる。   The dielectric constants of the insulating sealing material 9 and the insulating layer 10 are not particularly limited, but from the viewpoint of suppressing the electric field concentration in the vicinity of the semiconductor substrate 1, the dielectric constant of the insulating layer 10 is the insulating sealing. It is preferable that the dielectric constant of the material 9 is higher. Furthermore, the dielectric constant of the dielectric layer 11 needs to be higher than that of the insulator layer 10, and the higher the dielectric constant, the higher the electric field relaxation effect.

誘電体層１１の材料として、例えば、アルミナ（比誘電率：約９〜１０）や窒化珪素（比誘電率：約８）等のセラミック材料を用いてもよい。これらの誘電率は窒化アルミニウムに近いため、同程度の電界緩和効果が得られる。他に、例えばガラス（比誘電率：約３．５〜４）を用いた場合には、誘電率が低いため電界緩和効果は低い。マイカ（比誘電率：約６）を用いた場合には、ガラスよりは電界緩和効果が高いが、上記セラミック材料よりは効果は低い。誘電率の高い材料として、例えばジルコニア（比誘電率：３０）や酸化チタン（比誘電率：８３）を使うと、より高い効果が得られる。   As a material of the dielectric layer 11, for example, a ceramic material such as alumina (relative dielectric constant: about 9 to 10) or silicon nitride (relative dielectric constant: about 8) may be used. Since these dielectric constants are close to those of aluminum nitride, the same degree of electric field relaxation effect can be obtained. In addition, for example, when glass (relative dielectric constant: about 3.5 to 4) is used, the electric field relaxation effect is low because the dielectric constant is low. When mica (relative dielectric constant: about 6) is used, the electric field relaxation effect is higher than that of glass, but the effect is lower than that of the ceramic material. For example, when zirconia (relative permittivity: 30) or titanium oxide (relative permittivity: 83) is used as a material having a high permittivity, a higher effect can be obtained.

第４の解析では、誘電体層１１として様々な比誘電率の材料を用いた場合について、第２の解析と同様の計算をした。誘電体層１１の比誘電率以外の条件については、第２の解析と同様である。第４の解析の結果を図８及び図９に示す。図８及び図９において、横軸は誘電体層１１の長さａ（ｍｍ）、縦軸は回路電極端部１２の電界強度（ｋＶ／ｍｍ）であり、図８はｄ＝０．２ｍｍ、図９はｄ＝０．４ｍｍのときの結果を示している。第４の解析の結果から、誘電体層１１の材料として誘電率の低い材料を用いた場合には電界緩和効果が低く、誘電率の高い材料を用いるほど、高い電界緩和効果が得られる。   In the fourth analysis, the same calculation as in the second analysis was performed for the case where various dielectric constant materials were used as the dielectric layer 11. The conditions other than the dielectric constant of the dielectric layer 11 are the same as in the second analysis. The results of the fourth analysis are shown in FIGS. 8 and 9, the horizontal axis represents the length a (mm) of the dielectric layer 11, the vertical axis represents the electric field strength (kV / mm) of the circuit electrode end 12, and FIG. FIG. 9 shows the result when d = 0.4 mm. From the result of the fourth analysis, when a material having a low dielectric constant is used as the material of the dielectric layer 11, the electric field relaxation effect is low, and the higher the dielectric constant material is, the higher the electric field relaxation effect is obtained.

以上のことから、電界緩和効果を高めるための条件として、誘電体層１１を最適位置に配置すること、誘電体層１１の厚さを大きくすること、誘電体層１１の誘電率を高くすること、及び回路電極２ａの厚さを小さくすること、が挙げられる。ただし、誘電体層１１の誘電率を高くしすぎると、誘電体層１１の端部の角に電界が集中しやすくなる。誘電体層１１は導電物ではないため放電は発生し難いが、電界集中を抑えるために角部を丸くする加工を施しておくことが望ましい。   From the above, as conditions for enhancing the electric field relaxation effect, the dielectric layer 11 is disposed at the optimum position, the thickness of the dielectric layer 11 is increased, and the dielectric constant of the dielectric layer 11 is increased. And reducing the thickness of the circuit electrode 2a. However, if the dielectric constant of the dielectric layer 11 is too high, the electric field tends to concentrate on the corners of the end portions of the dielectric layer 11. Since the dielectric layer 11 is not a conductive material, it is difficult for electric discharge to occur. However, in order to suppress electric field concentration, it is desirable to perform processing for rounding corners.

また、絶縁基板３の表面において電界緩和効果を高めすぎると、絶縁基板３の裏面側の回路電極２ｂ端部の電界強度の方が高くなる場合がある。例えば第４の解析において、ｄ＝０．４ｍｍ、εｒ＝８３の場合（図９）、誘電体層の長さａが１ｍｍ以上になると、絶縁基板３の裏面側の回路電極２ｂ端部の電界強度が、表面側の回路電極２ａ端部の電界強度を上回る結果が得られた。このような状態を避けるためには、誘電体層１１の厚さや長さａを、大きくなりすぎないように調整すれば良い。   If the electric field relaxation effect is excessively increased on the surface of the insulating substrate 3, the electric field strength at the end of the circuit electrode 2b on the back surface side of the insulating substrate 3 may be higher. For example, in the fourth analysis, when d = 0.4 mm and εr = 83 (FIG. 9), when the length a of the dielectric layer is 1 mm or more, the electric field at the end of the circuit electrode 2b on the back surface side of the insulating substrate 3 A result in which the strength exceeded the electric field strength at the end of the circuit electrode 2a on the surface side was obtained. In order to avoid such a state, the thickness and length a of the dielectric layer 11 may be adjusted so as not to become too large.

また、誘電体層１１として、絶縁基板３と同質の無機セラミック材料を用いることにより、電界集中部のある領域の絶縁体層１０が、熱膨張係数が同等の絶縁基板３と誘電体層１１に挟まれる構造となる。これにより、絶縁体層１０は、絶縁基板３と誘電体層１１の熱膨張係数の差に起因する形状の変形が起こり難く、剥離等の不良が発生し難い。   Further, by using an inorganic ceramic material of the same quality as that of the insulating substrate 3 as the dielectric layer 11, the insulating layer 10 in a region where the electric field concentration portion is present is changed into the insulating substrate 3 and the dielectric layer 11 having the same thermal expansion coefficient. The structure is sandwiched. As a result, the insulator layer 10 is unlikely to deform due to a difference in thermal expansion coefficient between the insulating substrate 3 and the dielectric layer 11, and defects such as peeling are unlikely to occur.

本実施の形態１の比較例として、誘電体層１１が設けられていない構造、もしくは誘電体層１１ではなく高電位の導体が配置されている構造を想定すると、回路電極または高電位の導体の端部で高電界となりやすい。絶縁封止材９の材料であるシリコーンゲルは、高温動作時に応力の大きくなる角部で剥離等の欠陥が起こりやすく、剥離により露出した導体端部で局所放電が発生する可能性が高くなる。これに対し、本実施の形態１の構造では、絶縁封止材９の剥離が起こった場合でも、誘電体層１１が露出するため、局所放電を抑制することができる。   As a comparative example of the first embodiment, assuming a structure in which the dielectric layer 11 is not provided, or a structure in which a high potential conductor is arranged instead of the dielectric layer 11, a circuit electrode or a high potential conductor It tends to be a high electric field at the edge. Silicone gel, which is the material of the insulating sealing material 9, is liable to cause defects such as peeling at corners where stress increases during high-temperature operation, and the possibility of local discharge occurring at the conductor end exposed by peeling increases. On the other hand, in the structure of the first embodiment, even when the insulating sealing material 9 is peeled off, the dielectric layer 11 is exposed, so that local discharge can be suppressed.

以上のように、本実施の形態１によれば、絶縁基板３上に設けられた回路電極２ａとパワー半導体素子４、及びこれらを覆う絶縁封止材９を備えたパワー半導体モジュール５において、絶縁基板３上の回路電極２ａ周縁部に設けられ、その端部が回路電極２ａの端部と接合された絶縁体層１０と、回路電極２ａと絶縁体層１０の接合面を覆うように回路電極２ａ上及び絶縁体層１０上に跨って設けられた誘電体層１１を備えることにより、回路電極２ａ、特に回路電極端部１２の電界集中を緩和し、局所放電を抑制することが可能である。   As described above, according to the first embodiment, in the power semiconductor module 5 including the circuit electrode 2 a and the power semiconductor element 4 provided on the insulating substrate 3 and the insulating sealing material 9 covering these, The circuit electrode 2a is provided on the peripheral edge of the circuit electrode 2a on the substrate 3, and the end of the insulator layer 10 is joined to the end of the circuit electrode 2a, and the circuit electrode is covered so as to cover the joint surface of the circuit electrode 2a and the insulator layer 10 By providing the dielectric layer 11 provided over 2a and the insulator layer 10, it is possible to alleviate electric field concentration at the circuit electrode 2a, particularly the circuit electrode end 12, and to suppress local discharge. .

また、本実施の形態１に係る半導体モジュールの製造方法によれば、回路電極端部１２における電界集中を緩和し、局所放電を抑制することが可能な信頼性の高い半導体モジュールを、容易に製造することが可能である。   In addition, according to the method for manufacturing a semiconductor module according to the first embodiment, a highly reliable semiconductor module that can alleviate electric field concentration at the circuit electrode end 12 and suppress local discharge is easily manufactured. Is possible.

さらに、本実施の形態１に係る電界緩和構造のパワー半導体モジュール５を備えた例えばインバータ、ＤＣ／ＤＣコンバータ等のパワー半導体装置は、小型化が可能であり、パワー半導体素子４の破壊や誤動作を抑制することが可能である。   Furthermore, the power semiconductor device such as an inverter or a DC / DC converter including the power semiconductor module 5 having the electric field relaxation structure according to the first embodiment can be reduced in size, and the power semiconductor element 4 can be destroyed or malfunctioned. It is possible to suppress.

実施の形態２．
図１０は、本発明の実施の形態２に係る半導体モジュールの端部を示す拡大断面図である。なお、図１０中、図３と同一部分には同一符号を付している。本実施の形態２では、上記実施の形態１と同様に構成されたパワー半導体モジュールにおいて、回路電極２ａの周縁部に、厚さが他の部分よりも小さい段差部を設け、この段差部上に誘電体層１１を設けたものである。 Embodiment 2. FIG.
FIG. 10 is an enlarged cross-sectional view showing an end portion of the semiconductor module according to Embodiment 2 of the present invention. In FIG. 10, the same components as those in FIG. In the second embodiment, in the power semiconductor module configured in the same manner as in the first embodiment, a step portion having a thickness smaller than that of the other portion is provided at the peripheral portion of the circuit electrode 2a, and the step portion is provided on the step portion. A dielectric layer 11 is provided.

上記実施の形態１で説明したように、回路電極２ａ及び絶縁体層１０の厚さｄ（図３参照）が小さいほど、高い電界緩和効果が得られる。このとき、回路電極２ａ全体の厚さが小さくなくてもよく、回路電極２ａ端部の誘電体層１１が設置される部分のみ、厚さが小さくなっていればよい。   As described in the first embodiment, the smaller the thickness d of the circuit electrode 2a and the insulator layer 10 (see FIG. 3), the higher the electric field relaxation effect. At this time, the thickness of the entire circuit electrode 2a may not be small, and only the portion where the dielectric layer 11 at the end of the circuit electrode 2a is installed needs to be thin.

そこで、本実施の形態２では、図１０に示すように、回路電極２ａ端部の表面を、誘電体層１１が配置される長さｂだけ任意の深さに切削し、厚さを小さく形成している。また、回路電極２ａの端部と接合される絶縁体層１０の厚さも同様に小さく形成している。さらに、この厚さの小さい段差部上に、回路電極２ａと絶縁体層１０の接合面を覆うように誘電体層１１を設けている。なお、誘電体層１１は、回路電極２ａと絶縁体層１０の接合面に近接する回路電極２ａ上及び絶縁体層１０上のいずれか一方にのみ配置しても良いが、両方に跨って配置した方が、より高い電界緩和効果を得られるため望ましい。   Therefore, in the second embodiment, as shown in FIG. 10, the surface of the end portion of the circuit electrode 2a is cut to an arbitrary depth by the length b where the dielectric layer 11 is disposed, and the thickness is reduced. doing. Also, the thickness of the insulator layer 10 joined to the end of the circuit electrode 2a is similarly reduced. Furthermore, the dielectric layer 11 is provided on the step portion having the small thickness so as to cover the bonding surface between the circuit electrode 2a and the insulating layer 10. The dielectric layer 11 may be disposed only on one of the circuit electrode 2a and the insulator layer 10 adjacent to the joint surface between the circuit electrode 2a and the insulator layer 10, but is disposed across both. This is desirable because a higher electric field relaxation effect can be obtained.

本実施の形態２によれば、上記実施の形態１と同様の効果に加え、回路電極２ａ端部の誘電体層１１が設置される部分の厚さを小さくすることにより、さらに高い電界緩和効果が得られると共に、誘電体層１１を設置する際の位置決めに微調整を必要とせず、誘電体層１１を正確な位置に容易に設置することができる。   According to the second embodiment, in addition to the same effects as those of the first embodiment, the electric field relaxation effect can be further increased by reducing the thickness of the portion where the dielectric layer 11 at the end of the circuit electrode 2a is installed. In addition, fine adjustment is not required for positioning when the dielectric layer 11 is placed, and the dielectric layer 11 can be easily placed at an accurate position.

実施の形態３．
図１１は、本発明の実施の形態３に係るパワー半導体基板における回路電極の配置を示している（パワー半導体素子４の図示は省略している）。また、図１２は、図１１に示すパワー半導体基板を用いたパワー半導体モジュールにおける絶縁体層と誘電体層の配置を示している。上記実施の形態１（図１参照）では、絶縁基板３の表面に１つの回路電極２ａが形成された例について説明したが、本実施の形態３では、絶縁基板３の表面に複数の回路電極２ｃ、２ｄが形成された例について説明する。 Embodiment 3 FIG.
FIG. 11 shows the arrangement of circuit electrodes on the power semiconductor substrate according to the third embodiment of the present invention (illustration of the power semiconductor element 4 is omitted). FIG. 12 shows an arrangement of the insulator layers and the dielectric layers in the power semiconductor module using the power semiconductor substrate shown in FIG. In the first embodiment (see FIG. 1), the example in which one circuit electrode 2a is formed on the surface of the insulating substrate 3 has been described. In the third embodiment, a plurality of circuit electrodes are formed on the surface of the insulating substrate 3. An example in which 2c and 2d are formed will be described.

図１１に示すように、複数の回路電極２ｃ、２ｄを有するパワー半導体基板を用いたパワー半導体モジュールにおいても、回路電極２ｃ、２ｄの周縁に沿って絶縁体層１０を設け、さらにその上に誘電体層１１を設けることにより、電界緩和効果を得ることができる。その場合、図１２に示すように、回路電極２ｃ、２ｄの端部から絶縁基板３の端部までを覆う絶縁体層１０を形成すると共に、回路電極２ｃと回路電極２ｄの間の領域にも絶縁体層１０を形成する。   As shown in FIG. 11, also in a power semiconductor module using a power semiconductor substrate having a plurality of circuit electrodes 2c and 2d, an insulator layer 10 is provided along the periphery of the circuit electrodes 2c and 2d, and a dielectric is further formed thereon. By providing the body layer 11, an electric field relaxation effect can be obtained. In that case, as shown in FIG. 12, the insulator layer 10 is formed to cover the end of the circuit electrodes 2c and 2d to the end of the insulating substrate 3, and also in the region between the circuit electrode 2c and the circuit electrode 2d. The insulator layer 10 is formed.

また、回路電極２ｃ、２ｄと絶縁体層１０の接合面を覆うように、回路電極２ｃ上と絶縁体層１０上、または回路電極２ｄと絶縁体層１０上に跨る誘電体層１１を設ける。回路電極２ｃと回路電極２ｄの間の領域では、回路電極２ｃ上、絶縁体層１０上、及び回路電極２ｄ上に跨る誘電体層１１を設ける。これにより、互いに対向する回路電極２ｃと回路電極２ｄの端部においても電界緩和効果が得られる。   Further, a dielectric layer 11 is provided over the circuit electrode 2c and the insulator layer 10 or over the circuit electrode 2d and the insulator layer 10 so as to cover the bonding surface between the circuit electrodes 2c and 2d and the insulator layer 10. In a region between the circuit electrode 2c and the circuit electrode 2d, a dielectric layer 11 is provided over the circuit electrode 2c, the insulator layer 10, and the circuit electrode 2d. Thereby, the electric field relaxation effect can be obtained also at the ends of the circuit electrode 2c and the circuit electrode 2d facing each other.

なお、誘電体層１１は、回路電極２ｃ（または回路電極２ｄ）と絶縁体層１０の接合面に近接する回路電極２ｃ（または回路電極２ｄ）上及び絶縁体層１０上のいずれか一方にのみ配置しても良いが、両方に跨って配置した方がより高い電界緩和効果を得られるため望ましい。   The dielectric layer 11 is only on one of the circuit electrode 2c (or circuit electrode 2d) and the insulator layer 10 adjacent to the joint surface between the circuit electrode 2c (or circuit electrode 2d) and the insulator layer 10. Although it may be arranged, it is desirable to arrange it over both because a higher electric field relaxation effect can be obtained.

本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略したりすることが可能である。   Within the scope of the present invention, the present invention can be freely combined with each other, or can be appropriately modified or omitted.

Claims (8)

絶縁基板上に設けられた回路電極と半導体素子、及びこれらを覆う絶縁封止材を備えた半導体モジュールであって、
前記絶縁基板上に前記回路電極の周縁に沿って設けられ、前記回路電極の端部と同じ厚さを有し、その端部が前記回路電極の端部と段差なく接合された絶縁体層と、
前記回路電極と前記絶縁体層の接合面に近接する前記回路電極上及び前記絶縁体層上のいずれか一方に設けられた誘電体層を備えたことを特徴とする半導体モジュール。 A semiconductor module comprising a circuit electrode and a semiconductor element provided on an insulating substrate, and an insulating sealing material covering these,
An insulating layer provided on the insulating substrate along the periphery of the circuit electrode, having the same thickness as the end of the circuit electrode, and the end joined to the end of the circuit electrode without a step; ,
A semiconductor module comprising a dielectric layer provided on one of the circuit electrode and the insulator layer adjacent to a joint surface between the circuit electrode and the insulator layer. 前記絶縁体層の誘電率は、前記絶縁封止材の誘電率よりも高いことを特徴とする請求項１記載の半導体モジュール。 The dielectric constant of the insulator layer, a semiconductor module according to claim 1, wherein the higher than a dielectric constant of the insulating sealing material. 前記誘電体層の誘電率は、前記絶縁体層の誘電率よりも高いことを特徴とする請求項１または請求項２に記載の半導体モジュール。 The dielectric constant of the dielectric layer, a semiconductor module according to claim 1 or claim 2, wherein the higher than a dielectric constant of the insulator layer. 前記誘電体層は、無機材料からなることを特徴とする請求項１から請求項３のいずれか一項に記載の半導体モジュール。 The dielectric layer, a semiconductor module according to any one of claims 1 to 3, characterized in that it consists of an inorganic material. 前記回路電極は、その周縁部に、厚さが他の部分よりも小さい段差部を有し、この段差部上に前記誘電体層を設けたことを特徴とする請求項１から請求項４のいずれか一項に記載の半導体モジュール。 Said circuit electrodes, on its periphery, has a small stepped portion than the other portion thickness, from claim 1, characterized in that a said dielectric layer on the stepped portion of claim 4 The semiconductor module as described in any one. 回路電極が形成された絶縁基板上に前記回路電極の端部を起点として絶縁性樹脂を塗布し、その端部が前記回路電極の端部と接合された絶縁体層を形成する第１の工程、
前記第１の工程に続いて、前記回路電極と前記絶縁体層の接合面を覆うように前記回路電極上及び前記絶縁体層上に跨る誘電体層を形成する第２の工程を含むことを特徴とする半導体モジュールの製造方法。 A first step of applying an insulating resin on the insulating substrate on which the circuit electrode is formed, starting from the end of the circuit electrode, and forming an insulating layer in which the end is joined to the end of the circuit electrode ,
Subsequent to the first step, including a second step of forming a dielectric layer straddling the circuit electrode and the insulator layer so as to cover a joint surface between the circuit electrode and the insulator layer. A method for manufacturing a semiconductor module. 前記第２の工程は、前記第１の工程で塗布した絶縁性樹脂が硬化する前に実施され、前記絶縁性樹脂が硬化することにより、前記第２の工程で形成された前記誘電体層が前記絶縁体層上に固定されることを特徴とする請求項６に記載の半導体モジュールの製造方法。 The second step is performed before the insulating resin applied in the first step is cured, and the dielectric layer formed in the second step is formed by curing the insulating resin. The method of manufacturing a semiconductor module according to claim 6 , wherein the semiconductor module is fixed on the insulator layer. 前記第１の工程において、前記絶縁性樹脂として、シリコーン系樹脂、ウレタン系樹脂、アクリル系樹脂、及びエポキシ系樹脂のいずれかを用いたことを特徴とする請求項６または請求項７に記載の半導体モジュールの製造方法。 In the first step, as the insulating resin, silicone resin, urethane resin, according to claim 6 or claim 7 characterized by using any of acrylic resin, and epoxy resin Manufacturing method of semiconductor module.
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