JP2013080432A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a CPU to acquire time information when a valid edge occurs first, even if valid edges occur multiple times during a monitoring period from start of prescribed monitoring to the time when the CPU performs read processing of a value of a time storage register, in a microcomputer including the time storage register which stores the time information when a valid edge of a specific direction occurs in an input signal.SOLUTION: In a microcomputer, when a value of a capture mode register is set to "1" by a CPU (S101:Y), the capture register updates and stores a value of a free running timer (S102), only if a value of a capture enable register is set to "0" (S104:Y) when an edge of a detection target occurs in an input signal, and the value of the capture enable register changes to "1" from "0" (S103) regardless of software processing, when the update and storage are performed. Also, the value of the capture enable register is rewritable to "0" by software processing of the CPU.

Description

  The present invention relates to a microcomputer provided with a register for storing time information indicating the time when an edge in a specific direction occurs in an input signal.

  As a microcomputer (hereinafter also referred to as a microcomputer), when an edge in a specific direction (level change edge) occurs in an input signal to a specific terminal, a free running timer (also referred to as a free running counter) is counted as time information at that time. A device having an input capture register (hereinafter referred to as a capture register) that latches a value is known (for example, see Patent Document 1). In such a microcomputer, the CPU can detect the time when the edge in the specific direction occurs in the input signal by reading the value (time information) of the capture register.

  Furthermore, there is also known a microcomputer in which when an edge in a specific direction occurs in an input signal to a specific terminal, an interrupt request is generated and the CPU executes an interrupt process (for example, see Patent Document 2).

  In addition, regarding the capture register, if the edge that causes the capture register to latch the count value of the free running timer is referred to as a valid edge, a capture register whose rising edge is a rising edge (hereinafter, rising edge capture). A microcomputer including a register and a capture register whose effective edge is a falling edge (hereinafter referred to as a falling edge capture register) is also well known. In the microcomputer, when a rising edge occurs in the input signal to a specific terminal, the rising edge capture register latches the count value of the free running timer as time information indicating the time when the rising edge occurs. When a falling edge occurs in the input signal, the falling edge capture register latches the count value of the free running timer as time information indicating the time when the falling edge occurs.

Here, an example of use of a microcomputer provided with a rising edge capture register and a falling edge capture register will be described with reference to FIG.
FIG. 10 shows a usage example in the case of measuring the duty ratio of a PWM (pulse width modulation) signal in which the falling edge generation period (T in FIG. 10) is constant. In this example, the low level time (W in FIG. 10) from the falling edge of the PWM signal to the next rising edge is a variable pulse width.

  In the usage example shown in FIG. 10, every time a PWM signal is input to the microcomputer and a falling edge occurs in the PWM signal, an interrupt request is generated inside the microcomputer, and the CPU executes an interrupt process. That is, the valid edge for the interrupt request is a falling edge.

Then, the CPU of the microcomputer performs the following processes [S1] to [S4] in the interrupt process associated with the falling edge of the PWM signal.
[S1] The value of the falling edge capture register is read, and the read value (that is, the count value of the free-running timer when the falling edge occurs in the PWM signal this time) Na and the interrupt processing are executed last time. The period of the PWM signal is calculated from the difference from the value Nb read from the falling edge capture register and stored in the RAM (that is, the count value of the free running timer when the falling edge occurred in the PWM signal last time) Nb. (That is, one cycle time from the last occurrence of the falling edge to the current occurrence) is calculated.

  [S2] The value of the rising edge capture register is read, and the PWM signal is calculated from the difference between the read value (that is, the count value of the free running timer when the rising edge occurs in the PWM signal) Nc and the value Nb. Pulse width (that is, the pulse width time from the occurrence of the falling edge to the occurrence of the rising edge) is calculated.

[S3] The PWM signal duty ratio is calculated by dividing the pulse width calculated in [S2] by the period calculated in [S1].
[S4] After at least the processes of [S1] and [S2], the value Na of the falling edge capture register read in [S1] is updated and stored in the RAM as the new value Nb. Note that the value Nb stored in the RAM in the process [S4] is used in the processes [S1] and [S2] in the next interrupt process.

  For this reason, as shown in FIG. 10, if a falling edge occurs in the PWM signal at time t1, a rising edge occurs at time t2, and a falling edge occurs at time t3, at time t1, the falling edge The count value (C1) of the free running timer at time t1 is stored in the falling edge capture register, and at time t2, the count value (C2) of the free running timer at time t2 is stored in the rising edge capture register. At time t3, the count value (C3) of the free running timer at time t3 is stored in the falling edge capture register.

  In the interrupt process associated with the falling edge at time t3, the period from time t1 to time t3 (specifically, the count number of the free running timer from time t1 to time t3 (= C3-C1)) is set as a period T. In addition to calculation, the time from time t1 to time t2 (specifically, the count number of the free running timer from time t1 to time t2 (= C2-C1)) is calculated as the pulse width W, and the calculated period T The ratio of the pulse width W to is calculated as the duty ratio.

JP-A-8-258694 JP 57-49040 A

  In the conventional microcomputer, the value of the capture register is automatically updated every time a valid edge for the capture register occurs (that is, regardless of the processing performed by the CPU according to software).

  For this reason, the period from the start of a predetermined monitor to the time when the CPU performs the reading process for reading the value of the capture register is set as the valid edge monitor period, and the valid edge is first generated during the monitor period. The following problems occur when it is desired to acquire the time information in the above reading process.

  That is, if a valid edge occurs twice or more during the monitoring period, the capture register value is not the time information when the valid edge is first generated when the CPU performs the above reading process. As a result, the time information when the valid edge first occurs is lost (the time when the valid edge first occurs cannot be detected).

  For example, the above-described use example (shown in FIG. 10) of the microcomputer including the rising edge capture register and the falling edge capture register will be described. As illustrated in FIG. 11, the falling edge is added to the PWM signal at time t3. Until the CPU starts interrupt processing (more specifically, until the value of the rising edge capture register is read in the interrupt processing), at time t4 during the processing start delay period, the PWM signal is caused by noise. Assume that an unnecessary (extra) rising edge occurs.

  Then, the count value (C4) of the free running timer at the time t4 is updated and stored in the rising edge capture register, and the count value (C2) at the time t2 when the PWM signal first rises after the previous fall. ) Will be lost.

  For this reason, the CPU cannot acquire the count value (C2) at the time t2 (cannot detect the time t2), and thus correctly calculates the pulse width and duty ratio of the PWM signal. Can not do. In the example of FIG. 11, the free running timer count number (= C4−C1) from time t1 to time t4, which is longer than the period T, is calculated as the pulse width W.

  In the example of FIGS. 10 and 11, the value of the rising edge capture register is read in the interrupt processing is the end of the previous monitoring period for the rising edge, and the start of the next monitoring period (monitoring start). Time).

  The present invention has been made in view of such a problem. When a valid edge in a specific direction occurs in an input signal, the microcomputer having a time storage register for storing time information at that time, the CPU starts from a predetermined monitor start time. Even when a valid edge occurs a plurality of times during the monitoring period until the time of reading the value of the time storage register, the CPU can acquire time information when the valid edge first occurs, It is an object.

  When a valid edge that is an edge in a specific direction occurs in an input signal, the microcomputer according to claim 1 includes a time storage register that stores time information indicating a time at that time, and a CPU that executes a program. In addition, update control means is provided.

  Then, when the time storage register stores the time information, the update control means prohibits the time storage register from updating and storing the time information until receiving a permission signal output from the CPU.

  In this microcomputer, when a valid edge occurs in the input signal and the time storage register stores the time information, the valid edge occurs again in the input signal until the CPU gives a permission signal to the update control means by software processing. However, the stored value of the time storage register is not updated.

  Therefore, according to this microcomputer, even if the valid edge occurs a plurality of times in the monitoring period from the start of the predetermined monitoring to the time when the CPU reads the value of the time storage register, the valid edge occurs first. If the CPU wants to acquire the time information of the hour, the CPU should give a permission signal to the update control means at the start of monitoring.

  By doing so, the time storage register is in a state in which the time information can be updated and stored from the start of monitoring, and even after that, even if the valid edge occurs multiple times in the input signal, Information is updated and stored. Therefore, even if the valid edge occurs multiple times during the monitoring period, the CPU can acquire the time information when the valid edge first occurs by reading the value of the time storage register. The time when the valid edge first occurs can be detected.

  According to a second aspect of the present invention, in the microcomputer of the first aspect, the time storage register is provided as a first time storage register, and the input signal is one of a rising edge and a falling edge. This is a signal in which the reference edge is generated a plurality of times.

  The first time storage register stores time information indicating the current time when a non-reference edge in the direction opposite to the reference edge is generated as a valid edge in the input signal.

  The microcomputer according to claim 2 generates an interrupt request when a reference edge occurs in the input signal and a second time storage register for storing time information indicating the time at the time when the reference edge occurs in the input signal. Interrupt generating means.

  In this microcomputer, the CPU performs the following first to sixth processes in the interrupt process that starts execution when an interrupt request is generated by the interrupt generation means (that is, when a reference edge occurs in the input signal).

  That is, in the interrupt processing, the CPU performs “first processing for reading time information stored in the first time storage register” and “second processing for reading time information stored in the second time storage register”. ”And“ time information value read in the second process, and the previous occurrence of the reference edge, which is the time information read in the second process and stored in the memory when the interrupt process was executed last time From the difference from the value of the time information, the third process for calculating one cycle time, which is the time from the last occurrence of the reference edge to the input signal to the current occurrence, and the time read in the first process A pulse width time that is a time from when the reference edge is generated in the input signal to when the non-reference edge is generated is calculated from the difference between the information value and the value of the reference edge previous generation time information. Processing Cormorant. Then, after the third process and the fourth process, a “fifth process for updating and storing the time information read in the second process as new reference edge previous occurrence time information in the memory” is performed. After the first process, a “sixth process for giving a permission signal to the update control unit and allowing the first time storage register to update and store time information” is performed.

  According to such a microcomputer, due to the interrupt processing accompanying the generation of the reference edge, one cycle time of the input signal (the time from when the reference edge is generated to the current generation) and the pulse width time of the input signal (the reference edge) The time from when the edge occurs last time until the non-reference edge occurs) can be calculated. Further, the ratio of the pulse width time to one cycle time of the input signal can be calculated from the calculated cycle and the pulse width time. If a PWM signal having a constant reference edge generation cycle is an input signal, the ratio As a result, the duty ratio of the PWM signal can be calculated.

  In particular, in the interrupt processing, the permission signal is given to the update control means by the sixth processing after the first processing for reading the value (time information) of the first time storage register, so that the input signal has a reference edge. A non-reference edge (that is, a first time memory that is unnecessary for an input signal due to noise) between occurrence of the interrupt signal and start of interrupt processing (more specifically, until the first processing in the interrupt processing is performed). Even if a valid edge for the register occurs, the value of the first time storage register is not updated. For this reason, when the value of the first time storage register is read in the first processing in the interrupt processing, the first time storage register has a non-reference edge first in the input signal after the previous occurrence of the reference edge. Time information at the time of occurrence is stored.

  Therefore, even if an unnecessary non-reference edge due to the noise occurs, the interrupt process can acquire time information when the non-reference edge first occurs after the reference edge occurred in the input signal last time. It is possible to avoid calculating an incorrect pulse width time. In other words, the time from when the reference edge occurs in the input signal to the time when the first non-reference edge occurs can be calculated as the pulse width time, thus avoiding erroneous calculation of the pulse width time due to noise. it can.

  In this microcomputer, the time when the value of the first time storage register is read in the first process of the interrupt process is the end of the previous monitor period, and the start of the next monitor period (monitor start time) Strictly speaking, the monitoring start time is strictly when the permission signal is given to the update control means in the sixth process.

  According to a third aspect of the present invention, in the microcomputer according to the second aspect, the input signal is a PWM (pulse width modulation) signal having a constant reference edge generation period. Then, in the interrupt process, the CPU performs “seventh process for calculating the duty ratio of the PWM signal from one cycle time calculated in the third process and the pulse width time calculated in the fourth process”.

  According to this microcomputer, even if an unnecessary non-reference edge occurs in the PWM signal due to noise between the occurrence of the reference edge in the PWM signal as the input signal and the execution of the first process in the interrupt process. It is possible to avoid calculating an incorrect duty ratio.

  Next, in the microcomputer according to claim 4, in the microcomputer according to claim 3, in the interrupt process, the CPU determines “whether or not one cycle time calculated in the third process is within a predetermined normal range. When the eighth process is performed and it is determined by the eighth process that one cycle time is not within the normal range, the seventh process is skipped.

  That is, in the interrupt process, if the one cycle time calculated this time is not within the normal range, the duty ratio is not calculated using the one cycle time calculated this time and the pulse width time. Note that the normal range may be set to a normal permissible range (permissible range considered normal) of the PWM signal cycle (reference edge generation cycle).

  According to this microcomputer, between the occurrence of a regular reference edge in the PWM signal and the occurrence of the next regular reference edge, an unnecessary reference edge is generated due to noise, and the reference edge generation interval is normal. When it becomes shorter than the range, the one cycle time calculated in the third process in the interrupt process becomes shorter than the normal range, and this is determined in the eighth process, and the seventh process is skipped. Will be.

  For this reason, when an unnecessary reference edge is generated in the PWM signal due to noise (when the generation interval of the reference edge is shorter than the normal range), it is possible to avoid calculating an incorrect duty ratio. .

  Next, in the microcomputer of claim 5, in the microcomputer of claim 4, if the CPU determines that one cycle time is not within the normal range by the eighth process in the interrupt process, Processing is also skipped. That is, in the interrupt process, if the one cycle time calculated this time is not within the normal range, the update storage of the reference edge previous occurrence time information is stopped as well as the duty ratio calculation.

  According to this microcomputer, even if an unnecessary reference edge is generated due to noise between the occurrence of a normal reference edge in the PWM signal and the generation of the next normal reference edge, the next normal signal is generated in the PWM signal. When the reference edge is generated and interrupt processing is executed, the correct one cycle time (PWM signal cycle) is calculated by the interrupt processing at that time. The reference edge previous occurrence time information used in the third and fourth processes in the interrupt process at that time is not the time information when the reference edge due to noise occurs, but the time when the last regular reference edge occurs Because it is information.

  In addition, if an unnecessary reference edge is generated due to noise between the occurrence of a regular reference edge in the PWM signal and the occurrence of the next regular reference edge, it is unnecessary in the immediate vicinity of the unnecessary reference edge. In this case, if the next regular reference edge occurs in the PWM signal and interrupt processing is executed, the correct pulse width time is calculated by the interrupt processing of that time. As a result, the correct duty ratio is calculated.

  To explain this, first, as a pattern in which an unnecessary reference edge and a non-reference edge are generated due to noise between the generation of a normal reference edge in the PWM signal and the generation of the next normal reference edge. There are the following first pattern and second pattern.

  The first pattern is: “Non-reference edge and reference edge in that order due to noise during the pulse width period, which is the period from the generation of the normal reference edge to the PWM signal until the generation of the normal non-reference edge. It occurs.

  The second pattern is “a reference edge and a non-reference edge due to noise during an anti-pulse width period, which is a period from when a normal non-reference edge occurs in the PWM signal until the next normal reference edge occurs. Are generated in that order. "

  In the case of the first pattern, the time information when the non-reference edge due to noise occurs is stored in the first time memory, but in the interrupt processing accompanying the reference edge due to noise immediately after that, the first information is stored. The value of the time storage register is ignored. This is because it is determined by the eighth process that one cycle time is not within the normal range, and the seventh process is skipped.

  Also, in the interrupt processing accompanying the reference edge due to noise, the permission signal is given to the update control means by the sixth processing. Therefore, if a normal non-reference edge occurs thereafter, the time information at that time is updated and stored in the first time storage register.

  Then, if a normal reference edge occurs after that and interrupt processing is executed, the correct one cycle time and pulse width time of the PWM signal are calculated by the interrupt processing of that time. Thus, the correct duty ratio is calculated.

  On the other hand, in the case of the second pattern, when the reference edge due to noise occurs, the time information of the time when the normal non-reference edge occurs is already stored in the first time storage register. The register is in an update storage prohibition state. For this reason, even if a non-reference edge due to the noise occurs from when the reference edge due to noise occurs until interrupt processing associated with the reference edge starts (more specifically, until the sixth process is performed), The value of the first time storage register is not updated. Also in the case of the second pattern, in the interrupt processing accompanying the reference edge due to noise, it is determined by the eighth processing that one cycle time is not within the normal range, and the seventh processing is skipped.

  Therefore, if a normal reference edge occurs after that and interrupt processing is executed, the correct one cycle time and pulse width time of the PWM signal are calculated by the interrupt processing of that time, Thus, the correct duty ratio is calculated.

  From the above, according to the microcomputer of the fifth aspect, it is possible to further improve the avoidance performance of erroneous calculation of the duty ratio due to noise.

It is a block diagram showing the structure of the microcomputer of embodiment. It is a flowchart explaining operation | movement of a timer unit. It is a flowchart showing an initialization process. It is a flowchart showing an interruption process. It is a time chart showing operation when noise does not ride on a PWM signal. It is the 1st time chart showing operation when noise gets on a PWM signal. It is the 2nd time chart showing operation when noise gets on a PWM signal. It is a 3rd time chart showing operation | movement when a noise gets on a PWM signal. It is a 4th time chart showing operation when noise gets on a PWM signal. It is explanatory drawing explaining the usage example of the conventional microcomputer. It is explanatory drawing explaining the problem of a prior art.

The microcomputer of the embodiment to which the present invention is applied will be described below.
As shown in FIG. 1, the microcomputer 1 of the present embodiment includes a CPU 3 that executes a program, a ROM 5 that stores a program to be executed, a RAM 7 that stores a part of the program, a calculation result by the CPU 3, and the like. A timer unit 9 having a function of storing time information when an edge occurs in an input signal to the microcomputer 1, a bus 11 for connecting them, and an interrupt controller (INTC) 13 for outputting an interrupt request signal to the CPU 3 And an edge detection port 15.

  The edge detection port 15 outputs a rising edge detection signal when a rising edge (level change edge from low to high) occurs in the input signal input to the specific terminal 17 of the microcomputer 1, and the rising edge is detected by the input signal. When a falling edge (level change edge from high to low) occurs, a falling edge detection signal is output. Each of the rising edge detection signal and the falling edge detection signal is, for example, a pulse signal having a pulse width corresponding to a predetermined period (for example, half period or one period) of the internal clock in the microcomputer 1.

  The timer unit 9 includes a free running timer 19 that is counted up by an internal clock in the microcomputer 1, a rising edge capture register 21, a rising edge capture mode register 23, a rising edge capture enable register 25, and a rising edge capture. Control circuit 27, falling edge capture register 31, falling edge capture mode register 33, falling edge capture enable register 35, falling edge capture control circuit 37, interrupt request signal generator 41, interrupt request And an effective edge setting register 43.

  The rising edge detection signal output from the edge detection port 15 is input to the rising edge capture control circuit 27 and the interrupt request signal generation unit 41, and the falling edge detection signal output from the edge detection port 15 is The falling edge capture control circuit 37 and the interrupt request signal generator 41 are inputted.

  The rising edge capture register 21 is a register having the same number of bits as the free running timer 19. When the rising edge detection signal is input via the rising edge capture control circuit 27, the count value of the free running timer 19 at that time ( The timer value is latched (stored). The rising edge capture register 21 can be read from the CPU 3.

  The rising edge capture mode register 23 is a 1-bit register for setting the operation mode of the rising edge capture control circuit 27, and “1” or “0” is written by the CPU 3.

  The rising edge capture enable register 25 is a 1-bit register that is set to “1” every time the rising edge capture register 21 latches a timer value (that is, every time it is updated and stored). The value of the rising edge capture enable register 25 can be rewritten to “0” by the CPU 3.

  When the value of the rising edge capture mode register 23 is “0”, the rising edge capture control circuit 27 is in the normal mode, and when the value of the rising edge capture mode register 23 is “1”. The operation mode becomes the one-shot mode. Contrary to this correspondence, the value of the rising edge capture mode register 23 may be such that “0” corresponds to the one-shot mode and “1” corresponds to the normal mode. This also applies to the value of the falling edge capture mode register 33 described later.

  In the normal mode, the rising edge capture control circuit 27 outputs the rising edge detection signal from the edge detection port 15 to the rising edge capture register 21 as it is.

  Therefore, when the operation mode of the rising edge capture control circuit 27 is set to the normal mode, the processing mode in the timer unit 9 for the rising edge is the normal mode. In the normal mode, the input signal to the terminal 17 is Each time a rising edge occurs, the rising edge capture register 21 updates and stores the timer value.

  In the one-shot mode, the rising edge capture control circuit 27 sends the rising edge detection signal from the edge detection port 15 to the rising edge capture register 21 if the value of the rising edge capture enable register 25 is “0”. However, if the value of the rising edge capture enable register 25 is “1”, the rising edge detection signal is not output to the rising edge capture register 21. Therefore, the rising edge capture register 21 updates and stores the timer value only when the value of the rising edge capture enable register 25 is “0”.

  Therefore, when the operation mode of the rising edge capture control circuit 27 is set to the one-shot mode, the processing mode in the timer unit 9 for the rising edge is set to the one-shot mode. When the rising edge first occurs in the input signal to the terminal 17 after the value of the capture enable register 25 is set to “0”, the rising edge capture register 21 updates and stores the timer value. Until the value of the rising edge capture enable register 25 is rewritten from “1” to “0” by the CPU 3, even if a rising edge occurs in the input signal, the rising edge capture register 21 updates and stores the timer value. But, so that is prohibited.

  In addition, the falling edge capture register 31, the falling edge capture mode register 33, the falling edge capture enable register 35, and the falling edge capture control circuit 37 are respectively the rising edge capture register 21, the rising edge capture mode register 23, This is the same as each of the rising edge capture enable register 25 and the rising edge capture control circuit 27.

  That is, the falling edge capture register 31 is also a register having the same number of bits as the free-running timer 19, and when the falling edge detection signal is input via the falling edge capture control circuit 37, the timer value at that time is set. Latch (store). The falling edge capture register 31 can also be read-accessed from the CPU 3.

  The falling edge capture mode register 33 is a 1-bit register for setting the operation mode of the falling edge capture control circuit 37, and “1” or “0” is written by the CPU 3.

  The falling edge capture enable register 35 is a 1-bit register that is set to “1” every time the falling edge capture register 31 latches the timer value (that is, every time it is updated and stored). The value of the falling edge capture enable register 35 can be rewritten to “0” by the CPU 3.

  When the value of the falling edge capture mode register 33 is “0”, the falling edge capture control circuit 37 is in the normal mode and the value of the falling edge capture mode register 33 is “1”. In this case, the operation mode is the one-shot mode.

  In the normal mode, the falling edge capture control circuit 37 outputs the falling edge detection signal from the edge detection port 15 to the falling edge capture register 31 as it is.

  Therefore, when the operation mode of the falling edge capture control circuit 37 is set to the normal mode, the processing mode in the timer unit 9 for the falling edge is the normal mode. In the normal mode, the input to the terminal 17 is performed. Each time a falling edge occurs in the signal, the falling edge capture register 31 updates and stores the timer value.

  In the one-shot mode, the falling edge capture control circuit 37 outputs a falling edge detection signal from the edge detection port 15 as a falling edge if the value of the falling edge capture enable register 35 is “0”. Although it is output to the capture register 31, if the value of the falling edge capture enable register 35 is “1”, the falling edge detection signal is not output to the falling edge capture register 31.

  Therefore, when the operation mode of the falling edge capture control circuit 37 is set to the one-shot mode, the processing mode in the timer unit 9 for the falling edge is the one-shot mode. When the falling edge is first generated in the input signal to the terminal 17 after the value of the falling edge capture enable register 35 is set to “0”, the falling edge capture register 31 updates and stores the timer value. Even if a falling edge occurs in the input signal from the update storage time until the value of the falling edge capture enable register 35 is rewritten from “1” to “0” by the CPU 3, the falling edge capture register 31. Stores the timer value updated. But, so that is prohibited.

On the other hand, in the timer unit 9, the interrupt request valid edge setting register 43 is a 1-bit register that can be write-accessed by the CPU 3.
Then, the interrupt request signal generation unit 41 receives the signal indicated by the value of the interrupt request valid edge setting register 43 among the rising edge detection signal and the falling edge detection signal from the edge detection port 15. Then, an interrupt request signal is output to the interrupt controller 13.

  In this embodiment, for example, when the value of the interrupt request valid edge setting register 43 is “1”, the interrupt request signal generation unit 41 outputs an interrupt request signal when a rising edge detection signal is input, and reversely In addition, when the value of the interrupt request valid edge setting register 43 is “0”, an interrupt request signal is output when a falling edge detection signal is input.

  The interrupt request signal output from the interrupt request signal generation unit 41 is output from the interrupt controller 13 to the CPU 3 as an interrupt request signal corresponding to an external interrupt (that is, an external interrupt request signal). Then, the CPU 3 executes an interrupt process (that is, an external interrupt process) corresponding to the external interrupt request signal.

  That is, the interrupt request valid edge setting register 43 is a register for arbitrarily setting the valid edge of the interrupt request (specifically, the edge of the input signal that generates the interrupt request). If it is set to “1”, the rising edge becomes the effective edge of the interrupt request, and if the value of the register 43 is set to “0”, the falling edge becomes the effective edge of the interrupt request.

  A mode in which the interrupt request valid edge setting register 43 is a multi-bit register and the interrupt request signal generation unit 41 outputs an interrupt request signal regardless of which of the rising edge detection signal and the falling edge detection signal is input. A mode that outputs an interrupt request signal only when a rising edge detection signal is input, a mode that outputs an interrupt request signal only when a falling edge detection signal is input, and a rising edge detection signal and a falling edge detection It may be configured to switch to four modes, a mode in which no interrupt request signal is output regardless of which signal is input.

  From the above, the operation contents of the timer unit 9 are summarized as shown in the flowchart of FIG. Here, a case where a rising edge occurs in the input signal to the terminal 17 will be described as an example, but the same operation is performed when a falling edge occurs in the input signal.

  As shown in FIG. 2, for example, when the rising edge occurs in the input signal, if the value of the rising edge capture mode register 23 is “0” (S101: NO), the value is related to the value of the rising edge capture enable register 25. First, the rising edge capture register 21 updates and stores the timer value (S102), and "1" is set in the rising edge capture enable register 25 as the update storage is performed (S103).

  If the value of the rising edge capture mode register 23 is “1” when the rising edge occurs in the input signal (S101: YES), only when the value of the rising edge capture enable register 25 is “0” (S101: YES) (S104: YES), the rising edge capture register 21 updates and stores the timer value (S102), and "1" is set in the rising edge capture enable register 25 as the update storage is performed (S103).

  Therefore, when the rising edge occurs in the input signal, the value of the rising edge capture mode register 23 is “1” (S101: YES), and the value of the rising edge capture enable register 25 is “1”. (S104: NO), the rising edge capture register 21 does not update and store the timer value.

  On the other hand, when the rising edge is generated in the input signal, if the rising edge is set to the valid edge of the interrupt request by the interrupt request valid edge setting register 43 (S150: YES), the interrupt request signal generation unit 41 interrupts. An interrupt request signal is output to the controller 13 (S106). On the contrary, if the rising edge is not set to the valid edge of the interrupt request (S105: NO), the interrupt request signal generation unit 41 does not output the interrupt request signal.

  Note that the operation of the timer unit 9 when a falling edge occurs in the input signal to the terminal 17 in the description related to FIG. 2 above is to read “rising edge” as “falling edge” and “register 21” as “ The operation is performed by replacing “register 31”, “register 23” with “register 33”, and “register 25” with “register 35”.

Next, a usage example of the microcomputer 1 as described above will be described.
In the present embodiment, a PWM signal having a constant falling edge generation cycle is input to the terminal 17 of the microcomputer 1. In the microcomputer 1, the CPU 3 calculates the duty ratio of the PWM signal by executing the processing of FIGS. 3 and 4.

  In the following description, “periodic edge” refers to an edge (a falling edge in this example) that occurs every one period of the PWM signal among the edges of the PWM signal. “Periodic edge” means an edge in the opposite direction to the periodic edge (in this example, a rising edge). In this embodiment, the occurrence interval of the periodic edge (falling edge) in the PWM signal is detected as one period time (hereinafter simply referred to as “period”) of the PWM signal, and the periodic edge (falling edge) is detected. The time from occurrence to the occurrence of a non-periodic edge (rising edge) is detected as the pulse width time (hereinafter simply referred to as “pulse width”), and the ratio of the pulse width to the detected period is determined as the PWM signal. Calculated as the duty ratio.

First, FIG. 3 is a flowchart showing an initialization process executed by the CPU 3 immediately after the microcomputer 1 is activated.
As shown in FIG. 3, when the CPU 3 starts to execute the initialization process, first, in S110, “0” is written in the interrupt request valid edge setting register 43, so that the falling edge, which is a periodic edge, is interrupted. Set to valid edge of request.

  Then, in the next S120, “1” is written to the rising edge capture mode register 23 to set the operation mode of the rising edge capture control circuit 27 to the one-shot mode. In the next S 130, “0” is written to the falling edge capture mode register 33 to set the operation mode of the falling edge capture control circuit 37 to the normal mode. That is, in the present embodiment, the processing form in the timer unit 9 is set to the one-shot mode for the rising edge of the PWM signal, and the processing form in the timer unit 9 is set to the normal mode for the falling edge of the PWM signal. It is set.

  Next, “0” as an initial value is written in the rising edge capture enable register 25 in S140, and “0” as an initial value is also written in the falling edge capture enable register 35 in S150.

Then, the initialization process ends.
Next, FIG. 4 is a flowchart showing an interrupt process executed when the CPU 3 receives an external interrupt request signal from the interrupt controller 13 (that is, an interrupt request signal from the interrupt request signal generation unit 41). Therefore, the interrupt process in FIG. 4 is executed every time a falling edge occurs in the PWM signal to the terminal 17.

  As shown in FIG. 4, when the CPU 3 starts executing the interrupt process, first, in S210, the value of the falling edge capture register 31 is read, and the read value is stored in the RAM 7 as the periodic edge current occurrence time. . Note that the current occurrence time of the periodic edge is the “time when the periodic edge occurs this time”.

  Next, in S215, it is determined whether or not the current interrupt process is the first process (specifically, the process executed first after the microcomputer 1 is activated). If the current interrupt process is not the first process (that is, if it is the second or subsequent process), the process proceeds to S220.

  In S220, the value of the rising edge capture register 21 is read, and the read value is stored in the RAM 7 as the aperiodic edge occurrence time. The non-periodic edge derivation time is “the time when the non-periodic edge occurs”.

  In the next S230, the period of the PWM signal (specifically, the period of the PWM signal is determined by subtracting the period edge previous generation time stored in the RAM 7 from the current generation time of the periodic edge stored in the RAM 7 in S210). The time from the last occurrence of the edge to the current occurrence) is calculated. Note that the previous occurrence time of the periodic edge is the “time when the periodic edge occurred last time”, and when the interrupt processing was executed last time, it was read from the falling edge capture register 31 in S210, and in S270 described later. This is the value stored in the RAM 7.

  In subsequent S240, by subtracting the previous periodic edge generation time from the non-periodic edge generation time stored in the RAM 7 in S220, the pulse width of the PWM signal (specifically, the periodic edge is generated in the PWM signal last time). To the time from when the non-periodic edge occurs).

  In the present embodiment, since the time information indicating the occurrence time of the edge is a timer value, the period value calculated in S230 is actually the period time equal to one count of the free running timer 19. Similarly, the value of the pulse width calculated in S240 is actually a value obtained by dividing the time of the pulse width by the time of one count. .

Next, in S250, it is determined whether or not the cycle calculated in S230 is within the normal range. This normal range is set to an allowable range that is considered normal as a cycle value.
If it is determined in S250 that the cycle is within the normal range, the process proceeds to S260, and the duty ratio of the PWM signal is calculated from the cycle calculated in S230 and the pulse width calculated in S240. Specifically, the ratio of the pulse width to the cycle (= pulse width / cycle) is calculated as the duty ratio.

In next S270, the periodic edge current occurrence time is updated and stored in the RAM 7 as a new periodic edge previous occurrence time.
Further, in the next S280, “0” is written to the rising edge capture enable register 35 to allow the rising edge capture register 21 to update and store the timer value, and then the interrupt processing is ended.

  If it is determined in S250 that the cycle is not within the normal range, S260 and S270 are skipped, the process proceeds to S280, “0” is written in the rising edge capture enable register 35, and the interrupt is performed. The process ends.

  On the other hand, if it is determined in S215 that the current interrupt process is the first process, the process proceeds to S270. In other words, since the cycle and duty ratio cannot be calculated in the first interrupt processing, the value stored in the falling edge capture register 31 is stored in the RAM 7 as the previous cycle edge occurrence time in preparation for the next interrupt processing ( Only S210 and S270) and a process of writing “0” in the rising edge capture enable register 35 (S280) are performed.

Next, the operation and effect of the microcomputer 1 will be described with reference to FIGS.
First, FIG. 5 is a time chart showing the operation when noise is not applied to the PWM signal.
As shown in FIG. 5, in the microcomputer 1, the CPU 3 executes the interrupt process of FIG. 4 every time a falling edge occurs in the PWM signal.

  As described above, the processing mode in the timer unit 9 is set to the normal mode for the falling edge of the PWM signal (S130 in FIG. 3). As for the rising edge of the PWM signal, the processing mode in the timer unit 9 is set to the one-shot mode (S120 in FIG. 3), but the CPU 3 stores “0” in the rising edge capture enable register 35 in the interrupt processing. "Is written (S280 in FIG. 4).

  Therefore, as shown in FIG. 5, if a falling edge occurs in the PWM signal at time t1, a rising edge occurs at time t2, and a falling edge occurs at time t3, at time t1, the falling edge The timer value (C1) at time t1 is stored in the falling edge capture register 31, and at time t2, the timer value (C2) at time t2 is stored in the rising edge capture register 21, and at time t3, the time The timer value (C3) at t3 is stored in the falling edge capture register 31.

  In the interrupt process associated with the falling edge at time t3, the period from time t1 to time t3 (specifically, the count number of the free running timer from time t1 to time t3 (= C3-C1)) is set as a period T. Along with the calculation (S230), the time from time t1 to time t2 (specifically, the count number of the free running timer from time t1 to time t2 (= C2-C1)) is calculated as the pulse width W (S240), Further, the ratio of the pulse width W to the calculated period T (= W / T) is calculated as the duty ratio (S260).

  Next, FIG. 6 is a first time chart showing the operation when noise is added to the PWM signal. Specifically, the CPU 3 starts interrupt processing after a normal falling edge occurs in the PWM signal. 6 is a time chart showing an operation when an unnecessary rising edge due to noise occurs in the PWM signal during the processing start delay period until. The regular falling edge is a normal falling edge whose generation interval is normal as the period of the PWM signal. In other words, the normal falling edge is within the normal range used for the determination in S250 of FIG. It is a falling edge.

  As shown in FIG. 6, the process from when the regular falling edge occurs in the PWM signal at the same time t3 as in FIG. 5 until the CPU 3 starts the interrupt process (interrupt process associated with the falling edge at time t3). It is assumed that an unnecessary rising edge due to noise occurs in the PWM signal at time t4 during the start delay period.

  In this case, the first rising edge after the normal falling edge occurs in the PWM signal at time t2 before time t3, and at the time t2, the rising edge capture register 21 sets the timer value (C2). Is stored, the value of the rising edge capture enable register 35 is “1”. When the value of the rising edge capture enable register 35 is “1”, S280 in the interrupt processing (first interrupt processing after time t3 in FIG. 6) associated with the falling edge at time t3 is executed. Continue until

  For this reason, even if a rising edge occurs in the PWM signal at time t4, the value of the rising edge capture register 21 is not updated, and the first rising edge occurs after the last normal falling edge occurs in the PWM signal. The timer value (C2) at the time t2 remains unchanged.

  Therefore, in the interrupt process associated with the falling edge at time t3, in S220, the timer value (C2) at time t2 can be acquired from the rising edge capture register 21 instead of the timer value at time t4. As a result, it is possible to avoid calculating an incorrect pulse width in S240. That is, in the interrupt processing associated with the falling edge at time t3, as in the case of FIG. 5, the time from the time when the falling edge was last generated until the time when the rising edge was first generated (from time t1 to time t2). The count number (= C2-C1) of the free running timer can be calculated as the pulse width W, and an erroneous calculation of the pulse width due to noise can be avoided. For this reason, the duty ratio can also be calculated correctly.

  In the example of FIG. 6, a falling edge due to noise occurs in the PWM signal at time t5 after time t4. At the time t5, in the interrupt processing accompanying the falling edge at time t3, This is after the process of reading the value of the falling edge capture register 31 (S210). For this reason, in the interrupt processing accompanying the falling edge at time t3, the timer value (C3) at time t3 is read from the falling edge capture register 31 in S210. In FIG. 6, the time from time t1 to time t3 is described as “T1”. In the example of FIG. 6, in S230 of the interrupt process associated with the falling edge at time t3, the count number (= C3-C1) of the free running timer corresponding to the time T1 is calculated as the cycle. In S260 of the interrupt process, the value of “pulse width W / time T1” is calculated as the duty ratio.

  Next, FIG. 7 is a second time chart showing the operation when noise is added to the PWM signal. Specifically, the CPU 3 starts interrupt processing after a normal falling edge occurs in the PWM signal. During the processing start delay period until the time point, both unnecessary rising edge and falling edge due to noise occur in the PWM signal, and further, the interval from the last regular falling edge to the unnecessary falling edge (FIG. 7). T1) in FIG. 6 is also a time chart showing the operation when the PWM signal cycle is within an allowable range considered normal.

  As shown in FIG. 7, the process from when a regular falling edge occurs in the PWM signal at the same time t3 as in FIG. 5 until the CPU 3 starts an interrupt process (interrupt process associated with the falling edge at time t3). At time t4 during the start delay period, an unnecessary rising edge due to noise occurs in the PWM signal, and at time t5 during the processing start delay period, an unnecessary falling edge due to noise occurs at the PWM signal, Furthermore, it is assumed that the time T1 from the time t1 to the time t5 at which the regular falling edge was previously generated is also within an allowable range that is considered normal as the period of the PWM signal.

  Also in this case, as in the case of FIG. 6, the first rising edge after the normal falling edge occurs in the PWM signal at time t2 before time t3, and at the time t2, the rising edge Since the capture register 21 stores the timer value (C2), the value of the rising edge capture enable register 35 is “1”. When the value of the rising edge capture enable register 35 is “1”, S280 in the interrupt processing (first interrupt processing after time t3 in FIG. 7) associated with the falling edge at time t3 is executed. Continue until For this reason, even if a rising edge occurs in the PWM signal at time t4, the value of the rising edge capture register 21 is not updated, and the first rising edge occurs after the last normal falling edge occurs in the PWM signal. The timer value (C2) at the time t2 remains unchanged.

  Therefore, in the interrupt process associated with the falling edge at time t3, in S220, the timer value (C2) at time t2 can be acquired from the rising edge capture register 21 instead of the timer value at time t4. As a result, in S240, the count number (= C2-C1) of the free running timer from time t1 to time t2 can be calculated as the pulse width W. For this reason, erroneous calculation of the pulse width due to noise can be avoided.

  As for the falling edge, since the processing mode in the timer unit 9 is set to the normal mode, when the falling edge occurs at time t5, the value of the rising edge capture register 21 becomes the timer value at time t3. The timer value (C5) at time t5 is updated from (C3). Therefore, in the interrupt processing associated with the falling edge at time t3, the timer value (C5) at time t5 is acquired from the falling edge capture register 31 at S210, and from time t1 to time t5 at S230. The count number (= C5-C1) of the free running timer corresponding to the time T1 is calculated as a cycle. In this example, the time from the time t3 to the time t5 is very small, and the time T1 from the time t1 to the time t5 is also within the allowable range of the period of the PWM signal. In the interrupt processing, in S250, it is determined that the cycle calculated in S230 is within the normal range. In S260, the value of “pulse width W / time T1”, which is a duty ratio that can be regarded as correct, is determined. Will be calculated.

  In the above description regarding FIG. 7, it has been described that the falling edge at time t3 is a regular falling edge, and the falling edge at time t5 is an unnecessary falling edge due to noise. Even if the falling edge at t5 is a regular falling edge and the falling edge at time t3 is an unnecessary falling edge due to noise, the calculation result by the interrupt processing associated with the falling edge at time t3 is practical. Will be the same. That is, in the example of FIG. 7, if both the time from time t1 to time t3 and the time from time t1 to time t5 are within the allowable range as the period of the PWM signal, either time t3 or time t5 Even if the falling edge is a regular falling edge, the processing result is not substantially changed.

  Next, FIG. 8 is a third time chart showing the operation when noise is added to the PWM signal. Specifically, after the normal falling edge occurs in the PWM signal, the normal rising edge occurs. 6 is a time chart showing an operation when a rising edge and a falling edge occur in that order due to noise during a pulse width period up to (low level period in this embodiment).

  As shown in FIG. 8, in the same pulse width period (low level period) from time t1 to time t2 as in FIG. 5, the CPU 3 performs interrupt processing accompanying the falling edge of time t1 (in FIG. 8, after time t1). It is assumed that an unnecessary rising edge due to noise occurs in the PWM signal at time ta after the first interrupt processing), and an unnecessary falling edge due to noise occurs in the PWM signal immediately after time tb. .

  In this case, since the value of the rising edge capture enable register 25 is returned to “0” before the time ta, when a rising edge due to noise occurs at the time ta, the timer value (Ca) at the time ta is set. And stored in the rising edge capture register 21. When a falling edge due to noise occurs at time tb, the timer value (Cb) at that time tb is stored in the falling edge capture register 31.

  However, in the interrupt process associated with the falling edge at time tb, the values read from both capture registers 21 and 31 are invalidated, and it is possible to prevent an erroneous duty ratio from being calculated. In the interrupt processing of that time, in S250, it is determined that the cycle calculated in S230 (that is, a value corresponding to time T1 from time t1 to time tb in FIG. 8) is not within the normal range. This is because S270 is skipped.

  Also, in the interrupt processing associated with the falling edge at time tb, the value of the rising edge capture enable register 25 is set to “0” in S280, so that a normal rising edge is generated in the PWM signal at time t2. Then, the timer value (C2) at the time t2 is updated and stored in the rising edge capture register 21.

  Then, when a regular falling edge occurs in the PWM signal at a subsequent time t3, the timer value (C3) at that time t3 is updated and stored in the falling edge capture register 31.

  Furthermore, at the time when the interrupt processing associated with the falling edge at time t3 is started, the previous generation time of the periodic edge in the RAM 7 is not the timer value (Cb) at the time tb at which the falling edge due to noise occurred, but the previous time. The timer value (C1) at the time t1 when the regular falling edge is generated. This is because, in the interrupt processing accompanying the falling edge at time tb, not only S260 for calculating the duty ratio but also S270 for updating the previous occurrence time of the periodic edge is skipped.

  Therefore, if the interrupt process associated with the falling edge at time t3 is executed, the interrupt process at that time causes the correct period (that is, time T1 from time t1 to time tb and time tb to time t3 in FIG. 8). And a correct pulse width (that is, a value corresponding to time W from time t1 to time t2 in FIG. 8) is calculated and extended. Therefore, the correct duty ratio (“W / (T1 + T2” in FIG. 8) is calculated.

  Next, FIG. 9 is a fourth time chart showing the operation when noise is added to the PWM signal. Specifically, after the normal rising edge occurs in the PWM signal, the next normal falling edge is detected. 6 is a time chart showing an operation when a falling edge and a rising edge are generated in that order due to noise during an anti-pulse width period (high level period in the present embodiment) until they occur.

  As shown in FIG. 9, in the same anti-pulse width period (high level period) from time t2 to time t3 as in FIG. 5, an unnecessary falling edge due to noise occurs in the PWM signal at time tc. It is assumed that an unnecessary rising edge due to noise occurs in the PWM signal at time td before the interrupt processing associated with the falling edge is started.

  In this case, at the time tc, the rising edge capture register 21 already stores the timer value (C2) at the time t2 when the normal rising edge occurs, and the value of the rising edge capture enable register 25 is “1”. "It has become.

  For this reason, even if a rising edge due to noise occurs at time td before the interrupt processing associated with the falling edge at time tc is started, the value of the rising edge capture register 21 is not updated and the timer value (C2) It remains.

  When a falling edge due to noise occurs at time tc, the timer value (Cc) at that time tc is updated and stored in the falling edge capture register 31, but interrupt processing associated with the falling edge at time tc is performed. In S250, it is determined that the cycle calculated in S230 (that is, a value corresponding to time T1 from time t1 to time tc in FIG. 9) is not within the normal range, and S260 and S270 are skipped. . Therefore, it is possible to prevent the values read from both capture registers 21 and 31 from being invalid and calculating an incorrect duty ratio.

  Then, when a regular falling edge occurs in the PWM signal at a subsequent time t3, the timer value (C3) at that time t3 is updated and stored in the falling edge capture register 31. At that time, the value of the rising edge capture register 21 remains the timer value (C2) at time t2.

  Furthermore, at the time when the interrupt processing associated with the falling edge at time t3 is started, the previous generation time of the periodic edge in the RAM 7 is not the timer value (Cc) at the time tc when the falling edge due to noise occurs, but the previous time. The timer value (C1) at the time t1 when the regular falling edge is generated. This is because S270 is skipped in the interrupt processing accompanying the falling edge at time tc as described above.

  Therefore, if the interrupt process associated with the falling edge at time t3 is executed, the interrupt process at that time causes the correct period (ie, time T1 from time t1 to time tc and time tc to time t3 in FIG. 9). And a correct pulse width (that is, a value corresponding to time W from time t1 to time t2 in FIG. 9) is calculated. In this case, the correct duty ratio (“W / (T1 + T2” in FIG. 9) is calculated.

  On the other hand, in the example of FIG. 6 described above, in the interrupt process associated with the falling edge at time t5 (interrupt process shown on the rightmost side in FIG. 6), in S210, from the falling edge capture register 31 at time t5. The timer value (C5) is read, and in S230, the count number (= C5-C3) of the free running timer corresponding to the time T2 from the time t3 to the time t5 is calculated as a cycle. Then, it is determined that the period (value corresponding to time T2) calculated in S230 is not within the normal range, and S260 and S270 are skipped.

  That is, in the example of FIG. 6, the interrupt process associated with the falling edge at time t5 has the same processing result as the interrupt process associated with the falling edge at time tb in FIG. Therefore, if a normal falling edge occurs after a normal rising edge occurs in the PWM signal, the correct period, pulse width, and duty ratio are calculated by an interrupt process associated with the normal falling edge. It will be.

  Similarly, also in the example of FIG. 7 described above, in the interrupt process (interrupt process shown on the rightmost side in FIG. 7) associated with the falling edge at time t5, the falling edge capture register 31 starts from S210. The timer value (C5) at time t5 is read. In the interrupt processing of that time, when calculating the cycle in S230, the value of the previous occurrence time of the cycle edge is set to the time by S270 of the previous interrupt processing (that is, the interrupt processing associated with the falling edge at time t3). Since the timer value (C5) at t5 is set, 0 (= C5-C5) is calculated as a cycle. In S250, the cycle (= 0) calculated in S230 is not within the normal range. It will be judged. Therefore, S260 and S270 are skipped.

  For this reason, in the example of FIG. 7, the interrupt process associated with the falling edge at time t5 has the same processing result as the interrupt process associated with the falling edge at time tb in FIG. Therefore, if a normal falling edge occurs after a normal rising edge occurs in the PWM signal, the correct period, pulse width, and duty ratio are calculated by an interrupt process associated with the normal falling edge. It will be.

  According to the microcomputer 1 as described above, if “1” is written in the rising edge capture mode register 23, the processing mode in the timer unit 9 can be set to the one-shot mode for the rising edge of the input signal. If “1” is written in the falling edge capture mode register 33, the processing mode in the timer unit 9 can be set to the one-shot mode for the falling edge of the input signal.

  For example, if the one-shot mode is set for the rising edge, the input signal has a plurality of rising edges in the monitoring period from the start of arbitrary monitoring to the time when the CPU 3 performs the process of reading the value of the rising edge capture register 21. Even if it occurs, the CPU 3 can acquire the timer value as time information when the rising edge first occurs.

  Furthermore, the CPU 3 can calculate the period, pulse width, and duty ratio of the PWM signal by performing the initialization process of FIG. 3 and the interrupt process of FIG. It is possible to avoid giving the calculated result.

  In the use example of the microcomputer 1 described above (use example for calculating the duty ratio of the PWM signal), when the value of the rising edge capture register 21 is read in S220 in the interrupt processing of FIG. At the end of the previous monitoring period, which corresponds to the start of the next monitoring period (monitoring start time), strictly speaking, the monitoring start time is set to “0” in the rising edge capture enable register 25 in S280. Will be written.

  On the other hand, in the microcomputer 1 of the above embodiment, the rising edge capture register 21 and the falling edge capture register 31 correspond to an example of a time storage register.

  For the rising edge capture register 21 having the rising edge as an effective edge, the rising edge capture control circuit 27 in which the operation mode is set to the one-shot mode and the rising edge capture enable register 25 are examples of the update control means. A signal in which the CPU 3 writes “0” in the rising edge capture enable register 25 corresponds to an example of a permission signal.

  Similarly, for the falling edge capture register 31 having the falling edge as an effective edge, the falling edge capture control circuit 37 in which the operation mode is set to the one-shot mode and the falling edge capture enable register 35 are updated. A signal corresponding to an example of a control means, and a signal that the CPU 3 writes “0” in the falling edge capture enable register 35 corresponds to an example of a permission signal.

  In the usage example of the microcomputer 1, the falling edge (periodic edge) of the PMW signal corresponds to an example of a reference edge, and the rising edge (non-periodic edge) of the PMW signal corresponds to an example of a non-reference edge. The rising edge capture register 21 corresponds to an example of a first time storage register, the falling edge capture register 31 corresponds to an example of a second time storage register, and the interrupt request signal generation unit 41 generates an interrupt. The RAM 7 corresponds to an example of a means, and the RAM 7 corresponds to an example of a memory. 4 corresponds to an example of the first process, S210 of FIG. 4 corresponds to an example of the second process, S230 of FIG. 4 corresponds to an example of the third process, The previous occurrence time of the periodic edge corresponds to an example of reference edge previous occurrence time information, S240 of FIG. 4 corresponds to an example of the fourth process, and S270 of FIG. 4 corresponds to an example of the fifth process. 4 corresponds to an example of the sixth process, S260 of FIG. 4 corresponds to an example of the seventh process, and S250 of FIG. 4 corresponds to an example of the eighth process. .

  As mentioned above, although one Embodiment of this invention was described, this invention is not limited to such Embodiment at all, Of course, in the range which does not deviate from the summary of this invention, it can implement in a various aspect. .

  For example, as a modification, in S130 of FIG. 3, by writing “1” into the falling edge capture mode register 33, the processing mode in the timer unit 9 is also set to the one-shot mode for the falling edge (that is, The operation mode of the falling edge capture control circuit 37 is set to the one-shot mode). In S280 of FIG. 4, “0” is written not only to the rising edge capture enable register 35 but also to the falling edge capture enable register 25. You may deform | transform. And even if it deform | transforms in this way, the same effect as the effect demonstrated using FIGS. 6-9 is acquired.

Further, for each of the rising edge and the falling edge, the processing mode in the timer unit 9 may be fixed to the one-shot mode.
In the example of use in which the CPU 3 executes the interrupt process of FIG. 4 and calculates the duty ratio of the PWM signal, the processing mode in the timer unit 9 is fixed to the one-shot mode for the rising edge, and the falling edge For the edge, the processing mode in the timer unit 9 may be fixed to the normal mode.

  Conversely, if the periodic edge of the PWM signal is a rising edge, the processing mode in the timer unit 9 is fixed to the normal mode for the rising edge, and the processing in the timer unit 9 is performed for the falling edge. The form may be fixed to the one-shot mode.

  DESCRIPTION OF SYMBOLS 1 ... Microcomputer (microcomputer), 3 ... CPU, 5 ... ROM, 7 ... RAM, 9 ... Timer unit, 11 ... Bus, 13 ... Interrupt controller, 15 ... Edge detection port, 17 ... Terminal, 19 ... Free running timer, 21 ... Rising edge capture register, 23 ... Rising edge capture mode register, 25 ... Rising edge capture enable register, 27 ... Rising edge capture control circuit, 31 ... Falling edge capture register, 33 ... Falling edge capture mode register, 35 ... Falling edge capture enable register 37: Falling edge capture control circuit 41: Interrupt request signal generator 43: Interrupt request valid edge setting register

Claims (5)

When a valid edge that is an edge in a specific direction occurs in an input signal, the microcomputer has a time storage register that stores time information indicating the time at that time, and a CPU that executes a program,
When the time storage register stores the time information, update control means for prohibiting the time storage register from updating and storing the time information until receiving a permission signal output from the CPU is provided. about,
A featured microcomputer. The microcomputer according to claim 1,
The time storage register is provided as a first time storage register,
The input signal is a signal in which a reference edge that is one of a rising edge and a falling edge is generated a plurality of times,
The first time storage register is configured to store time information indicating a time at that time when a non-reference edge in a direction opposite to the reference edge occurs as the effective edge in the input signal,
Furthermore, the microcomputer
When the reference edge occurs in the input signal, a second time storage register for storing time information indicating a time at that time;
An interrupt generating means for generating an interrupt request when the reference edge occurs in the input signal;
In the interrupt processing that starts execution when the interrupt request is generated,
A first process of reading time information stored in the first time storage register;
A second process of reading time information stored in the second time storage register;
The value of the time information read in the second process and the value of the reference edge previous occurrence time information which is the time information read in the second process and stored in the memory when the interrupt process was executed last time A third process for calculating one cycle time, which is a time from the occurrence of the reference edge in the input signal to the current occurrence, from the difference between
From the difference between the value of the time information read in the first process and the value of the reference edge previous occurrence time information, from the previous occurrence of the reference edge to the input signal until the non-reference edge occurs A fourth process for calculating a pulse width time, which is a time, and
After the third process and the fourth process, perform a fifth process of updating and storing the time information read in the second process as new reference edge previous occurrence time information in the memory,
Further, after the first process, performing a sixth process for giving the permission signal to the update control means and allowing the first time storage register to update and store the time information,
A microcomputer characterized by. The microcomputer according to claim 2,
The input signal is a PWM signal having a constant generation period of the reference edge,
In the interrupt process, the CPU performs a seventh process of calculating a duty ratio of the PWM signal from the one cycle time calculated in the third process and the pulse width time calculated in the fourth process. What to do,
A microcomputer characterized by. The microcomputer according to claim 3,
In the interrupt process, the CPU performs an eighth process for determining whether or not the one cycle time calculated in the third process is within a predetermined normal range. If it is determined that one cycle time is not within the normal range, skipping the seventh process;
A microcomputer characterized by. The microcomputer according to claim 4,
When the CPU determines that the one cycle time is not within the normal range by the eighth process in the interrupt process, the CPU also skips the fifth process.
A microcomputer characterized by.

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