JP5942904B2 - Processing equipment - Google Patents

Description

  The present invention relates to a multitasking processing apparatus that processes a plurality of tasks with priorities in parallel, and initializes a plurality of data stored in a data area.

  Usually, the processing device is configured to include a calculation unit and a storage unit. In addition, the processing device may initialize the entire data area in which a plurality of data is stored in the storage unit for some reason. In this way, when initializing the entire data area, other tasks (high priority tasks) are executed so that the data area being initialized is not referred to in order to maintain consistency of the entire data area. It is necessary to. In other words, during the initialization of the data area, it is necessary to prevent data from being read from or written to this data area.

  Therefore, as disclosed in Patent Document 1, it is conceivable that input to the external interrupt terminal is prohibited after the CPU is reset until the initial value setting to the RAM is completed. In other words, while the entire data area is being initialized, it is conceivable to prohibit interruption of other tasks.

JP-A-60-116862

  As described above, by prohibiting interruption of other tasks, it is possible to prevent other tasks from being executed and to refer to the data area being initialized. However, while the entire data area is being initialized, interrupts of other tasks are prohibited, so the interrupt prohibition time increases in proportion to the amount of data to be initialized, and the real-time responsiveness decreases. There is.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a processing apparatus capable of suppressing a reduction in real-time responsiveness.

In order to achieve the above object, the present invention provides:
A multi-task processing device (10) that includes a calculation unit (11) and a storage unit (12), and processes a plurality of tasks provided with priority in parallel.
The storage unit includes a data area in which a plurality of data is stored,
The computation unit initializes all data stored in the data area by repeatedly performing initialization using at least one of a plurality of data as an initialization unit as one of a plurality of tasks. ,
A prohibition means (S40) for prohibiting interruption of a task when performing initialization in each initialization unit;
A first unit initialization unit (50) for performing initialization in units of initialization after the interruption of a task is prohibited by the prohibition unit;
And release means (S60) for releasing the prohibition of the interrupt of the task prohibited by the prohibiting means after the initialization in each initialization unit by the first unit initializing means is completed. .

  As described above, according to the present invention, when a plurality of data stored in the data area is initialized, all data stored in the data area is initialized by repeatedly performing initialization in units of initialization. Further, the present invention prohibits task interruption when initializing a plurality of data stored in the data area. However, the present invention cancels the prohibition of interrupts after the initialization in each initialization unit is completed. Therefore, in the present invention, when initializing a plurality of data stored in the data area, all of the data stored in the data area is repeatedly performed by repeatedly disabling interrupts, initializing in units of initialization, and canceling the prohibition of interrupts. Initialize the data. In other words, the present invention does not prohibit interrupts while initializing all data stored in the data area. As described above, according to the present invention, since the prohibition of the interrupt is released every time the initialization in each initialization unit is completed, it is possible to prevent the prohibition of the interrupt from continuing for a long time and to suppress the deterioration of the real-time responsiveness.

It is a block diagram which shows schematic structure of ECU in embodiment. It is a flowchart which shows the initialization process of CPU in embodiment. It is a flowchart which shows the unit initialization process of CPU in embodiment. It is an image figure which shows interruption prohibition and cancellation | release in embodiment. It is an image figure which shows the data structure in embodiment. It is a flowchart which shows the read-out process of CPU in embodiment. It is a flowchart which shows the write-in process of CPU in embodiment. It is a flowchart which shows the initialization process of CPU in a comparative example. It is a conceptual diagram which shows interruption prohibition and cancellation | release in a comparative example.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the present embodiment, the processing apparatus according to the present invention is applied to a microcomputer 10 provided in the ECU 100. Note that ECU is an abbreviation for Electronic Control Unit.

  As shown in FIG. 1, the ECU 100 includes a microcomputer 10, an output IF 20, and an input IF 30 as main parts. The ECU 100 is electrically connected to external devices such as the sensor 200 and the controlled object 300. The ECU 100 can acquire a detection signal from the sensor 200 via the input IF 30. Further, the ECU 100 can output a control signal to the controlled object 300 via the output IF 20. ECU 100 may acquire a signal from an ECU other than ECU 100 instead of sensor 200. Further, the control object 300 may employ an actuator such as a motor, an ECU other than the ECU 100, or the like.

  The ECU 100 can be applied to, for example, various electronic control devices that electronically control onboard equipment. In addition, vehicle-mounted devices that are controlled by the electronic control device include powertrain devices such as engines, transmissions, and brakes, body devices such as air conditioners, seats, and door locks, and information systems such as navigation, ETC, and radio. Equipment and safety equipment such as airbags.

  As shown in FIG. 1, the microcomputer 10 includes a CPU 11 and a storage unit 12 as main parts. Note that the microcomputer 10 may include an FPU 13 that performs floating-point arithmetic. That is, the microcomputer 10 is configured to include the FPU 13 when performing floating point arithmetic. The FPU 13 corresponds to a calculation unit in the claims of the present invention. FPU is an abbreviation for Floating Point number processing Unit.

  The CPU 10 corresponds to the calculation unit in the claims of the present invention. The CPU 11 reads out an operating system (hereinafter referred to as OS) program and various data stored in the storage unit 12 and executes predetermined calculations. The CPU 11 performs calculation while temporarily storing the calculation results in the storage unit 12. By performing the above, various processes are executed. CPU is an abbreviation for Central Processing Unit.

  In the present embodiment, a real-time OS (hereinafter, RTOS) that processes a plurality of tasks in parallel and performs a task schedule in real time is employed as the OS. This RTOS is designed with emphasis on executing processing in real time. For this reason, it is important to observe time constraints in the resource management of the storage unit 20 and peripheral circuits (A / D, timer, buffer, etc.) not shown.

  Priorities are set in advance for a plurality of tasks. The CPU 11 switches tasks based on this priority. In other words, task switching is performed based on a preset task priority, and the task with the highest priority among the tasks in the executable state is executed. Therefore, the microcomputer 10 can be referred to as a multi-task processing device that processes a plurality of tasks with priorities in parallel.

  Furthermore, as shown in FIG. 5, the microcomputer 10 has an initialization flag 11a and an update flag 11b, and manages data in these two flags. In other words, the CPU 11 is an initial stage in which one of initialization information indicating that the data area 12a described later is being initialized and non-initialization information indicating that the data area 12a is not being initialized is set. An in-process flag 11a is provided. One initialization flag 11a is provided for the data area 12a. In the present embodiment, 1 is used as the in-initialization information and 0 is used as the non-initialization information. However, the present invention is not limited to this. Thus, by providing the initialization flag 11a, the CPU 11 can grasp (recognize) whether or not the data area 12a is being initialized.

  Further, the CPU 11 is provided for each initialization unit to be described later, initialized information indicating that each initialization unit has been initialized, and uninitialized indicating that each initialization unit has not been initialized. An update flag 11b in which any of the information is set is provided. That is, one update flag 11b is provided for each initialization unit. In other words, one update flag 11b is provided for data included in each initialization unit.

  For example, when one data is used as an initialization unit, one update flag 11b is provided for each data. When two data are used as initialization units, one update flag 11b is provided for the two data. Therefore, the update flag corresponding to the data included in the initialization unit that has been initialized indicates the update flag corresponding to the data that has been initialized. Each update flag 11b can also be referred to as being provided corresponding to the data number of each data in the data area 12a.

  In this embodiment, 1 is adopted as the initialized information and 0 is adopted as the uninitialized information. However, the present invention is not limited to this. Thus, by providing the update flag 11b, the CPU 11 can grasp whether or not the data of each initialization unit has been initialized. Further, it is possible to avoid a state in which only some data is not initialized.

  Note that the CPU 11, for example, a read process for reading data from the storage unit 12, a write process for writing data to the storage unit 12, an initialization process for initializing the data area of the storage unit 12, a prohibition process for prohibiting interruption, Execute processing such as release processing to release. The processing operation of the CPU 11 will be described in detail later.

  The storage unit 12 includes a ROM, a RAM, and a register. The storage unit 12 is collectively managed with, for example, ROM, RAM, and registers as one address space. As described above, the storage unit 12 stores RTOS programs, various data, and data used in arithmetic processing. Note that ROM is an abbreviation for Read Only Memory, and RAM is Random Access Memory.

  Further, as shown in FIG. 5, a part of the storage unit 12 is provided with a data area 12a in which a plurality of data is stored. In other words, the storage unit 12 has a unified data area 12a. In this data area 12a, N pieces of data with data numbers 1 to N are stored. N is a natural number of 2 or more. In the data area 12a, for example, a plurality of collected data used in a certain task or a plurality of data to be processed in an integrated manner is stored. In addition, when data having a large data size and taking time to initialize all of the data stored in the data area 12a is employed, the effect of the present invention becomes remarkable.

  The plurality of data stored in the data area 12a includes intermediate data (floating point) of a program created by automatic code generation, buffer data (control learning value) of an external storage device, and freeze frame when detecting a diagnosis. Data can be used. These data are characterized in that the data size is large and it takes time to initialize all of them.

  Note that when a non-number occurs in a floating-point operation, all subsequent calculation results become non-number, and all data must be initialized. Therefore, when the intermediate data is adopted, the CPU 11 starts the processing of the flowchart shown in FIG. 2 described later when the occurrence of a non-number is detected in the floating point calculation. Further, when the buffer data is adopted, the CPU 11 will be described later when detecting an abnormality of the buffer data (outside the upper / lower limit range) or when there is an instruction to reset the data from an external device of the ECU 100. The process of the flowchart shown in FIG. Further, when freeze frame data is employed, the CPU 11 starts the processing of the flowchart shown in FIG. 2 to be described later when there is an instruction to clear the data from an external device of the ECU 100.

  As shown in FIG. 5, a part of the storage unit 12 (for example, a ROM) is provided with an initial value table 12 b in which initial values of each data in the data area 12 a are stored. That is, the initial value table 12b stores a plurality of initial value data corresponding to each data in the data area 12a.

  Here, the processing operation of the CPU 11 in the microcomputer 10 will be described with reference to FIGS. When the initialization condition indicating that the initialization of all data stored in the data area 12a is executed is established, the CPU 11 executes the initialization process shown in the flowchart of FIG. As described above, the initialization condition can be considered to be satisfied when an abnormality of data stored in the data area 12a is detected or when an initialization instruction is received from an external device. That is, the CPU 11 performs initialization processing of a plurality of data stored in the data area 12a as one of the plurality of tasks.

  In step S10, 0 is set to all the elements of the update flag 11b (first update means). When starting initialization of all data stored in the data area 12a, the CPU 11 sets all update flags 11b to 0. In other words, when the initialization condition is satisfied, the CPU 11 sets all update flags 11b to 0 before executing a data initialization loop described later. This is to make it possible to grasp whether or not each data stored in the data area 12a has been initialized.

  In step S20, 1 is set to the in-initialization flag 11a (second updating means). When starting the initialization of all data stored in the data area 12a, the CPU 11 sets 1 to the in-initialization flag 11a. In other words, when the initialization condition is satisfied, the CPU 11 sets the initialization flag 11a to 1 before executing a data initialization loop described later. This is to make it possible to grasp whether or not the data area 12a is being initialized. Therefore, the CPU 11 can grasp whether or not the data area 12a is being initialized by checking the value of the initialization flag 11a.

  As described above, when the initialization condition is satisfied, the CPU 11 first sets 0 to all the update flags 11b and sets 1 to the in-initialization flag 11a. Thereafter, the CPU 11 executes the processing after step S30.

  In steps S30 to S70, a data initialization loop is executed. The CPU 11 initializes all data stored in the data area by repeatedly performing initialization in the initialization unit using at least one of the data in the data area 12a as an initialization unit (data initialization). Loop means). That is, the CPU 11 repeatedly executes the processing from step S40 to step S60 until the initialization of all data in the data area 12a is completed.

  In other words, the CPU 11 divides the data stored in the data area 12a into a plurality of pieces, and initializes each divided data (or each data group) in order, so that all the data stored in the data area 12a is stored. Initialize the data. The CPU 11 divides a plurality of data stored in the data area 12a into initialization units including at least one data, and sequentially initializes each divided data to store the data in the data area 12a. In other words, all data is initialized. The initialization unit can also be referred to as a unit that the CPU 11 initializes at a time. Step S30 is a loop end indicating the start of the data initialization loop, and step S70 is a loop end indicating the end of the data initialization loop.

  In this embodiment, as an example, as shown in FIG. 5, one data is used as an initialization unit. That is, the CPU 11 of the present embodiment initializes all data stored in the data area 12a with the data corresponding to each data number as an initialization unit. More specifically, the data area 12a stores a plurality of data with data numbers 1 to N. The CPU 11 initializes all data stored in the data area 12a by performing unit initialization processing N times with the data of each data number as an initialization unit.

  However, the initialization unit only needs to include at least one piece of data. Therefore, two or more data can be used as an initialization unit. However, all data stored in the data area 12a cannot be made into one initialization unit.

  In the data initialization loop, first, the process of step S40 is executed. In step S40, interrupt inhibition is started (inhibiting means). The CPU 11 prohibits task interruption when performing initialization in each initialization unit. In other words, before executing the processing in step S50, the CPU 11 prohibits interruption of a task having a higher priority than this task, which is an initialization process for a plurality of data stored in the data area 12a.

  In step S50, single data initialization processing is executed (first unit initialization means). The CPU 11 performs initialization in units of initialization after task interruption is prohibited in step S40. Step S50 is a process for performing initialization in units of initialization. However, in this embodiment, since one data is used as an initialization unit, it is described as a single data initialization process.

  This single data initialization process will be described with reference to the flowchart of FIG. In step S51 of FIG. 3, the update flag of the initialization target data is determined. If the CPU 11 determines that 0 is set in the update flag 11b corresponding to the initialization target data, the CPU 11 regards that initialization is necessary and proceeds to step S52. If the CPU 11 determines that 1 is set in the update flag 11b corresponding to the initialization target data, the CPU 11 regards that there is no need for initialization and ends the processing shown in the flowchart of FIG. Note that the initialization target data is one of a plurality of data stored in the data area 12a, and is data to be initialized in the current single data initialization process.

  As described above, when 1 is set in the update flag 11b corresponding to the initialization target data, the CPU 11 does not execute the processing from step S52 to step S54 described later. Even though all update flags 11b are set to 0 in step S10, the update flag 11b corresponding to the initialization target data is set to 1 because it is updated before the initialization target data is initialized. It is because it has been. As will be described in detail later, the CPU 11 can update the initialization target data by executing another task before initializing the initialization target data. Therefore, in this case, in order to give priority to the value updated while executing other tasks before the initialization, the processing from step S52 to step S54 is not executed. This point will be described later with reference to FIG.

  Note that the CPU 11 can grasp (specify) the initialization target data that is the current initialization target from among a plurality of data stored in the data area 12a by using a loop counter or the like. That is, the CPU 11 can grasp the data (or data number) to be initialized in each single data initialization process by using a loop counter or the like.

  In step S52, an initial value is read. The CPU 11 reads initial value data corresponding to the initialization target data from the initial value table 12b. In step S53, the initial value is written. The CPU 11 writes the initial value data read in step S52. That is, the CPU 11 rewrites (updates) the initialization target data to the initial value data read in step S52. As a result, the initialization target data that is the current initialization target can be initialized.

  In step S54, 1 is set in the update flag 11b (first update means). The CPU 11 sets 1 to the update flag 11b corresponding to the initialization target data that has been initialized in the single data initialization process. In other words, the CPU 11 sets 1 to the update flag 11b corresponding to the data number of the data that has been initialized. In other words, the CPU 11 can also be described as setting 1 to the update flag corresponding to the initialization unit that has been initialized in the single data initialization process.

  For example, in FIG. 5, when the target of the current single data initialization process is data of data number 3, when the initialization of data of data number 3 is completed, the update flag 11b corresponding to data number 3 Set 1 to. Therefore, FIG. 5 shows that data numbers 1 to 3 have been initialized, and data numbers 4 to N have not been initialized. In the data area 12a in FIG. 5, ○ (maru) and x (cross) are shown for easy understanding of the drawing. ○ indicates that initialization has been completed, and x indicates that initialization has not been performed.

  In this way, the CPU 11 sets 0 to all the update flags 11b in the above-described step S10, and sets 1 to the update flag 11b corresponding to the data that has been initialized in step S54. Thereby, the CPU 11 can grasp whether or not the data corresponding to each update flag 11b has been initialized by checking each update flag 11b. That is, the CPU 11 can grasp whether or not each data stored in the data area 12a has been initialized. When the process in step S54 is completed, the process returns to step S60 in the flowchart shown in FIG.

  In step S60, the interrupt prohibition is ended (cancellation means). After completing the initialization in the single data initialization process in step S50, the CPU 11 cancels the prohibition of the task interrupt that was prohibited in step S40. Since the CPU 11 executes step S50 in the interrupt disabled state, the CPU 11 is prevented from accessing the data area 12a by executing a task having a higher priority during the data initialization and update flag 11b operations. it can. That is, when the CPU 11 executes a task having a higher priority, it is possible to prevent data from being read from or written to the data area 12a.

  As described above, the CPU 11 calls the single data initialization process after setting the interrupt disabled state inside the data initialization loop, and returns to the interrupt enabled state when the single data initialization process is completed. In other words, according to the present invention, the interrupt disabled state is maintained only during the single data initialization process, and an interrupt is possible before the next data is initialized.

  As described above, the CPU 11 repeatedly performs initialization in units of initialization, and when the initialization of all data in the data area 12a is completed, executes the processing in step S80. In step S80, 0 which is non-initialization information is set in the in-initialization flag 11a (second updating means).

  Thus, when initializing a plurality of data stored in the data area 12a, the microcomputer 10 initializes all data stored in the data area 12a by repeatedly performing initialization in units of initialization. To do. In addition, when initializing a plurality of data stored in the data area 12a, the microcomputer 10 prohibits task interruption. However, the microcomputer 10 cancels the prohibition of the interrupt after the initialization in each initialization unit is completed. Therefore, according to the present invention, when a plurality of data stored in the data area 12a is initialized, the interrupt is prohibited, the initialization in the initialization unit, and the interrupt prohibition are repeatedly performed, so that the data is stored in the data area 12a. Initialize all data.

  In other words, the microcomputer 10 does not prohibit interruption during the initialization of all the data stored in the data area 12a. As described above, the microcomputer 10 cancels the prohibition of the interrupt every time the initialization in each initialization unit is completed, so that the prohibition of the interrupt can be prevented from continuing for a long time and the deterioration of the real-time response can be suppressed.

  Here, the effect of the microcomputer 10 will be described in comparison with the microcomputer of the comparative example. The microcomputer of the comparative example includes a CPU, a storage unit, and the like, and is hereinafter referred to as a comparative example microcomputer. The comparative microcomputer has a data area similar to the data area 12a. When the initialization condition indicating that the CPU of the comparative example microcomputer executes the initialization of all the data stored in the data area is established as in the microcomputer 10, the initialization process shown in the flowchart of FIG. Execute.

  In step S300, interrupt inhibition is started. The CPU of the comparative example microcomputer prohibits task interruption before initialization in each initialization unit.

  In steps S310 to S330, a data initialization loop is executed. The CPU of the comparative example microcomputer initializes all data stored in the data area by repeatedly performing initialization in the initialization unit using at least one of the data in the data area as an initialization unit. That is, the CPU of the comparative example microcomputer executes steps S310 to S330 until the initialization of all data in the data area is completed.

  In step S340, the interrupt prohibition ends. The CPU of the comparative example microcomputer cancels the prohibition of the task interrupt that has been prohibited in step S300 for the first time after the initialization of all the data in the data area is completed.

  Therefore, as shown in FIG. 9, the comparative example microcomputer initializes a plurality of data stored in the data area between the timing t1 and the timing t2, during the entire period from the timing t1 to the timing t2. Disable interrupts.

  On the other hand, as shown in FIG. 4, when the microcomputer 10 initializes a plurality of data stored in the data area 12a between timing t1 and timing t2, initialization of each initialization unit is completed. Cancel the interrupt disable every time. Therefore, the microcomputer 10 can interrupt the task even between the timing t1 and the timing t2. As described above, the microcomputer 10 can prevent the interruption of interruption for a long time from continuing as compared with the comparative example microcomputer, and can suppress a decrease in real-time response. In other words, the microcomputer 10 can suppress a reduction in real-time responsiveness by limiting the interrupt prohibition period during initialization to initialization of data included in each initialization unit instead of all data.

  Therefore, for example, when intermediate data is adopted as data to be initialized, normal calculation can be performed even while the intermediate data is being initialized. In addition, when buffer data is adopted as the data to be initialized, normal control can be performed even while the buffer data is being initialized. In addition, when freeze frame data is employed as the data to be initialized, writing to the data area 12a is possible even while the freeze frame data is being initialized.

  Further, as described above, in the case of the microcomputer of the comparative example, there is a problem that the interrupt prohibition time becomes longer in proportion to the amount of data to be initialized and the real-time response is lowered. Furthermore, this microcomputer may be applied to, for example, an electronic control device (hereinafter referred to as an engine ECU) that electronically controls a vehicle engine. When the number of pulses generated by the engine rotation sensor is one per 30 ° of engine rotation, the engine ECU is 1 / (6000/60) / (360/30) = 830 [μs] when the engine is 6000 revolutions per minute. It is necessary to perform pulse input processing every time. However, the microcomputer of the comparative example prohibits interrupts so that processing other than initialization does not operate. Therefore, in the microcomputer of the comparative example, when initializing the amount of data that takes several hundreds μs for initialization, the pulse input processing may not be in time, and engine control may malfunction.

  On the other hand, even when the microcomputer 10 initializes a plurality of data stored in the data area 12a, the microcomputer 10 cancels the prohibition of interrupt every time initialization of each initialization unit is completed. Therefore, the microcomputer 10 is applied to the engine ECU, and even when the amount of data that takes several hundreds of μs to be initialized is initialized, the pulse input processing is not in time and the engine control is prevented from malfunctioning. it can.

  Although not a prior art, a state variable indicating whether initialization is in progress is provided, and the CPU confirms the state variable before accessing the storage unit (before data access), and the initialization is in progress. It is also possible to postpone without reading / writing data areas. However, this method has a restriction that normal control cannot be executed because necessary data cannot be read and written during the initialization.

  For example, in a gasoline engine control device, a learning value for correcting the fuel injection amount and the ignition timing may be stored in a data area serving as a buffer of an external storage device. If the control of the ignition device or the fuel injection device is postponed just because the learning value cannot be read during the data area initialization, the engine stops.

  In general, the microcomputer may periodically transmit data inside the control device on which the microcomputer is mounted to an external device of the control device through communication means. As an example of data to be transmitted periodically, the engine coolant temperature, the learning value for air-fuel ratio correction, and the like in the engine control device can be given. If the data to be transmitted is stored in the data area being initialized, data transmission is stopped until the initialization is completed. Therefore, an external device that periodically receives this data may consider it as a timeout and determine a communication error.

  On the other hand, even when the microcomputer 10 initializes a plurality of data stored in the data area 12a, the microcomputer 10 cancels the interrupt inhibition every time the initialization of each initialization unit is completed. That is, the microcomputer 10 can write data into the data area 12a and read data from the data area 12a even when initializing a plurality of data stored in the data area 12a.

  Therefore, even if the data which is the learning value for correcting the fuel injection amount and the ignition timing as described above, the data to be transmitted, and the like are stored in the data area 12a, the microcomputer 10 is configured as described above. It is possible to suppress the occurrence of such problems. That is, even when the microcomputer 10 initializes the data that is the learning value stored in the data area 12a, until the initialization of all the data to be initialized is completed, the microcomputer 10 It is not necessary to postpone the control, and the engine can be prevented from stopping. Further, even when the microcomputer 10 initializes the data to be transmitted stored in the data area 12a, it is not necessary to stop the data transmission until the initialization of all the data to be initialized is completed. It can suppress that it is determined as a communication abnormality from an external device. As described above, the microcomputer 10 can suppress the problem that it becomes impossible to read and write necessary data during the execution of the initialization, and the normal control cannot be executed.

  As described above, the CPU 11 interrupts a task having a higher priority than the task of the initialization process while canceling the prohibition of the task interrupt, and performs data processing from the data area 12a by performing the processing of this task. Can be read out. In addition, while canceling the prohibition of task interruption, the CPU 11 interrupts a task having a higher priority than the task of the initialization process, and writes data to the data area 12a by performing this task processing. Is possible.

  Here, processing in the case where a task interrupt is performed during initialization will be described. First, the reading process of the CPU 11 will be described with reference to FIG. FIG. 6 is a flowchart of the read request process. When there is a data read request, the CPU 11 executes the processing shown in the flowchart of FIG. This read request is a request indicating reading data from the data area 12a.

  In step S110, the in-initialization flag 11a is determined. The CPU 11 determines whether 0 is set in the initialization flag 11a or 1 is set. This is to determine whether or not the data area 12a is being initialized, that is, whether or not the processing from step S10 is being executed. If the CPU 11 determines that 0 is set in the in-initialization flag 11a, the CPU 11 considers that the data area 12a is not being initialized, and proceeds to step S160. On the other hand, if the CPU 11 determines that 1 is set in the initialization flag 11a, the CPU 11 regards the data area 12a as being initialized and proceeds to step S120.

  In step S120, the update flag of the read target data is determined. If the update flag 11b corresponding to the read target data is set to 0, the CPU 11 assumes that the data area 12a is being initialized, but has not yet initialized the read target data, and proceeds to step S130. . On the other hand, if 1 is set in the update flag 11b corresponding to the read target data, the CPU 11 assumes that the data area 12a is being initialized and that the read target data has already been initialized, and the process proceeds to step S160. move on. The read target data corresponds to the target data in the claims of the present invention. In the present embodiment, one data among a plurality of data stored in the data area 12a is adopted as the read target data.

  Note that the processing in steps S130 to S150 is the same as the processing in steps S40 to S60 described above. That is, in steps S130 to S150, the CPU 11 initializes single data (in this case, data to be read) after starting prohibition of interrupt, and thereafter ends interrupt prohibition. In step S160, the value is read out. At this time, the CPU 11 reads the read target data from the data area 12a.

  That is, the CPU 11 interrupts the task during initialization of the data area 12a, and prohibits the task interrupt when reading the data to be read (second prohibiting means). Then, the CPU 11 initializes the data to be read while the task interrupt is prohibited (second unit initialization unit). Then, after the initialization of the read target data is completed, the CPU 11 cancels the prohibition of the task interrupt that has been prohibited by the second prohibiting unit (second canceling unit). Further, when the prohibition of task interruption is canceled, the CPU 11 reads data to be read (reading means). As a result, when the data to be read is read during the interrupt processing, it is possible to prohibit interruption of a task having a higher priority and to protect the data area 12a.

  In this way, when the initialization flag 11a is set to 1 and the update flag 11b corresponding to the read target data is set to 0, the CPU 11 initializes the read target data (second). Unit initialization means). At this time, the CPU 11 initializes the initialization unit including the read target data. Then, the CPU 11 reads the data to be read after the initialization (reading means).

  For example, in the example shown in FIG. 5, when the data with the data number 2 is the data to be read, the CPU 11 reads out this data because the data with the data number 2 has already been initialized. On the other hand, when the data with the data number N is the read target data, the CPU 11 reads the data number N after initializing it because the data with the data number N has not been initialized yet. Note that the CPU 11 returns to step S30 in FIG. 2 after executing the processing of steps S120 and S160, or after executing the processing of steps S120 to S160.

  As described above, the CPU 11 initializes the read target data if the read target data is uninitialized when the data is read from the data area 12a being initialized by executing the high priority task. Read from. The fact that 1 is being set in the in-initialization flag 11a (when it is determined to be 1 in step S110) indicates that the data stored in the data area 12a needs to be initialized. Therefore, as described above, by reading the read target data after being initialized, it is possible to suppress reading of data that needs to be initialized without being initialized.

  On the other hand, when the data area 12a is not being initialized and when the read target data has already been initialized, it is not necessary to reinitialize the read target data. Therefore, when the CPU 11 determines that 0 is set in step S110, the CPU 11 performs step S160 without performing the processes of steps S120 to S150, and reads the read target data. If the CPU 11 determines that 1 is set in step S120, the CPU 11 proceeds to step S160 and reads the read target data without performing the processes in steps S130 to S150.

  Next, the writing process of the CPU 11 will be described with reference to FIG. FIG. 7 is a flowchart of the write request process. When there is a data write request, the CPU 11 executes the process shown in the flowchart of FIG. The write request is a request indicating that data of a predetermined data number in the data area 12a is rewritten with another data. In other words, it is a request indicating that data of a predetermined data number in the data area 12a is updated with other data. Note that data to be written to the data area 12a is also referred to as write data. In the present embodiment, one data is adopted as the write data.

  In step S210, the in-initialization flag 11a is determined. The CPU 11 determines whether 0 is set in the initialization flag 11a or 1 is set. This is to determine whether or not the data area 12a is being initialized, that is, whether or not the processing from step S10 is being executed. If the CPU 11 determines that 0 is set in the initialization flag 11a, the CPU 11 considers that the data area 12a is not being initialized and proceeds to step S220. On the other hand, if the CPU 11 determines that 1 is set in the initialization flag 11a, the CPU 11 considers that the data area 12a is being initialized and proceeds to step S230.

  In step S220, the value is updated. In other words, data with a predetermined data number is rewritten to write data. That is, since the data area 12a is not being initialized, the CPU 11 writes the write data to the data area 12a without performing any special processing.

  On the other hand, in step S230, interrupt inhibition is started (third inhibition means). In this way, the CPU 11 interrupts a task during the initialization of the data area 12a, and when writing data by executing this task, first, the task interrupt is prohibited.

  In step S240, the correctness of the write data is checked (check means). That is, when writing data to the data area 12a, the CPU 11 checks the correctness of the write data when the initialization flag is set to 1. This is to prevent incorrect data from being written to the data area 12a. Further, the CPU 11 checks the correctness of the data while prohibiting the interruption in step S230. If the CPU 11 determines that the data is correct, the process proceeds to step S250. If the CPU 11 determines that the data is not correct, the process proceeds to step S260. This correctness check will be described later.

  In step S250, the value is updated (writing means). When the CPU 11 determines that the write data is correct, the CPU 11 writes the write data determined to be correct to the data area 12a. Thereby, correct data can be written in the data area 12a. Note that the CPU 11 writes the write data while interrupts are prohibited in step S230.

  In step S250, when a plurality of data is used as an initialization unit, only a part of the data in the initialization unit may be updated. That is, only a part of the data in the initialization unit may be rewritten with the write data determined to be correct. In such a case, it is preferable that data other than the data updated by the write data among the plurality of data included in the initialization unit is rewritten to the initial value. In other words, in a plurality of data included in the initialization unit, data other than data corresponding to the write data is preferably rewritten to the initial value.

  In step S260, single data is initialized (writing means). When the CPU 11 determines that the write data is not correct, the CPU 11 initializes data corresponding to the write data in the data area 12a in order to prevent incorrect data from being written to the data area 12a. At this time, the CPU 11 performs initialization in an initialization unit including data corresponding to the write data. As a result, even when the data to be written is not correct, it is possible to prevent incorrect data from being written. Note that the CPU 11 initializes data while interrupts are prohibited in step S230.

  The processing in step S260 is the same as that in step S50 described above. However, in step S50, initialization is performed in an initialization unit including initialization target data specified by a loop counter or the like, whereas in step S260, initialization in an initialization unit including data corresponding to write data is performed. Perform initialization.

  In step S270, 1 is set to the update flag 11b. The CPU 11 sets 1 in the update flag 11b in order to record that the data that has not yet been initialized has been updated in the data area 12a being initialized.

  In step S280, the interrupt prohibition is ended (third canceling means). After completing the initialization in step S260 or the writing in step S250, the CPU 11 cancels the prohibition of the task interrupt prohibited in step S230.

  The CPU 11 returns to step S30 in FIG. 2 after executing the process of step S280. Further, when the CPU 11 returns to the flowchart of FIG. 2 after executing step S280, the data initialized in step S260 or the data written in step S250 may be set as the initialization target data. In such a case, the CPU 11 determines that 1 is set in the update flag 11b in the determination in step S51 described above. Therefore, as described above, when the CPU 11 determines that 1 is set in the update flag 11b in step S51, the CPU 11 does not execute the processing of steps S52 to S54, but the data initialized in step S260 or the step The data written in S250 is prioritized.

  For example, in the example illustrated in FIG. 5, when the data with the data number N is the data to be written, the CPU 11 initializes the data with the data number N or updates it to the write data. Then, the CPU 11 sets 1 to the update flag 11b.

  As described above, when writing data during initialization of the data area 12a, the microcomputer 10 first sets the interrupt disabled state, and then performs initialization in step S260 or writing in step S250. As a result, when initialization is performed in step S260 or writing is performed in step S250, interruption of a task with a higher priority can be prohibited, and the data area 12a can be protected.

  Several correctness checking methods in step S230 are conceivable. Here, an example of the correctness check method will be described.

  First, the case where the microcomputer 10 includes the FPU 13 and a floating point number is stored as a plurality of data in the data area 12a will be described. In this case, the FPU 13 determines that the write data is not correct when the write data is non-numeric, and determines that the write data is correct when the write data is not non-number (check means).

  As another method, the CPU 11 determines that the write data is not correct when the write data is not within the predetermined range, and determines that the write data is correct when the write data is within the predetermined range (check unit). Even in this way, it is possible to determine whether or not the write data is correct.

  In the present embodiment, when the data area 12a is initialized, an example of initializing with the initial value data stored in the initial value table 12b is employed. However, the present invention is not limited to this. When the initial values of all the data in the data area 12a are the same data (for example, a fixed initial value such as 0), initialization may be performed with this fixed initial value. Thus, it is not necessary to provide the initial value table 12b by initializing with the fixed initial value. Therefore, the processing time required for initialization can be reduced, and the amount of use of the storage unit 12 can be reduced by the amount of the initial value table 12b.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit of the present invention.

  10 microcomputer, 11 CPU, 11a initialization flag, 11b update flag, 12 storage unit, 12a data area, 12b initial value table, 13 FPU, 20 output IF, 30 input IF, 100 ECU, 200 sensor, 300

Claims (6)

A multi-task processing device (10) that includes a calculation unit (11) and a storage unit (12), and processes a plurality of tasks provided with priority in parallel.
The storage unit includes a data area in which a plurality of data is stored,
The calculation unit initializes all data stored in the data area by repeatedly performing initialization using at least one of the plurality of data as an initialization unit as one of the plurality of tasks. Is what
Prohibiting means (S40) for prohibiting interruption of the task when performing initialization in each initialization unit;
First unit initialization means (S50) for performing initialization in the initialization unit after interruption of the task is prohibited by the prohibition means;
Release means (S60) for canceling the prohibition of the interrupt of the task that has been prohibited by the prohibition means after the initialization in each initialization unit by the first unit initialization means has been completed. Characteristic processing device. An initializing flag (11a) in which one of initialization information indicating that the data area is being initialized and non-initialization information indicating that the data area is not being initialized is set;
Provided for each initialization unit, initialized information indicating that the data included in each initialization unit has been initialized, and not indicating that the data included in each initialization unit has not been initialized. An update flag (11b) in which any of the initialization information is set,
The computing unit is
When the initialization of all data stored in the data area is started, uninitialized information is set in all the update flags, and the initialization unit in which the initialization by the first unit initialization unit is completed First update means (S10, S54) for setting initialized information in the update flag corresponding to the data included in
When the initialization of all data stored in the data area is started, the in-initialization information is set in the in-initialization flag, and when the initialization of all the data is completed, the in-initialization flag is not initialized. Second update means (S20, S80) for setting information;
The processing apparatus according to claim 1, further comprising: The computing unit is
While the prohibition of the interrupt of the task is canceled by the canceling means, the task having a higher priority than the task of the initialization process is interrupted, and the task is processed from the data area. Data can be read
When reading target data to be read from the data area, information during initialization is set, and uninitialized information is set in the update flag corresponding to the target data, the target data Second unit initialization means (S140) for initializing an initialization unit including
Reading means (S160) for reading out the target data after being initialized by the second unit initialization means;
The processing apparatus according to claim 2, further comprising: The computing unit is
While the prohibition of the interrupt of the task is canceled by the canceling means, the task having a higher priority than the task of the initialization process is interrupted, and the task is processed to the data area. Data can be written,
Checking means (S240) for checking the correctness of the data to be written if the information being initialized is set when the data is written to the data area;
When it is determined that the data written by the check means is not correct, the initialization unit including the data in the data area corresponding to the data is initialized, and the data written by the check means is correct If it is determined, the writing means (S250, S260) for writing the data to the data area,
The processing apparatus according to claim 2, further comprising: In the data area, a floating point number is stored as the data,
5. The processing apparatus according to claim 4, wherein the check unit determines that the data to be written is not correct when the data to be written is non-numeric, and determines that the data to be written is correct when the data to be written is not a non-number.   5. The processing apparatus according to claim 4, wherein the check unit determines that the data to be written is not correct when the data to be written is not within a predetermined range, and determines that the data to be written is correct when the data to be written is within the predetermined range.

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