JP6009518B2 - Electronic control unit - Google Patents

Description

  The present invention relates to an electronic control device that can avoid a delay in arithmetic processing associated with exclusive control of shared resources in a multi-core microcontroller.

  An automobile or a ship is equipped with an electronic control device (hereinafter referred to as ECU) that controls the ignition timing of the engine and the steering motor. In recent years, an ECU equipped with a multi-core microcontroller has been used for the purpose of dealing with an increase in processing amount due to complicated control and reducing power consumption.

  In a multi-core microcontroller, each core executes a plurality of arithmetic processes in parallel. When these arithmetic processes share resources, for example, unintended data rewriting may occur due to simultaneous write access from each arithmetic process to the same memory address. In order to avoid such contention, it is necessary to perform exclusive control so that only one core can access the shared resource at a time.

  As a method of exclusive control, there is a method using a lock flag indicating an exclusive state. The arithmetic processing sets the lock flag before accessing the shared resource, and clears the lock flag after the access is completed. If the lock flag is already set, it indicates that another core is accessing the shared resource, so exclusive control is avoided by avoiding access to the shared resource until the lock flag is cleared. Can be realized.

  Here, a calculation method in which the lock flag cannot be set is known as a spin lock in which the lock flag is repeatedly set until the lock flag can be set. By doing so, it is possible to immediately set and access the shared resource if other arithmetic processing clears the lock flag. However, since the set trial is continued until the lock flag is cleared, there is a problem that the processing capability of the core cannot be utilized effectively and the execution of subsequent arithmetic processing in the same core is delayed.

  This will be described with reference to the example of FIG. FIG. 26 is an explanatory diagram showing an example of exclusive control execution according to the background art of the present invention. In FIG. 26, in the core 0, the arithmetic processing e0 is started at the cycle t0, and in the core 1, the arithmetic processing e1 and the subsequent arithmetic processing e2 are started at the cycle t1 (twice the length of t0) to perform the processing. , It is assumed that exclusive control for accessing the shared resource is executed in the arithmetic processing e0 and the arithmetic processing e1. Since the execution timing of this exclusive control is duplicated between the two cores, and the arithmetic processing e0 sets the lock flag first and accesses the shared resource, the arithmetic processing e1 clears the lock flag. During the time ts until this is done, only set trials that are not directly related to the control of the automobile or ship are repeatedly executed.

  As a result, the processing time of the arithmetic processing e1 becomes longer, the processing load on the core 1 increases, and the start time of the arithmetic processing e2 executed after the exclusive control in the arithmetic processing e1 is delayed. Further, since the length of the set trial time ts depends on the execution timing of the arithmetic processing e0 and the arithmetic processing e1 and the processing time of exclusive control of the arithmetic processing e0, the set trial time is larger than the substantial processing time related to control. There is a possibility that ts becomes longer and the processing load of the core 1 increases. In addition, as shown in FIG. 26, if the arithmetic processing that performs exclusive control is cyclically activated, the overlapping time (set trial time ts) of the exclusive control processing also occurs periodically.

  Therefore, as a method for shortening the lock flag set trial time, for example, Patent Document 1 proposes a method of changing the execution order of the arithmetic processing when the set trial time satisfies a predetermined condition. Patent Document 2 proposes a method for selecting whether to put the arithmetic processing to sleep or to add it to the end of the queue for waiting according to the set trial time, and to execute another arithmetic processing.

WO2012 / 001835 JP 2011-170414 A

  However, Patent Document 1 does not disclose how to change the execution order of the arithmetic processing according to the set trial time. Therefore, since the execution order does not take into account the set trial time, that is, the exclusive control process overlap time, the exclusive control process may still overlap even if the execution order of the arithmetic process is changed, and the set trial time may not be reduced. There are challenges.

  On the other hand, in the said patent document 2, the state of arithmetic processing is determined according to the set trial time. However, it does not disclose how long it takes to return from sleep or standby and resume exclusive control, and how to select another arithmetic process executed during that time. As in Patent Document 1, the set trial time is reduced. There is a problem that it may not be possible.

  The present invention has been made to solve the above-described problems in the conventional apparatus, and optimizes the execution order of the arithmetic processing according to the set trial time, which is the overlap time of the exclusive control processing, and is efficient. To provide an electronic control device that can reduce the processing load on the microcontroller by exclusive control and efficiently use the processing performance while reliably executing exclusive control on shared resources by shortening the set trial time It is an object.

An electronic control device according to the present invention includes:
A first processor that executes arithmetic processing;
A second processor that executes arithmetic processing in parallel with execution of arithmetic processing of the first processor;
An electronic control device comprising:
The first processor is configured to periodically execute a first calculation process and a plurality of second calculation processes according to a predetermined execution order,
The second processor is configured to periodically execute a third arithmetic process,
The first calculation process and the third calculation process are calculation processes that exclusively access a shared resource,
A lock flag that is set when any one of the first calculation process and the third calculation process exclusively accesses the shared resource;
When the shared resource is exclusively accessed by the third calculation process and the first calculation process cannot set the lock flag, the setting calculation is attempted until the first calculation process can set the lock flag. A set trial counter for counting the number of set trials to be repeated;
With
When the value of the set trial counter exceeds a predetermined threshold value,
Based on the value of the set trial counter, select at least one of the plurality of second arithmetic processes,
By changing the execution order of the first processing and the selected second arithmetic processing, and is configured to perform the calculation processing of the first processor,
It is characterized by this.

  According to the electronic control device of the present invention, at least one of the plurality of second calculation processes is selected based on the value of the set trial counter, and the selected second calculation process and the first calculation are selected. Since the execution order of the first processor is changed to execute the processing of the first processor, processing by exclusive control is performed by suppressing the overlap time in which multiple arithmetic processing accesses the shared resource exclusively. The load can be reduced and the processing performance of the microcontroller can be used efficiently. As a result, for example, a process that is performed as a lowest priority task such as a memory test can be executed for a longer time, and in addition to being able to efficiently use the processing performance of the microcontroller, it is possible to detect an abnormality early. It becomes like this.

It is a block diagram of the electronic control apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the arithmetic processing time table in the electronic controller which concerns on Embodiment 1 of this invention. It is a flowchart regarding the exclusive control process by the calculation process b in the electronic control apparatus which concerns on Embodiment 1 of this invention. It is a flowchart regarding the starting timing of task TA0 of the management process performed by the core A in the electronic control apparatus which concerns on Embodiment 1 of this invention. It is a time chart regarding the arithmetic processing a-the arithmetic processing i, the lock flag, the set trial counter, and the excess set trial frequency in the electronic control apparatus according to Embodiment 1 of the present invention. It is a block diagram of the electronic controller which concerns on Embodiment 2 of this invention. It is explanatory drawing which shows the arithmetic processing execution order table before the execution order change in the electronic controller which concerns on Embodiment 2 of this invention. It is a flowchart regarding the starting timing of task TA0 of the management process performed by the core A in the electronic control apparatus which concerns on Embodiment 2 of this invention. It is a time chart regarding the arithmetic processing a-the arithmetic processing i, the lock flag, the set trial counter, and the excess number of set trials in the electronic control apparatus according to Embodiment 2 of the present invention. It is explanatory drawing which shows the arithmetic processing execution order table after the execution order change in the electronic controller which concerns on Embodiment 2 of this invention. It is a block diagram of the electronic controller which concerns on Embodiment 3 of this invention. It is explanatory drawing which shows the arithmetic processing execution order storage table before the execution order change in the electronic control apparatus which concerns on Embodiment 3 of this invention. It is a flowchart in the starting timing of task TA0 of the management process performed with the core A in the electronic control apparatus which concerns on Embodiment 3 of this invention. It is a flowchart in the starting timing of the task TB of the management process performed with the core B in the electronic control apparatus which concerns on Embodiment 3 of this invention. It is a time chart of the arithmetic processing a-the arithmetic processing i, the lock flag, the set trial counter, the excess set trial frequency, and the change request flag in the electronic control apparatus according to Embodiment 3 of the present invention. It is explanatory drawing which shows the arithmetic processing execution order storage table after the first execution order change in the electronic control apparatus which concerns on Embodiment 3 of this invention. It is explanatory drawing which shows the arithmetic processing execution order table after the 1st execution order change in the electronic controller which concerns on Embodiment 3 of this invention. It is explanatory drawing which shows the arithmetic processing execution order storage table after the 2nd execution order change in the electronic controller which concerns on Embodiment 3 of this invention. It is a block diagram of the electronic controller which concerns on Embodiment 4 of this invention. It is explanatory drawing which shows the arithmetic processing execution order initial setting table in the electronic controller which concerns on Embodiment 4 of this invention. It is a flowchart of the exclusive control process by the arithmetic process b in the electronic control apparatus which concerns on Embodiment 4 of this invention. It is a flowchart in the starting timing of task TA0 of the management process performed with the core A in the electronic control apparatus which concerns on Embodiment 4 of this invention. In the electronic control unit according to Embodiment 4 of the present invention, the calculation process a to calculation process i, the lock flag, the set trial counter, the excess set trial count, the frequency change flag, and the core B state variable time when the operating frequency is changed It is a chart. In the electronic control unit according to Embodiment 4 of the present invention, arithmetic processing a to arithmetic processing i at the time of state change of core B, lock flag, set trial counter, excess set trial count, frequency change flag, core B state variable It is a time chart. In the electronic control unit according to Embodiment 4 of the present invention, arithmetic processing a to i when the set trial counter upper limit value of the set trial counter is exceeded, a lock flag, a set trial counter, an excessive set trial count, a frequency change flag, a core It is a time chart of a B state variable. It is explanatory drawing which shows the example of exclusive control execution concerning the background art of this invention.

Embodiment 1 FIG.
The electronic control apparatus according to Embodiment 1 of the present invention will be described below. FIG. 1 is a configuration diagram of an electronic control device according to Embodiment 1 of the present invention, and shows an ECU as an electronic control device mounted on an automobile. In FIG. 1, an electronic control unit (hereinafter referred to as ECU) 101 is connected to another ECU (not shown) via a CAN communication line 102, and transmits and receives data according to a communication protocol CAN. As a result, advanced vehicle control is realized.

  The ECU 101 is connected to a core A 103 as a first processor that executes calculations, a core B 104 as a second processor that executes calculations in parallel with the execution of calculations of the core A, a memory 105, and a CAN communication line 102. The CAN communication interface 122 is provided. The memory 105 includes a management process 106, an operation process a107, an operation process b108, an operation process c109, an operation process d110, an operation process e111, an operation process f112, an operation process g113, an operation process h114, Processing i 115, shared data 116 as a shared resource, lock flag 117, set trial counter 118, set trial count threshold 119, excess set trial count 120, and arithmetic processing time table 121 are provided.

  The core A 103 executes a management process 106 and calculation processes a107 to f112. The core B 104 executes the management process 106 and the calculation processes g113 to i115. Here, the arithmetic processing b108 executed by the core A103 as the first processor corresponds to the first arithmetic processing in the present invention, and the arithmetic processing a107 and arithmetic processing c109 to arithmetic processing f112 are in the present invention. This corresponds to the second calculation process. The arithmetic processing h114 executed by the core B104 as the second processor corresponds to the third arithmetic processing in the present invention, and the arithmetic processing g113 and the arithmetic processing i115 correspond to the fourth arithmetic processing in the present invention. .

  The management process 106 manages the activation and termination of the calculation processes a107 to i115 and adjusts the execution order.

  Arithmetic processing a107 to arithmetic processing i115 perform computations related to automobile control. The arithmetic processing b108, the arithmetic processing f112, and the arithmetic processing h114 execute exclusive control and access the shared data 116.

  The shared data 116 as a shared resource is written and accessed from the arithmetic processing b108 and the arithmetic processing h114. Further, it is read and accessed from the arithmetic processing f112.

  The lock flag 117 writes (sets) “1” when the arithmetic process b108, the arithmetic process f112, and the arithmetic process h114 access the shared data 116, and “0” when the access to the shared data 116 ends. Is a flag to write (clear).

  The initial value of the set trial counter 118 is “0”, and every time the arithmetic processing b108 of the core A103 tries to set the lock flag 117 in a state where the arithmetic processing h114 of the core B104 sets the lock flag 117, It is a counter that is incremented. That is, the count value as the value of the set trial counter 118 indicates the number of times that the setting of the lock flag 117 by the arithmetic processing b108 as the first arithmetic processing has failed.

  The set trial count threshold 119 is a threshold used for comparison with the set trial counter 118. In the first embodiment, the threshold value is “50”.

  The excess set trial count 120 stores the value of the set trial counter 118 when the value of the set trial counter 118 exceeds the set trial count threshold “50”.

  The arithmetic processing time table 121 is a table in which processing times of the arithmetic processing a107 to arithmetic processing e111 are described. This is shown in FIG. That is, FIG. 2 is a diagram showing an arithmetic processing time table of the electronic control apparatus according to Embodiment 1 of the present invention. The calculation process a107 and calculation process c109 are set to 0.4 [ms], the calculation process d110 is set to 1.0 [ms], and the calculation process e111 is set to 1.5 [ms]. As described above, in the first embodiment, it is assumed that approximate values of the processing times of the arithmetic processing a107, the arithmetic processing c109, the arithmetic processing d110, and the arithmetic processing e111 are clarified.

  The CAN communication interface 122 transmits the value of the shared data 116 received from the arithmetic processing f112 to the CAN communication line 102 as a CAN message in response to a trigger of the arithmetic processing f112 executed by the core A103.

  Next, the execution of the management process 106, the calculation process a107 to the calculation process i115 by the core A103 and the core B104 will be described. In the core A103, the management process 106 executes the calculation process a107 to the calculation process e111 as one task TA0 at a cycle tA. Further, the arithmetic processing f112 is executed as one task TA1 with the same cycle tA. In the core B104, the management process 106 executes the calculation process g113 to the calculation process i115 as one task TB with a period tB. In the first embodiment, it is assumed that the period tB is twice as long as the period tA. In the initial setting (default), the task TA0 is executed in the order of the calculation process a107 → the calculation process b108 → the calculation process c109 → the calculation process d110 → the calculation process e111. In the task TB, the calculation process g113 → the calculation process h114 → the calculation process. i115 is executed in this order. Both the core A 103 and the core B 104 execute a background task (not shown in FIG. 1) while there is no arithmetic processing to be executed, and execute an abnormality detection process such as an error check of the memory 105 with a low priority. .

  Next, the exclusive control executed when the arithmetic process b108 accesses the shared data 116 will be described. FIG. 3 is a flowchart related to the exclusive control process by the arithmetic process b of the electronic control apparatus according to Embodiment 1 of the present invention. In FIG. 3, the calculation process b108 reads the value of the lock flag 117 (step S301). It is determined whether the value of the read lock flag 117 is set or cleared (step S302). If the value of the lock flag 117 is cleared, the lock flag 117 is set (step S303), the shared data 116 is accessed and the value is written (step S304). On the other hand, if the lock flag 117 is not cleared, the set trial counter 118 is incremented (step S307), and the process returns to reading the value of the lock flag 117 (step S301). When the write access to the shared data 116 is completed, the lock flag 117 is cleared (step S305). Then, the value of the set trial counter 118 is compared with the set trial count threshold (“50”) (step S306), and if the value of the set trial counter 118 is equal to or smaller than the set trial count threshold, the series of processing ends. On the other hand, if the value of the set trial counter 118 exceeds the set trial count threshold, the set trial counter 118 is stored in the excess set trial count 120 (step S308), and then the set trial counter 118 is reset. (Step S309), a series of processing ends.

  The arithmetic processing f112 and the arithmetic processing h114 also execute exclusive control to access the shared data 116, but in the flowchart of FIG. 3, the set trial counter 118 is not incremented (step S307), and the lock flag 117 is set. If yes, the process returns to reading the value of the lock flag 117 (step S301). Further, after clearing the lock flag 117 (step S305), the processing regarding the set trial counter 118 is not executed, and the processing is immediately terminated. The rest is the same as the arithmetic processing b108.

  Next, the management process 106 when the task TA0 is activated in the core A103 will be described. FIG. 4 is a flowchart relating to the activation timing of task TA0 of management process 106 executed by core A103 in the electronic control apparatus according to Embodiment 1 of the present invention. In FIG. 4, the management process 106 refers to the value of the excess set trial count 120 (step S401), and if the value is “0” or less, it is not necessary to change the execution order. The execution of a107 to arithmetic processing e111 is started in the order of initial setting, and the management processing 106 is ended. When the value of the excess set trial count 120 is larger than “0”, the set trial time is calculated using the excess set trial count 120 (step S402). In the first embodiment, 10 [us / time] is used as the processing time for the set trial. This value can be obtained from the calculation result from the operating frequency and execution code of the core A 103 or from the actual measurement result.

  Subsequently, referring to the arithmetic processing time table 121, an arithmetic processing having a processing time closest to the calculated set trial time is selected (step S403). Then, the execution order is changed so that the selected arithmetic processing is executed before the arithmetic processing b108 that performs exclusive control to access the shared data 116 (step S404). Next, the excess set trial count 120 is reset to “0” (step S405), the execution of the arithmetic processing a107 to the arithmetic processing e111 is started according to the determined execution order, and the management processing 106 is ended.

  Next, a management process 106 that operates according to the flowcharts shown in FIGS. 3 and 4, an execution operation of each arithmetic process, a lock flag 117 at that time, a set trial counter 118, and an excess set trial count 120, This will be described with reference to the time chart of FIG. FIG. 5 is a time chart regarding arithmetic processing a to arithmetic processing i, a lock flag, a set trial counter, and an excess set trial count in the electronic control apparatus according to Embodiment 1 of the present invention. Note that the processing time of the management process 106 is not described on the time chart of FIG.

  In FIG. 5, when the task TA0 of the core A 103 is activated for the first time at time t500, the management process 106 determines that the change of the execution order is unnecessary because the value of the excess set trial count 120 is “0”. As a result, the arithmetic processing a107 to arithmetic processing e111 included in the task TA0 are executed in the order of initial setting of the arithmetic processing a107 → the arithmetic processing b108 → the arithmetic processing c109 → the arithmetic processing d110 → the arithmetic processing e111. At this time, since the task TB of the core B 104 is not at the start timing, the lock flag 117 is cleared, and in the exclusive control by the arithmetic processing b108, the lock flag 117 can be immediately set and written to the shared data 116. When the writing to the shared data 116 is completed, the lock flag 117 is cleared and the set trial counter 118 remains “0”, so that the exclusive control process is terminated.

  At time t501, the task TA1 of the core A103 is activated for the first time, and the arithmetic processing f112 included in the task TA1 is executed. The calculation process f112 also performs exclusive control, but the lock flag 117 can be set immediately. When the value of the shared data 116 is read, the arithmetic processing f112 performs transmission processing to the CAN communication line 102 via the CAN communication interface 122.

  At time t502, the task TB of the core B 104 is activated for the first time, and the arithmetic processing g113 to arithmetic processing i115 included in the task TB are executed in the order of initial setting of the arithmetic processing g113 → the arithmetic processing h114 → the arithmetic processing i115. Since the lock flag 117 is cleared at the start of the execution of the arithmetic processing h114 as the third arithmetic processing, the arithmetic processing h114 can immediately set the lock flag 117 as in the arithmetic processing f112.

  Subsequently, while the arithmetic processing h <b> 114 is being executed in the core B <b> 104, the time t <b> 503 (= t500 + (task TA <b> 0 cycle tA)) is reached, and the task TA <b> 0 is activated again in the core A <b> 103. Again, since the value of the excess set trial count 120 is “0”, the management process 106 determines that it is not necessary to change the execution order, and performs the arithmetic process a107 in the same order as that at the time t500. ~ Calculation process e111 is executed. However, since the lock flag 117 remains set by the calculation process h114 of the core B 104 even when the start time of the calculation process b108 for writing access to the shared data 116 is reached, the calculation process b108 immediately sets the lock flag 117. The set trial is repeated as shown in FIG. Each time the setting of the lock flag 117 fails, the set trial counter 118 is incremented. At time t504, the value of the set trial counter 118 exceeds the set trial count threshold (“50”). Nevertheless, the calculation process b108 repeats the set trial until the lock flag 117 is cleared.

  Next, at time t505, when the arithmetic processing h114 finishes writing to the shared data 116 and clears the lock flag 117, the arithmetic processing b108 that has repeated the setting trial can set the lock flag 117. At this time, the set trial counter 118 is set to “90” in the first embodiment. After the write access to the shared data 116 and the lock flag 117 being cleared, the value of the set trial counter 118 (“90”) is larger than the set trial count threshold (“50”). Is stored with the value of the set trial counter 118 (“90”), and the set trial counter 118 is reset. When the calculation process b108 ends, the calculation processes c109 to e111 are executed.

  Since the processing content of the calculation processing f112 of the task TA1 to be started is the same as that at time t501, the description is omitted.

  Next, at time t506, the task TA0 is activated again. Here, since the value of the excess set trial count 120 is “90” and larger than “0”, the management process 106 calculates the set trial time using the excess set trial count 120 (“90”). . The set trial time can be calculated as [10 [μs] × 90 = 0.9 [ms]]. Then, the arithmetic processing time table 121 in FIG. 2 is referred to, and the arithmetic processing having the processing time closest to the set trial time 0.9 [ms] is searched. Thereby, the calculation process d110 whose processing time is 1.0 [ms] is selected. Therefore, the execution order is changed so that the selected calculation process d110 is executed before the calculation process b108. That is, the task TA0 was executed in the order of the arithmetic processing a107 → the arithmetic processing b108 → the arithmetic processing c109 → the arithmetic processing d110 → the arithmetic processing e111 at the time t500 and t503, but after the time t506, the arithmetic processing a107 → The calculation process d110, the calculation process b108, the calculation process c109, and the calculation process e111 are executed in this order. Next, the excess set trial count 120 is reset to “0”, and the execution of the arithmetic processing a107 to arithmetic processing e111 is started in accordance with the changed execution order. While the task TA0 is being activated at time t506, the task TB of the core B 104 is not at the activation timing. Therefore, the arithmetic processing b108 can immediately set the lock flag 117 and write to the shared data 116. Therefore, the total processing time of task TA0 is the same as the total processing time when started at time t500.

  Next, at time t507 (= t502 + (task TB cycle tB)), the task TB of the core B 104 starts. Similar to time t502, the calculation process h114 can immediately set the lock flag 117.

  Next, at time t508 (= t6 + (task TA0 cycle tA)), task TA0 is activated. Since the value of the excess set trial count 120 is “0”, the management process 106 determines that it is not necessary to change the execution order, and the arithmetic process a107 to the arithmetic process e111 are performed in the execution order determined at time t506. Start execution. Thereby, the calculation process d110 is executed before the calculation process b108. Therefore, unlike the activation at time t503, the calculation process b108 starts at time t510 after the calculation process h114 clears the lock flag 117 and ends the process at time t509. The lock flag 117 can be set without repeating the above. In this way, the task TA0 can avoid exclusive control with the arithmetic processing g113 while keeping the cycle tA, and the total processing time becomes the same as the total processing time when starting at the time t500 or the time t506, The set trial time can be shortened by 0.9 ms compared to when the system is started at time t503.

  As described above, when the number of set trials of the calculation process b108 exceeds a predetermined number, the ECU 101 executes the calculation process d110 having the process time closest to the set trial time before the calculation process b108. Change the execution order. As a result, the processing time of the arithmetic processing b108 can be shortened by the set trial time compared to before the execution order is changed, and as a result, the total processing time of the task TA0 is shortened. Therefore, it is possible to reduce the processing load of the core A 103 due to exclusive control, to execute the processing time of the background task having an abnormality detection function such as an error check of the memory 105 for a long time, and to detect early when an abnormality exists. It becomes like this.

  Further, according to the first embodiment, if only the calculation process of the core A 103 accesses the shared data 116, the calculation process is not executed in the core B 104. However, the execution order can be appropriately changed, and the set trial time can be suppressed and the processing time related to the exclusive control can be shortened while achieving the exclusive control.

  In the first embodiment, it is assumed that the processing time of the arithmetic processing a107 to the arithmetic processing e111 excluding the arithmetic processing b108 is described in advance in the arithmetic processing time table 121, but it is measured and recorded during execution. It may be a thing.

  In the first embodiment, all the arithmetic processes a107 to e111 except for the arithmetic process b108 included in the task TA0 of the core A103 can be changed to change the execution order. However, the execution order is changed. The arithmetic processing that should not be performed may be excluded from the change target.

  In the first embodiment, the set trial count threshold value is set to “50”. However, when “0” is set and duplication of exclusive control occurs, the execution order may always be changed. .

Embodiment 2. FIG.
Next, an electronic control unit according to Embodiment 2 of the present invention will be described. FIG. 6 is a configuration diagram of an electronic control device according to Embodiment 2 of the present invention, and shows an ECU as an electronic control device mounted on an automobile. In FIG. 6, the same reference numerals are given to the same or corresponding parts as in FIG. The ECU 101 holds an arithmetic processing execution order table 604 and an arithmetic processing execution FIFO 605 in the memory 105. In addition to the memory 105, a nonvolatile memory 603 is provided.

  Arithmetic processing a <b> 107 to arithmetic processing e <b> 111 store their IDs (a to e) in the arithmetic processing execution FIFO 605 every time they are executed, in addition to calculations related to automobile control. The arithmetic processing f112 has a control flow monitoring function in addition to read access to the shared data 116, a CAN message transmission trigger, and refers to the arithmetic processing execution order table 604 and the arithmetic processing execution FIFO 605 with reference to the arithmetic processing a107 to arithmetic processing. It is monitored whether e111 is executed in the correct execution order. The arithmetic processing f112 refers to the arithmetic processing execution FIFO 605 for each execution, checks whether or not the stored value is equal to the arithmetic processing execution order table 604, and determines that it is abnormal if not equal.

  The arithmetic processing execution order table 604 is a table that describes the execution order (index) of the arithmetic processing a107 to arithmetic processing e111. FIG. 7 is an explanatory diagram showing an arithmetic processing execution order table before changing the execution order in the electronic control apparatus according to Embodiment 2 of the present invention. The arithmetic processing execution order table 604 in the initial setting (default) is shown in FIG. The contents are shown. The calculation process b108 as the first calculation process that executes the exclusive control is always set as a reference (“0”), the calculation process a107 is “−1 or less” before the calculation process b108, and the calculation process c109 is the calculation process b108. “1” for the next execution, “2” for the operation d110 after the operation b108, and “3 or more” for the operation e111 after the operation b108. .

  The arithmetic processing execution FIFO 605 is a buffer that stores its own ID (a to e) every time the arithmetic processing a107 to arithmetic processing e111 are executed. Since they are stored in the execution order of the arithmetic processing a107 to the arithmetic processing e111, when they are correctly executed in the default execution order, the values are calculated in the order of the arithmetic processing a107 → the arithmetic processing b108 → the arithmetic processing c109 → the arithmetic processing d110 → the arithmetic processing e111. Stored.

  The non-volatile memory 603 is a memory 105 that can retain a value even if the power is lost due to a reset or the like.

  Execution of the management processing 106 and the arithmetic processing a107 to arithmetic processing i115 by the core A103 as the first processor and the core B104 as the second processor is the same as that in the first embodiment, and therefore will be omitted.

  Exclusive control executed when the arithmetic processing b108 as the first arithmetic processing, the arithmetic processing f112 as the second arithmetic processing, and the arithmetic processing h114 as the third arithmetic processing access the shared data 116 as the shared resource. Is omitted because it is the same as in the first embodiment.

Next, the management process 106 when the task TA0 is activated in the core A103 will be described with reference to the flowchart of FIG. FIG. 8 is a flowchart relating to the start timing of task TA0 of management process 106 executed by core A103 in the electronic control apparatus according to Embodiment 2 of the present invention. In FIG. 8, the same processes as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted. When the value of the excess set trial count 120 is larger than “0”, the management process 106 uses the excess set trial count 120 to calculate the index of the arithmetic processing to be replaced (step S801). In the second embodiment, the index of the arithmetic processing to be replaced is calculated using the following equation (1). The division result is rounded down.

(Operation processing index to be replaced)
= (Number of set trials at the time of excess 120) / 50 + 1 Equation (1)

  Subsequently, with reference to the arithmetic processing execution order table 604, it is confirmed whether there is an arithmetic processing having the calculated index (step S802). If it exists, the execution order of the arithmetic process having the calculated index and the arithmetic process b108 for performing exclusive control to access the shared data 116 are switched (step S803). Then, the index of the calculation process execution order table 604 is updated so as to follow the exchanged execution order based on the calculation process b108 (step S804). On the other hand, when there is no calculation process having the calculated index, the execution order is not changed.

  Next, the management processing 106 that operates according to the flowchart of FIG. 8, the execution operation of the arithmetic processing, the lock flag 117 at that time, the set trial counter 118, and the excess set trial count 120 are shown in the time chart of FIG. It explains using. FIG. 9 is a time chart regarding arithmetic processing a to arithmetic processing i, a lock flag, a set trial counter, and an excess set trial count in the electronic control apparatus according to Embodiment 2 of the present invention. Note that the processing time of the management process 106 is not described on this time chart.

  In FIG. 9, the operation from time t500 to time t505 is the same as that of the first embodiment except for the arithmetic processing f112 at time t501. The arithmetic processing f112 refers to the arithmetic processing execution order table 604 and the arithmetic processing execution FIFO 605 in addition to reading the shared data 116 accompanied by the exclusive control and transmitting the CAN message, so that the arithmetic processing a107 to e111 are executed in the correct execution order. Monitor whether it is running. Here, since the execution order of the arithmetic processing a107 to the arithmetic processing e111 of the task TA0 started at time t500 is equal to the arithmetic processing execution order table 604, it is determined that the arithmetic processing f112 is normal.

  At time t900 (= t503 + (period tA of task TA0)), task TA0 is activated again. Here, since the value of the excess set trial count 120 is “90” and larger than “0”, the management process 106 uses the excess set trial count 120 (“90”) and the above-described equation (1). Then, the index of the arithmetic processing to be replaced is calculated. The index can be calculated as “2”. Then, with reference to the arithmetic processing execution order table 604 of FIG. 7, it is confirmed whether there is an arithmetic processing having index 2. Therefore, since the calculation process d110 has the index “2”, the execution order of the calculation process b108 and the calculation process d110 is switched, and the index of the calculation process execution order table 604 is updated as shown in FIG. That is, FIG. 10 is an explanatory diagram showing an arithmetic processing execution order table after the execution order is changed in the electronic control apparatus according to Embodiment 2 of the present invention. The task TA0 is executed in the order of the arithmetic processing a107 → the arithmetic processing d110 → the arithmetic processing c109 → the arithmetic processing b108 → the arithmetic processing e111 after the time t900. Next, the excess set trial count 120 is reset to “0”, and the execution of the arithmetic processing a107 to arithmetic processing e111 is started according to the changed execution order. While the task TA0 is being activated at time t900, the task TB of the core B 104 is not at the activation timing, so the arithmetic processing b108 can immediately set the lock flag 117 and write it to the shared data 116. Therefore, the total processing time of task TA0 is the same as the total processing time when started at time t500.

  Next, at time t901, the task TA1 of the core A103 is activated. As in the case of the time t501, the arithmetic processing f112 refers to the arithmetic processing execution order table 604 and the arithmetic processing execution FIFO 605 and monitors whether the arithmetic processing a107 to the arithmetic processing e111 are executed in the correct execution order. Although the execution order of the arithmetic processing a107 to arithmetic processing e111 of the task TA0 started at time t900 has been changed from time t500 and t503, the arithmetic processing execution order table 604 also changes simultaneously with the execution order change at time t900. Because of the update, the execution order of the arithmetic processing a107 to arithmetic processing e111 is equal to the execution order indicated by the arithmetic processing execution order table 604. Thereby, it can be determined that the arithmetic processing f112 is normal.

  Next, at time t902 (= t502 + (task TB cycle tB)), the task TB of the core B 104 starts. As in the case of time t502, the calculation process h114 can immediately set the lock flag 117.

  Next, at time t903 (= t900 + (task TA0 cycle tA)), task TA0 is activated. Since the value of the excess set trial count 120 is “0”, the management process 106 determines that it is not necessary to change the execution order, and the calculation process a107 to the calculation process e111 are performed in the execution order determined at time t900. Start execution. Therefore, unlike the activation at time t503, the calculation process b108 starts at time t905 after the calculation process h114 clears the lock flag 117 and ends the process at time t904. The lock flag 117 can be set without repeating setting attempts. In this way, the task TA0 can avoid exclusive control with the arithmetic processing g113 while keeping the cycle tA, and the total processing time is the same as the total processing time when starting at the time t500 or the time t900. , It can be shortened by the set trial time compared to when it is started at time t503.

  Next, it is assumed that at time t906, the background task detects a memory 105 error and the memory 105 needs to be reset. Therefore, the management processing 106 writes the arithmetic processing execution order table 604 updated at t900 into the nonvolatile memory 603. The management process 106 refers to the non-volatile memory 603 when resuming the process, and copies it to the calculation process execution order table 604, so that the calculation process is performed according to the execution order changed at t900 from the start of the first task TA0 after the restart. a107 to arithmetic processing e111 can be executed.

  As described above, when the set trial count of the calculation process b108 exceeds a predetermined number, the ECU 101 replaces the calculation process d110 having an index corresponding to the excess count with the execution order of the calculation process b108. As a result, as in the first embodiment, the processing time of the arithmetic processing b108 can be shortened by the set trial time compared to before the execution order is changed. Therefore, it is possible to reduce the processing load of the core A 103 due to exclusive control, to execute the processing time of the background task having an abnormality detection function such as an error check of the memory 105 for a long time, and to detect early when an abnormality exists. It becomes like this.

  Further, according to the second embodiment, the execution order can be changed even if the processing time of the arithmetic processing to be replaced is not clear, and the development man-hour such as measurement of the processing time of the arithmetic processing is reduced. can do.

  Furthermore, in the second embodiment, the ECU 101 includes the nonvolatile memory 603, and the execution order of the arithmetic processing is written in the nonvolatile memory 603, so that the memory 105 that is volatilized by resetting the memory 105 or power loss is cleared. , The calculation process can be executed in accordance with the execution order of the calculation process after the change, and it is not necessary to perform the process of detecting the duplication of the execution timing of the exclusive control process and changing the execution order at each reset. Total processing time can be reduced.

  Furthermore, the ECU 101 includes an arithmetic processing execution FIFO 605, and compares the arithmetic processing execution order table 604 with each other to determine whether the arithmetic processing execution order is correct. By using the arithmetic processing execution order table 604, even if the execution order of arithmetic processing is changed due to duplication of the exclusive control execution timing, the arithmetic processing execution order table 604 is also updated to indicate the changed execution order. The execution order of the arithmetic processing can always be monitored.

  In the second embodiment, the calculation process execution order table 604 is set so that the calculation process with the duplicated execution timing of the exclusive control is always changed to the execution order of the subsequent calculation process according to the equation (1). It was. However, the present invention is not limited to this expression, and a more complicated conditional expression that can change the execution order of the previous arithmetic processing may be used.

Embodiment 3 FIG.
Next, an electronic control unit according to Embodiment 3 of the present invention will be described. FIG. 11 is a configuration diagram of an electronic control device according to Embodiment 3 of the present invention, and shows an ECU as an electronic control device mounted on an automobile. In FIG. 11, the same reference numerals are given to the same and corresponding parts as in FIG. The ECU 101 holds an arithmetic processing execution order storage table 1101 and a change request flag 1102 in the memory 105.

  The arithmetic processing execution order storage table 1101 stores the arithmetic processing execution order (maximum) when the excess set trial count 120 is the minimum value when the execution order of the arithmetic processing a107 to arithmetic processing e111 is repeatedly changed. This is a table for storing a minimum execution order) and a minimum excess set trial count 120. In the initial setting before the execution of the arithmetic processing, nothing is described as shown in FIG. That is, FIG. 12 is an explanatory diagram showing an arithmetic processing execution order storage table before the execution order is changed in the electronic control apparatus according to Embodiment 3 of the present invention.

  The change request flag 1102 is a flag that is set by the management process 106 of the core A 103 in order to request a change in the execution order of the calculation process of the task TB. The management process 106 of the core B 104 refers to this flag when the task TB is activated.

  Since the execution method of the management process 106 and the calculation process a107 to the calculation process i115 by the core A103 and the core B104 is the same as that of the first embodiment, the description is omitted.

  The exclusive control executed when the arithmetic process b108, the arithmetic process f112, and the arithmetic process h114 access the shared data 116 is the same as that in the first embodiment, and therefore will be omitted.

  Next, the management processing 106 when the task TA0 is activated in the core A 103 will be described with reference to the flowchart of FIG. FIG. 13 is a flowchart at the start timing of the task TA0 of the management process executed by the core A in the electronic control apparatus according to Embodiment 3 of the present invention. In FIG. 13, the same processes as those in FIG. 8 are denoted by the same reference numerals, and description thereof is omitted. In FIG. 13, when the value of the excess set trial count 120 is greater than “0”, the management process 106 sets the minimum excess set trial count 120 in the arithmetic processing execution order storage table 1101 and the current excess set trial. Compared with the number of times 120 (step S1301), if the current overtime set trial count 120 is smaller, the current arithmetic processing execution order and the current overtime set trial count 120 are stored in the arithmetic processing execution order storage table 1101. Store (step S1303).

  If the current excess set trial count 120 is not smaller than the minimum excess set trial count 120 in the arithmetic processing execution order storage table 1101, the value is set to the minimum excess set trial count 120 in the arithmetic processing execution order storage table 1101. Is described (step S1302), and a value is written in the minimum excess set trial count 120 in the arithmetic processing execution order storage table 1101, that is, the current excess set trial count 120 is larger. Determines that it is not necessary to change the execution order of the arithmetic processing, and only resets the excess set trial count 120 (step S405). When a value is not described in the minimum excess set trial count 120 in the arithmetic processing execution order storage table 1101, the arithmetic processing execution order storage table 1101 is the same as when the current excess set trial count 120 is smaller. The current calculation processing execution order and the current excess set trial count 120 are stored (step S1303).

  Subsequently, after the calculation of the index (step S801), if there is no calculation process having the calculated index, the execution order cannot be changed. Therefore, the management process 106 sets the change request flag 1102 and tries to set the excess time. Reset 120 times is executed (step S405).

  Next, the management process 106 when the task TB is activated in the core B 104 will be described with reference to the flowchart of FIG. FIG. 14 is a flowchart at the start timing of the task TB of the management process executed by the core B in the electronic control apparatus according to Embodiment 3 of the present invention. In FIG. 14, the management process 106 checks whether or not the change request flag 1102 is set (step S1401). If the change request flag 1102 is set, the calculation process h114 as a third calculation process for performing exclusive control, The execution order of the arithmetic process g113 as the fourth arithmetic process executed before is changed (step S1402), the change request flag 1102 is cleared (step S1403), and the arithmetic processes g113 to i115 are executed according to the changed execution order. The management process 106 is ended. On the other hand, if the change request flag 1102 is not set, it is not necessary to change the execution order, so the execution of the arithmetic processes g113 to i115 is started according to the initially set execution order, and the management process 106 is terminated. Arithmetic processing i115 corresponds to arithmetic processing g113 and the fourth arithmetic processing in the present invention.

  Next, the management processing 106 that operates according to the flowcharts of FIGS. 13 and 14, the execution operation of the arithmetic processing, the lock flag 117 at that time, the set trial counter 118, the excess set trial count 120, and the change request flag 1102 Will be described with reference to the time chart of FIG. FIG. 15 is a time chart of arithmetic processing a to arithmetic processing i, lock flag, set trial counter, excess set trial count, and change request flag in the electronic control apparatus according to Embodiment 3 of the present invention. Note that the processing time of the management process 106 is not described on this time chart.

  In FIG. 15, the operation from time t500 to time t504 is the same as that in the first embodiment, and is therefore omitted.

  At time t1500, when the arithmetic processing h114 finishes writing to the shared data 116 and clears the lock flag 117, the arithmetic processing b108 that has repeated the setting attempt can set the lock flag 117. At this time, it is assumed that the set trial counter 118 points to “280”. After the write access to the shared data 116 and the lock flag 117 being cleared, the value of the set trial counter 118 (“280”) is larger than the set trial count threshold 119 (“50”). The value of the set trial counter 118 (“280”) is stored in 120 and the set trial counter 118 is reset. When the calculation process b108 ends, the calculation processes c109 to e111 are executed.

  Next, at time t1501 (= t503 + (task TA0 cycle tA)), task TA0 is started again. Here, since the value of the excess set trial count 120 is “280” and larger than “0”, the management process 106 determines that the minimum excess set trial count 120 and the current value in the arithmetic processing execution order storage table 1101 of FIG. Compare the number of set trials 120 when exceeded. At this time, since the minimum excess set trial count 120 is not described, as shown in FIG. 16, the current calculation processing execution order (a → b → c → d → e) and the current excess set trial The number of times 120 (“280”) is stored and updated. That is, FIG. 16 is an explanatory diagram showing an arithmetic processing execution order storage table after the first execution order change in the electronic control apparatus according to Embodiment 3 of the present invention.

  Next, using the excess set trial count 120 (“280”) and the above-described equation (1), the index of the arithmetic processing to be replaced is calculated. The index can be calculated as “6”. Then, with reference to the calculation processing execution order table 604 of FIG. Therefore, since the calculation process e111 has an index “3 or more”, the execution order of the calculation process b108 and the calculation process e111 is switched, and the index of the calculation process execution order table 604 is updated as shown in FIG. That is, FIG. 17 is an explanatory diagram showing an arithmetic processing execution order table after the first execution order change in the electronic control apparatus according to Embodiment 3 of the present invention.

  The task TA0 is executed in the order of the arithmetic processing a107 → the arithmetic processing e111 → the arithmetic processing c109 → the arithmetic processing d110 → the arithmetic processing b108 after the time t1501. Next, the excess set trial count 120 is reset to “0”, and the execution of the arithmetic processing a107 to arithmetic processing e111 is started according to the changed execution order. While the task TA0 is being activated at time t1501, the task TB of the core B 104 is not at the activation timing, so that the arithmetic processing b108 can immediately set the lock flag 117 and write to the shared data 116. Therefore, the total processing time of task TA0 is the same as the total processing time when started at time t500.

  Furthermore, at time t1502, which is the next cycle, task TA0 is activated. Since the value of the excess set trial count 120 is “0”, the management process 106 determines that it is not necessary to change the execution order, and executes the arithmetic processes a107 to e111 in the execution order determined at time t1501. To start. However, since the processing of the arithmetic processing b108 is started before the arithmetic processing h114 ends, the arithmetic processing b108 repeats the set trial, and the value of the set trial counter 118 is set again at the set trial count threshold 119 (“50” at time t1503. )) Is exceeded. Nevertheless, the calculation process b108 repeats the set trial until the lock flag 117 is cleared.

  Next, at time t1504, when the arithmetic processing h114 finishes writing to the shared data 116, the arithmetic processing b108 can set the lock flag 117. At this time, it is assumed that the set trial counter 118 points to “100”. Then, after writing access to the shared data 116 and clearing the lock flag 117, the value of the set trial counter 118 (“100”) is still larger than the set trial count threshold value 119 (“50”). The value (“100”) of the set trial counter 118 is stored in the trial count 120, and the set trial counter 118 is reset.

  Next, at time t1505, the task TA0 is activated. Since the value of the excess set trial count 120 is “100” and larger than “0”, the management process 106 has a minimum excess set trial count 120 of the arithmetic processing execution order storage table 1101 of FIG. Compare the number of hour set trials 120. At this time, the minimum overrun set trial count 120 is “280”, and the current overrun set trial count 120 of “100” is smaller. Therefore, as shown in FIG. a → e → c → d → b) and the current excess set trial count 120 (“100”) is stored and updated. That is, FIG. 18 is an explanatory diagram showing an arithmetic processing execution order storage table after the second execution order change in the electronic control apparatus according to Embodiment 3 of the present invention.

  Next, using the excess set trial count 120 (“100”) and the above-described equation (1), the index of the arithmetic processing to be replaced is calculated. The index is calculated as “3”. Then, with reference to the arithmetic processing execution order table 604 of FIG. 17, it is confirmed whether there is an arithmetic processing having the index “3”. However, since there is no calculation process having the index “3”, the management process 106 sets the change request flag 1102, resets the excess set trial count 120 to “0”, and executes the calculation process of the task TA 0. The execution of the arithmetic processing is started without changing the order. While the task TA0 is being activated at time t1505, the task TB of the core B 104 is not at the activation timing. Therefore, the arithmetic processing b108 proceeds from step S302 to step S303 and can set the lock flag 117. Therefore, the total processing time of task TA0 is the same as the total processing time when started at time t0.

  Next, at time t1506, the task TB of the core B 104 is activated. Since the change request flag 1102 is set, the management process 106 includes an operation process h114 as a third operation process for performing exclusive control and an operation process g113 as a fourth operation process executed before that. Change the execution order. That is, in the task TB, after time t1506, the calculation process h114, the calculation process g113, and the calculation process i115 are executed in this order. Then, the change request flag 1102 is cleared, the execution of the arithmetic processes g113 to i115 is started according to the changed execution order, and the management process 106 is ended.

  Next, at time t1507, the task TA0 is activated. The execution order of the arithmetic processing a107 to the arithmetic processing e111 of the task TA0 is the same as when the time t1502 is started, but the arithmetic processing h114 is changed by changing the execution order of the arithmetic processing g113 to the arithmetic processing i115 of the task TB at the time t1506. Since the processing of the arithmetic processing b108 is started after the completion, the arithmetic processing b108 can set the lock flag 117 without repeating the setting trial.

  As described above, the ECU 101 includes the arithmetic processing execution order storage table 1101 that stores the execution order when the excess set trial count 120 is the smallest value among the execution orders that have been changed so far. When the number of set trials always exceeds the predetermined number and the execution order can no longer be changed, the execution order held in the arithmetic processing execution order storage table 1101 is changed to the subsequent arithmetic processing execution order. And In this way, even if a plurality of execution order patterns are executed, even if the number of set trials exceeds a predetermined time, the number of set trials among those execution order patterns is It is possible to select an optimal execution order that is the minimum, reduce the overlap control processing time, reduce the processing load on the core A 103, and increase the processing time of the background task.

  Further, in the case where the overlapping time of the exclusive control processing of the core A 103 exceeds a predetermined time, the ECU 101 changes the execution timing of the arithmetic processing h 114 executed by the core B 104 that accesses the same shared data 116. Thereby, compared with the case where only the execution order of the arithmetic processing a107 to the arithmetic processing e111 of the core A103 is optimized, the set trial time can be further reduced, and an abnormality detection function such as an error check of the memory 105 is provided. The background task processing time can be extended.

Embodiment 4 FIG.
Next, an electronic control unit according to Embodiment 4 of the present invention will be described. FIG. 19 is a configuration diagram of an electronic control device according to Embodiment 4 of the present invention, and shows an ECU as an electronic control device mounted on an automobile.

  In FIG. 19, the same reference numerals are given to the same and corresponding parts as in FIG. 11, and description of those parts is omitted. The ECU 101 stores a frequency change flag 1901, an operation processing execution order initial setting table 1902, a core B state variable 1903, and a set trial count upper limit value 1904 in the memory 105.

  The arithmetic processing f112 as the second arithmetic processing includes a read access to the shared data 116, a CAN message transmission trigger, and a function of changing the operating frequency of the core A103 according to the arithmetic result. When it is determined that the processing load is low, the power consumption is suppressed by lowering the operating frequency of the core A103. Conversely, when the processing load is determined to be high, the operating frequency of the core A103 is increased. It is possible to prevent the processing load from exceeding the processing capacity of the core A103.

  The frequency change flag 1901 is a flag that is set when the arithmetic processing f112 changes the operating frequency.

  The arithmetic processing execution order initial setting table 1902 is a table that stores the default execution order of the arithmetic processing a107 to arithmetic processing e111. That is, FIG. 20 is an explanatory view showing the arithmetic processing execution order initial setting table 1902 in the electronic control apparatus according to Embodiment 4 of the present invention. As shown in FIG. 20, in the fourth embodiment, the execution order of the initial settings of the calculation process a107 → the calculation process b108 → the calculation process c109 → the calculation process d110 → the calculation process e111 is described.

  The core B state variable 1903 is a variable indicating the state of the core B 104. The core B state variable 1903 indicates one of four states of startup (0), normal (1), shutdown (2), and error (3). The state of the core B 104 is changed by executing the arithmetic processing g113 to the arithmetic processing i115 of the core B 104, and the core B state variable 1903 is changed.

  The set trial count upper limit 1904 is a value used for comparison with the set trial counter 118 for each set trial. When this value is exceeded, the management processing 106 of the core A 103 determines that an error has occurred in the core A 103.

  The execution method of the management process 106 and the arithmetic processes a107 to i115 by the core A103 and the core B104 is the same as that of the first embodiment except for the length of the period tB. In the fourth embodiment, it is assumed that the period tB has the same length as the period tA.

  Next, the exclusive control executed when the arithmetic process b108 accesses the shared data 116 will be described. FIG. 21 is a flowchart of the exclusive control process by the calculation process b in the electronic control apparatus according to Embodiment 4 of the present invention. In FIG. 21, the same reference numerals are given to the same and corresponding parts as in FIG. 3, and description of those parts is omitted. Since the lock flag 117 is not cleared, the management process 106 increments the set trial counter 118 (step S307), and then compares the value of the set trial counter 118 with the set trial count upper limit 1904 (“100”). (Step S2101) When the value of the set trial counter 118 is less than or equal to the set trial number upper limit value 1904, the process returns to reading the value of the lock flag 117 (Step S301). If the value of the set trial counter 118 exceeds the set trial count upper limit value 1904, it is determined that there is an abnormality and abnormal processing is started.

  Further, after the lock flag 117 is cleared (step S305), if the value of the set trial counter 118 exceeds the set trial count threshold value 119, is the core B state variable 1903 first indicating normal (1)? Confirmation (step S2102). If the core B state variable 1903 is normal (1), the set trial counter 118 is reset (step S309) after storing in the excess set trial count 120 (step S308), and the series of processing ends. On the other hand, when the core B state variable 1903 indicates a value other than normal (1), the set trial counter number 118 is not updated, the set trial counter 118 is reset (step S309), and a series of processes is performed. Exit.

  The exclusive control executed when the arithmetic processing f112 as the second arithmetic processing and the arithmetic processing h114 as the third arithmetic processing access the shared data 116 is the same as that in the first embodiment, and thus will be omitted.

  Next, the management process 106 when the task TA0 is activated in the core A103 will be described. FIG. 22 is a flowchart at the start timing of the task TA0 of the management process executed by the core A in the electronic control apparatus according to Embodiment 4 of the present invention. In FIG. 22, the same processes as those in FIG. The management process 106 first checks whether the frequency change flag 1901 is set (step S2201). If not set, reference to the value of the excess set trial count 120 is started (step S401), and the subsequent processing is the same as in the third embodiment. On the other hand, when the frequency change flag 1901 is set, the execution order of the operation processes a107 to e111 is set as the default execution order with reference to the operation process execution order initial setting table 1902. Further, the arithmetic processing execution order storage table 1101 is cleared (not described) (step S2202). Then, the set frequency change flag 1901 is cleared (step S2203), the execution of the arithmetic processing a107 to the arithmetic processing e111 is started according to the determined execution order, and the management processing 106 is ended.

  Next, when executing the operation frequency change, the management processing 106, the execution operation of the arithmetic processing, and the lock flag 117, the set trial counter 118, the set trial count threshold 119, the excess set trial count 120, the frequency change The flag 1901 and the core B state variable 1903 will be described using a time chart. FIG. 23 shows arithmetic processing a to arithmetic processing i when operating frequency is changed, lock flag, set trial counter, excess set trial count, frequency change flag, core B in the electronic control device according to Embodiment 4 of the present invention. It is a time chart of a state variable. Note that the processing time of the management process 106 is not described on this time chart.

  In FIG. 23, when the task TA0 of the core A 103 is activated for the first time at time t2300, the frequency change flag 1901 is not set and the excess set trial count 120 is “0”. The arithmetic processing a107 to the arithmetic processing e111 included in the task TA0 are executed in the order of the arithmetic processing a107 → the arithmetic processing b108 → the arithmetic processing c109 → the arithmetic processing d110 → the arithmetic processing e111. The operation of the arithmetic processing at this time is the same as that at time t500 in the first embodiment.

  At time t2301, the task TA1 of the core A103 is activated for the first time, and the arithmetic processing f112 included in the task TA1 is executed. At this time, the arithmetic processing f112 is measuring the processing load of the core A103, and the operating frequency is not yet changed. Other operations of the arithmetic processing f112 are the same as those at the time t501 in the first embodiment.

  Since the operation at the next time t2302 is the same as that at time t502 in the first embodiment, the description thereof is omitted.

  Subsequently, while the arithmetic processing h114 is being executed in the core B104, the time t2303 (= t2300 + (the period tA of the task TA0)) is reached, and the task TA0 is activated again in the core A103. Again, since the frequency change flag 1901 is not set and the excess set trial count 120 is “0”, the management process 106 does not change the execution order. However, since the lock flag 117 remains set by the calculation process h114 of the core B 104 even when the start time of the calculation process b108 for writing access to the shared data 116 is reached, the calculation process b108 immediately sets the lock flag 117. Repeated set trial. Each time the setting of the lock flag 117 fails, the set trial counter 118 is incremented, and the value of the set trial counter 118 exceeds the set trial count threshold value 119 (“50”) at time t2304. Nevertheless, the calculation process b108 repeats the set trial until the lock flag 117 is cleared, but the value of the set trial counter 118 does not exceed the set trial count upper limit value 1904 (“100”), and thus is not determined to be abnormal.

  Next, at time t2305, when the arithmetic processing h114 finishes writing to the shared data 116 and clears the lock flag 117, the arithmetic processing b108 that has repeatedly set attempts can set the lock flag 117. At this time, it is assumed that the set trial counter 118 points to “90”. Then, after writing access to the shared data 116 and clearing the lock flag 117, it is determined that the value of the set trial counter 118 (“90”) is larger than the set trial count threshold value 119 (“50”). At this time, referring to the core B state variable 1903 indicates normal (1), so the value of the set trial counter 118 (“90”) is stored in the excess set trial count 120 and the set trial counter 118 is reset. To do. When the calculation process b108 ends, the calculation processes c109 to e111 are executed.

  The content of execution of the next calculation process f112 is the same as that at time t2301, and is therefore omitted.

  Next, at time t2306 (= t2303 + (period tA of task TA0)), task TA0 starts again. Again, since the frequency change flag 1901 is not set, the management processing 106 has the value of the excess set trial count 120 being “90”, which is larger than “0”. The minimum excess set trial count 120 of 1101 is compared with the current excess set trial count 120. At this time, since the minimum excess set trial count 120 is not described, as shown in FIG. 16, the current calculation processing execution order (a → b → c → d → e) and the current excess set trial The number of times 120 (“90”) is stored and updated.

  Next, the index of the arithmetic processing to be replaced is calculated using the excess set trial count 120 (“90”) and the above-described equation (1). The index can be calculated as “2”. Then, with reference to the arithmetic processing execution order table 604 of FIG. 7, it is confirmed whether there is an arithmetic processing having the index “2”. Here, since the calculation process d110 is index “2”, the execution order of the calculation process b108 and the calculation process d110 is switched, and the index of the execution order table is updated as shown in FIG. That is, the task TA0 is executed in the order of the calculation process a107 → the calculation process d110 → the calculation process c109 → the calculation process b108 → the calculation process e111 after the time t2306. Next, the excess set trial count 120 is reset to “0”, and the execution of the arithmetic processing a107 to arithmetic processing e111 is started according to the changed execution order. While the task TA0 is being activated at time t2306, the task TB of the core B 104 is not at the activation timing, and therefore the arithmetic processing b108 can immediately set the lock flag 117. Therefore, the total processing time of task TA0 is the same as the total processing time when activated at time t2300.

  Next, at time t2307, the task TA1 of the core A103 is activated, and the arithmetic processing f112 included in the task TA1 is executed. At this time, the calculation process f112 determines that the operating frequency can be lowered from the measured processing load calculation result of the core A103, sets the operating frequency of the core A103 to 1/2, and sets the frequency change flag 1901. As a result, the processing time of the arithmetic processing a107 to arithmetic processing f112 is doubled. However, in order not to change the processing frequency and the CAN message transmission cycle, the length of the cycle tA is set to be the same as that before the change of the operating frequency.

  Next, at time t2308 (= t2306 + (period TA of task TA0)), task TA0 is activated. Since the frequency change flag 1901 is set, the management process 106 refers to the calculation process execution order initial setting table 1902 and sets the execution order changed at the time t2306 as the default execution order from the calculation process a107 to the calculation process b108. → Calculation process c109 → Calculation process d110 → Return to calculation process e111. Also, the arithmetic processing execution order storage table 1101 is cleared and returned to an undescribed state. Then, the frequency change flag 1901 is cleared, and the execution of the arithmetic processing a107 to arithmetic processing e111 is started according to the default execution order. As a result, the execution order becomes the same as the time t2303 when the set trial counter 118 exceeds the set trial count threshold value 119, but since the operating frequency has been changed, the arithmetic process b108 is started after the arithmetic process h114 ends. Therefore, the set trial is not repeated.

  As described above, when the operating frequency is changed, the ECU 101 returns the execution order of the arithmetic processing a107 to the arithmetic processing e111 to the default setting. As a result, the execution order set by the designer as an initial setting is used, so that the arithmetic processing can be performed in the execution order in which the intention of the designer is most reflected. Further, if the setting is not returned to the default setting, even if the set trial counter 118 exceeds the set trial count threshold value 119 after the operating frequency is changed, it cannot be determined whether the exclusive control is duplicated due to the change in the execution order. If 1) is left as it is, it is not suitable for use, and there is a high possibility that there is no arithmetic processing having the calculated index. On the other hand, by returning to the default setting as the operating frequency is changed, the options for changing the execution order can be increased, and the possibility that the duplication control processing overlap time can be shortened can be increased.

  In the fourth embodiment, only the execution order of the arithmetic processing a107 to arithmetic processing e111 executed in the core A103 is returned to the default. However, as shown in the third embodiment, the arithmetic processing executed in the core B104 is performed. When the execution order of the processing g113 to the arithmetic processing i115 is changed, the execution order of the arithmetic processing of the core B104 may be set to the default together with the change of the operating frequency. Furthermore, in the case of the ECU 101 that changes the operating frequency of the core B104, the execution order of the arithmetic processing executed by the core A103 or the core B104 may be set back to the default in accordance with the change of the operating frequency of the core B104. Good. By doing in this way, compared with the case where only the execution order in core A103 is returned to a default setting, the possibility that the duplication control processing duplication time can be shortened can be further increased.

  Next, when the state of the core B 104 changes, the management processing 106, the execution operation of the arithmetic processing, the lock flag 117, the set trial counter 118, the set trial count threshold 119, the excess set trial count 120, the frequency The change flag 1901 and the core B state variable 1903 will be described using a time chart. FIG. 24 shows arithmetic processing a to arithmetic processing i when the state of core B changes in the electronic control device according to Embodiment 4 of the present invention, lock flag, set trial counter, excess set trial count, frequency change flag, It is a time chart of a core B state variable. Note that the processing time of the management process 106 is not described on this time chart.

  Until time t2400, since the duplication control processing overlap time (repetition of set trials) has not occurred, the execution order remains the default.

  It is assumed that at time t2400, the task TB of the core B104 is activated and some abnormality occurs in the core B104 during the execution of the arithmetic processing h114. The arithmetic processing h114 sets the core B state variable 1903 to error (3), but continues the error state until the reset is applied while the lock flag 117 is set. Thereby, the calculation process b108 started to be executed at time t2401 repeats the set trial. However, since the value of the set trial counter 118 does not exceed the upper limit value 1904 (“100”) of the set trials, it is not determined to be abnormal.

  At time t2402, only the core B104 is reset and the lock flag 117 is cleared. As a result, the calculation process b108 can set the lock flag 117. At this time, it is assumed that the set trial counter 118 points to “90”. After the write access to the shared data 116 and the lock flag 117 being cleared, the value of the set trial counter 118 (“90”) is larger than the set trial count threshold value 119 (“50”). Refer to At this time, since the core B state variable 1903 indicates an error (1), the value of the excess set trial count 120 is not updated and remains zero. Then, the set trial counter 118 is reset to zero. When the calculation process b108 ends, the calculation processes c109 to e111 are executed.

  When the task TA0 is started again at time t2403, the frequency change flag 1901 is not set, and the excess set trial count 120 is 0. Therefore, the management process 106 performs the operation without changing the execution order. Execution of processing a107 to arithmetic processing e111 is started.

  When the task TA0 is started again at time t2404, the frequency change flag 1901 is not set, and the excess set trial count 120 is “0”, so the management process 106 does not change the execution order. Then, the execution of the arithmetic processing a107 to arithmetic processing e111 is started. At this time, the execution order of the arithmetic processing a107 to the arithmetic processing e111 has not been changed from the time t2401, but since the abnormal state of the core B104 is eliminated, the exclusive control processing does not overlap.

  Thus, since the ECU 101 changes the execution order only while it is normal, it is possible to avoid unnecessary change in the execution order in a state where the execution timing of the exclusive control is temporarily overlapped due to an error. .

  Next, when the abnormality occurs in the core B 104, the lock flag 117 is not cleared, and the set trial counter 118 exceeds the set trial count upper limit value 1904, the management processing 106 and the execution operation of the arithmetic processing are performed using a time chart. I will explain. FIG. 25 shows arithmetic processing ai when a set trial counter exceeds the set trial count upper limit value, lock flag, set trial counter, excess set trial count, frequency in the electronic control device according to Embodiment 4 of the present invention. It is a time chart of a change flag and a core B state variable.

  The operation from time t2400 to time t2401 is the same as that in the time chart of FIG.

  In FIG. 25, at time t2500, the calculation process b108 repeats the set trial because the lock flag 117 is not cleared, and the value of the set trial counter 118 exceeds the set trial count upper limit 1904 (“100”). As a result, it is determined that the core A 103 is also abnormal, and the abnormality process is started. Abnormal processing refers to, for example, H / W reset of the core A 103, the core B 104, the memory 105, and the like.

  In this way, the ECU 101 determines that an abnormality occurs when the value of the set trial counter 118 exceeds the set trial count upper limit value 1904, and by starting the abnormality process, the lock flag 117 is not cleared. It is possible to avoid a situation (deadlock) in which execution of periodic arithmetic processing is impossible.

  It should be noted that within the scope of the present invention, the embodiments can be freely combined, or the embodiments can be appropriately modified or omitted.

The above-described electronic control device according to Embodiment 1 of the present invention embodies (1), (2), and (3) among the following inventions.
The above-described electronic control device according to Embodiment 2 of the present invention embodies (1), (3), (9), and (11) among the following inventions.
The above-described electronic control device according to Embodiment 3 of the present invention embodies (1), (3), (4), and (5) among the following inventions.
The aforementioned electronic control device according to Embodiment 4 of the present invention embodies (1), (3), (6), (7), (8), and (10) among the following inventions. It is.

(1) a first processor that executes arithmetic processing;
A second processor that executes arithmetic processing in parallel with execution of arithmetic processing of the first processor;
An electronic control device comprising:
The first processor is configured to periodically execute a first calculation process and a plurality of second calculation processes according to a predetermined execution order,
The second processor is configured to periodically execute a third arithmetic process,
The first calculation process and the third calculation process are calculation processes that exclusively access a shared resource,
A lock flag that is set when any one of the first calculation process and the third calculation process exclusively accesses the shared resource;
When the shared resource is exclusively accessed by the third calculation process and the first calculation process cannot set the lock flag, the setting calculation is attempted until the first calculation process can set the lock flag. A set trial counter for counting the number of set trials to be repeated;
With
When the value of the set trial counter exceeds a predetermined threshold value,
Based on the value of the set trial counter, select at least one of the plurality of second arithmetic processes,
By changing the execution order of the first processing and the selected second arithmetic processing, and is configured to perform the calculation processing of the first processor,
An electronic control device characterized by that.

(2) It is configured to select one of the plurality of second calculation processes based on the processing time of each of the plurality of second calculation processes.
The electronic control device according to (1) above, wherein

(3) based on the current execution order of said second arithmetic processing, and is configured to select one of said plurality of second arithmetic processing,
The electronic control device according to (1) above, wherein

(4) If the value of the set trial counter exceeds the predetermined threshold even if the execution order is changed a plurality of times, the execution order when the value of the set trial counter is the smallest value is Configured to perform arithmetic processing of the first processor;
The electronic control device according to (1) above, wherein

(5) The second processor
The third calculation process and the fourth calculation process are configured to be periodically executed,
Wherein when the value of the even running change of the execution order set attempt counter has exceeded the predetermined threshold, to change to the third arithmetic processing, the execution order of the fourth arithmetic processing Configured ,
The electronic control device according to (1) above, wherein

(6) A function of changing an operating frequency of the first processor is provided.
When the operating frequency of the first processor is changed, the changed execution order is returned to the execution order before the change,
The electronic control device according to (1) above, wherein

(7) A function of changing an operating frequency of the second processor is provided.
When the operating frequency of the second processor is changed, the changed execution order is returned to the execution order before the change,
The electronic control device according to (1) above, wherein

( 8 ) The first processor
When at least one of the plurality of second arithmetic processes cannot be selected, a change request flag is set,
The second processor is
When the change request flag is set, the execution order of the third calculation process and the fourth calculation process is changed.
The electronic control device according to (5) above, wherein

( 9 ) The electronic control device
A monitoring process for monitoring an execution order of the first calculation process and the second calculation process;
The first calculation process and the second calculation process respectively notify the monitoring process of first process information and second process information indicating that the first calculation process and the second calculation process are executed,
The monitoring process is a process of determining an abnormality when a notification order of the first process information and the second process information is different from a predetermined notification order, wherein the second calculation process and the second process information When the execution order of the arithmetic processing of 2 is changed, the predetermined notification order is changed based on the changed execution order.
The electronic control device according to (1) above, wherein

( 10 ) When the value of the set trial counter exceeds a predetermined value, it is determined to be abnormal.
The electronic control device according to (1) above, wherein
(11) The electronic control unit includes a nonvolatile storage area,
Storing the changed execution order in the non-volatile storage area;
The electronic control device according to (1) above, wherein

  101 electronic control unit (ECU), 102 CAN communication line, 103 first processor (core A), 104 second processor (core B), 105 memory, 106 management processing, 107 arithmetic processing a, 108 arithmetic processing b, 109 arithmetic processing c, 110 arithmetic processing d, 111 arithmetic processing e, 112 arithmetic processing f, 113 arithmetic processing g, 114 arithmetic processing h, 115 arithmetic processing i, 116 shared resource (shared data), 117 lock flag, 118 set trial Counter, 119 set trial count threshold, 120 exceeding set trial count, 121 computation processing time table, 122 CAN communication interface, 604 computation processing execution order table, 605 computation processing execution FIFO, 1101 computation processing execution order storage table, 1102 change request Flag, 190 1 Frequency change flag, 1902 operation processing execution order initial setting table, 1903 core B state variable, 1904 upper limit number of set trials.

Claims (11)

A first processor that executes arithmetic processing;
A second processor that executes arithmetic processing in parallel with execution of arithmetic processing of the first processor;
An electronic control device comprising:
The first processor is configured to periodically execute a first calculation process and a plurality of second calculation processes according to a predetermined execution order,
The second processor is configured to periodically execute a third arithmetic process,
The first calculation process and the third calculation process are calculation processes that exclusively access a shared resource,
A lock flag that is set when any one of the first calculation process and the third calculation process exclusively accesses the shared resource;
When the shared resource is exclusively accessed by the third calculation process and the first calculation process cannot set the lock flag, the setting calculation is attempted until the first calculation process can set the lock flag. A set trial counter for counting the number of set trials to be repeated;
With
When the value of the set trial counter exceeds a predetermined threshold value,
Based on the value of the set trial counter, select at least one of the plurality of second arithmetic processes,
The execution order of the first processor is changed to change the execution order of the selected second arithmetic process and the first arithmetic process, and the first processor is executed.
An electronic control device characterized by that. Based on the processing time of each of the plurality of second calculation processes, one of the plurality of second calculation processes is selected.
The electronic control device according to claim 1, wherein: Based on the current execution order of the second arithmetic processing, configured to select one of the plurality of second arithmetic processing,
The electronic control device according to claim 1, wherein: If the value of the set trial counter exceeds the predetermined threshold even if the execution order is changed a plurality of times, the execution order of the first processor is determined according to the execution order when the value of the set trial counter is the smallest value. Configured to perform arithmetic processing,
The electronic control device according to claim 1. The second processor is
The third calculation process and the fourth calculation process are configured to be periodically executed,
If the set trial counter value exceeds the predetermined threshold even if the execution order is changed, the execution order of the third arithmetic processing and the fourth arithmetic processing is changed. ing,
The electronic control device according to claim 1. A function of changing an operating frequency of the first processor;
When the operating frequency of the first processor is changed, the changed execution order is returned to the execution order before the change,
The electronic control device according to claim 1. A function of changing an operating frequency of the second processor;
When the operating frequency of the second processor is changed, the changed execution order is returned to the execution order before the change,
The electronic control device according to claim 1. The first processor is
When at least one of the plurality of second arithmetic processes cannot be selected, a change request flag is set,
The second processor is
When the change request flag is set, the execution order of the third calculation process and the fourth calculation process is changed.
The electronic control device according to claim 5 . The electronic control device
A monitoring process for monitoring an execution order of the first calculation process and the second calculation process;
The first calculation process and the second calculation process respectively notify the monitoring process of first process information and second process information indicating that the first calculation process and the second calculation process are executed,
The monitoring process is a process of determining an abnormality when a notification order of the first process information and the second process information is different from a predetermined notification order, wherein the second calculation process and the second process information When the execution order of the arithmetic processing of 2 is changed, the predetermined notification order is changed based on the changed execution order.
The electronic control device according to claim 1 . The electronic control device
When the value of the set trial counter exceeds a predetermined value, it is configured to determine that it is abnormal.
The electronic control device according to claim 1. The electronic control device includes a nonvolatile storage area,
It is configured to store the changed execution order in the nonvolatile storage area,
The electronic control device according to claim 1.