JP6666216B2 - Electronic control unit, analysis system - Google Patents

Description

  The present invention relates to an electronic control device and an analysis system.

In an electronic control device in which a plurality of CPUs operate in cooperation, exclusive control of access to resources shared by the plurality of CPUs is required. When a certain CPU is using the shared resource, the other CPU cannot use the shared resource until the use of the previous CPU is completed, which causes a waiting time. Since the occurrence of the waiting time lowers the processing capacity of the electronic control unit, it is desirable that the waiting time does not occur. For that purpose, it is necessary to analyze the cause of the waiting time, and it is required to record the waiting time as a log for the analysis.
Patent Document 1 discloses a method of accessing a time register and calculating a waiting time as a difference between the current time and the acquired time.

International Publication No. 2012/132017

  In the invention described in Patent Document 1, the overhead for recording the waiting time is large.

An electronic control device according to a first aspect of the present invention is an electronic control device including a plurality of CPU cores and a shared resource, wherein each of the CPU cores can exclusively use the shared resource by exclusive control. An update counter storage unit for storing a counter value, a log storage unit for storing a log of a program executed by the CPU core, and changing the counter value when the CPU core accesses the shared resource. A counter updating unit that causes the log including the counter value to be stored in the log storage unit when the shared resource is not exclusively controlled by another CPU core when the CPU core accesses the shared resource. And a counter recording unit for recording.
An analysis system according to a second aspect of the present invention includes the electronic control device according to the first aspect and an analysis device, wherein the analysis device stores the log stored in the log storage unit of the electronic control device. An input log collection unit, a storage unit that stores conversion information for converting the count value to real time, and using the conversion information, the counter value input to the log collection unit is converted to real time. And an analysis unit for conversion.

  According to the present invention, it is possible to reduce overhead for recording a waiting time.

Diagram showing the configuration of the analysis system Diagram showing an operation example of the electronic control device The figure which shows an example of a 1st buffer. The figure which shows an example of a 2nd buffer Diagram showing an example of a time conversion table Diagram showing an example of analysis results Flow chart showing the operation of the electronic control unit Flow chart showing log analysis operation FIG. 3 is a diagram illustrating a configuration of an electronic control device according to a second embodiment. 9 is a flowchart illustrating the operation of the electronic control device according to the second embodiment. FIG. 14 is a diagram illustrating an example of a first buffer according to the third embodiment. The figure which shows an example of the time conversion table in 3rd Embodiment. 10 is a flowchart illustrating the operation of the electronic control device according to the third embodiment.

(First Embodiment)
Hereinafter, a first embodiment of an electronic control unit will be described with reference to FIGS.
FIG. 1 is a diagram showing a configuration of an electronic control device 100 and an analysis system 1 according to the present invention. The analysis system 1 includes an electronic control device 100 and an analysis device 200.

  The electronic control unit 100 is, for example, an ECU (Electronic Control Unit). The electronic control unit 100 includes a first CPU 160, a second CPU 170, a shared resource 110 usable by these two CPUs, a memory 130 as a main storage device, a timer 120 having current time information, and a log output unit 180. And Hereinafter, the first CPU 160 and the second CPU 170 will be collectively referred to as “CPU”.

  The shared resource 110 is a partial area of the memory 130, a physical memory independent of the memory 130, or a hardware register of any CPU. The shared resource 110 can be accessed by the first CPU 160 and the second CPU 170, and the shared resource 110 is occupied by any one of the CPUs through exclusive control described later. The shared resource 110 includes a storage unit in which a lock variable 111 and task information 112 are stored.

  The lock variable 111 is a variable indicating the state of the exclusive control. For example, in the present embodiment that takes values of “zero” and “1”, the state of the lock variable 111 of “0” means that the shared resource 110 Is not exclusively controlled by the CPU, that is, the CPU is not exclusively used. The state in which the lock variable 111 is “1” is a state in which the shared resource 110 is exclusively controlled by any one of the CPUs, that is, a state in which the shared resource 110 is exclusively used.

  The task information 112 is a variable indicating the identifier of the latest task that has occupied the shared resource 110. In other words, when the lock variable 111 is finally set to “1”, the identifier of the task executed in the CPU occupying the shared resource 110 is stored as the task information 112. When the CPU that has executed the task cannot be identified only by the identifier of the task, information that identifies the CPU that executed the task is also included in the task information 112 as identification information. The above-described task means a process executed by the CPU, and is called a job, a process, a thread, or the like depending on the processing system.

  Each of first CPU 160 and second CPU 170 is an individual CPU, and each has a CPU core. That is, the electronic control device 100 is a device having a so-called multiprocessor configuration including a plurality of physical CPUs. The first CPU 160 operates as a first lock acquisition unit 161 and a first counter recording unit 162 by expanding a program (not shown) in the memory 130 and executing the program. The second CPU 170 operates as a second lock acquisition unit 171 and a second counter recording unit 172 by loading and executing a program (not shown) in the memory 130. The first CPU 160 and the second CPU 170 temporarily occupy and use the shared resource 110 as described below.

  When the CPUs, that is, the first CPU 160 and the second CPU 170 need to use the shared resource 110, the CPU first checks the value of the lock variable 111. If the lock variable 111 is “zero” when the CPU confirms, the CPU rewrites the lock variable 111 to “1” and uses the shared resource 110 exclusively, and when the use ends, sets the lock variable 111 to “1”. From "to zero". If the lock variable 111 is “1” when the CPU confirms, the CPU accesses the lock variable 111 at predetermined time intervals, and keeps accessing until the lock variable 111 is changed to “zero”. The time interval at which the CPU accesses the lock variable 111 is known, and a time conversion table 212 described later is created in advance based on this time interval.

  As described above, the exclusive control method that repeats the access until the shared resource 110 is successfully occupied and the lock variable 111 becomes “zero” in the above example is called “spin lock”. In the present embodiment, the number of attempts to occupy the shared resource 110 in the spin lock, that is, the number of times after the second check of the value of the lock variable 111 is referred to as “spin count”. For example, the number of spins is zero when the lock variable 111 is checked for the first time and the number of spins is zero when the lock variable 111 is checked for the first time and the number of spins is two. Further, the time from when the value of the lock variable 111 is checked for the first time to when the value “1” can be assigned to the lock variable 111 to use the shared resource 110 is referred to as “lock wait time”. Further, the exclusive control of the shared resource 110 by rewriting the lock variable 111 from “zero” to “1” is also referred to as “lock acquisition”.

  The first lock acquisition unit 161 and the second lock acquisition unit 171 perform this lock acquisition. The first lock acquisition unit 161 operates when the first CPU 160 uses the shared resource 110, and the second lock acquisition unit 171 operates when the second CPU 170 uses the shared resource 110. Confirmation of the lock variable 111 and substitution of “1” when the lock variable 111 is “zero” by the first lock acquisition unit 161 and the second lock acquisition unit 171 are performed atomically as a TEST-and-SET instruction. Be executed. That is, the confirmation of the variable and the assignment to the variable are executed without interruption from the other CPUs as a series of operations.

The first counter recording unit 162 and the second counter recording unit 172 store the value of the lock variable 111 and the like after the first lock acquisition unit 161 and the second lock acquisition unit 171 acquire the lock, respectively. To be stored. The operations of the first counter recording unit 162 and the second counter recording unit 172 will be described later in detail.
The timer 120 is hardware for managing time. The timer 120 includes a time register 121 indicating time information. The time information may be an absolute time, or may be a relative time with reference to a predetermined time such as the time when the power of the electronic control device 100 is turned on, for example, zero.

  The memory 130 is a storage device and stores programs and data executed by the CPU. The memory 130 includes an update counter storage unit 140 and a log storage unit 150 as its functions. The shared resource 110, the memory 130, and the timer 120 may each be hardware independent of the CPU on the electronic control unit 100, or may be on a single semiconductor chip such as an SoC (System-on-Chip). It may be integrated into.

  The update counter storage section 140 stores a first counter 141 and a second counter 142. The first counter 141 is a counter value updated by the first CPU 160, and indicates the number of spins of the first CPU 160. The second counter 142 is a counter value updated by the second CPU 170 and indicates the number of spins of the second CPU 170. The initial values of the first counter 141 and the second counter 142 are zero, and each is incremented by one by updating.

The log storage unit 150 includes a first buffer 151 and a second buffer 152. The log of the program executed by the first CPU 160 is stored in the first buffer 151. The log of the program executed by the second CPU 170 is stored in the second buffer 152. The log stored in the log storage unit 150 is output to the analysis device 200 via a log output unit 180 described later.
The log output unit 180 is an interface that communicates with the log collection unit 270 of the analysis device 200. The log output unit 180 is, for example, a debug interface such as JTAG, or a communication interface corresponding to CAN (CarAreaNetwork) or IEEE802.3. The log output unit 180 outputs a log to the analysis device 200 in response to a request from the analysis device 200 or at regular intervals.

(Configuration of analyzer)
The analysis device 200 is, for example, a computer including a memory 210, a log analysis unit 220, a display unit 230, a CPU 260, and a log collection unit 270. The memory 210 stores a collection buffer 211 in which logs of the CPUs of the electronic control device 100 are collected, a time conversion table 212 indicating the relationship between the number of spins and time, and an analysis result 213 output by the log analysis unit 220. You.
The log analysis unit 220 analyzes the log stored in the collection buffer 211 using the time conversion table 212. In other words, the log analysis unit 220 converts the lock waiting time recorded as the number of spins into real time. The result analyzed by the log analysis unit 220 is stored in the memory 210 as the analysis result 213 and displayed on the display unit 230.

The display unit 230 displays the log stored in the collection buffer 211 and the analysis result 213 output by the log analysis unit 220. However, the display unit 230 may be a device that outputs information to be displayed on a display device connected to the analysis device 200. The CPU 260 is an arithmetic device that operates the analysis device 200. The architecture, the number of cores, the number of sockets, the operation speed, and the like of the CPU 260 are not particularly limited.
The log collection unit 270 is an interface that communicates with the log output unit 180 of the electronic control device 100. The log collection unit 270 is, for example, a debugging interface such as JTAG, or a communication interface corresponding to CAN or IEEE802.3. The log collection unit 270 stores the log received from the electronic control device 100 in the collection buffer 211.

(Operation example)
An operation example of the first CPU 160 and the second CPU 170 will be described with reference to FIG. The time chart illustrated in FIG. 2 illustrates tasks executed by the first CPU 160 and the second CPU 170, and lock acquisition. Time elapses from left to right in the figure. The numbers at the top of FIG. 2 indicate the time obtained from the time register 121. The logs stored in the first buffer 151 and the second buffer 152, which will be described later with reference to FIGS. 3 and 4, are logs obtained by the operation shown in FIG. In the following, in order to conveniently discriminate the exclusive control of the shared resource 110 that is executed a plurality of times, that is, lock acquisition, for convenience, they are referred to as lock L, lock M, lock N,. .

  The first CPU 160 is executing the task A from the time 850 to the time 910, the interrupt R occurs at the time 880, and the interrupt R continues until the time 900. The first CPU 160 starts acquisition of the lock L at time 860, starts acquisition of the lock N at time 885, and starts acquisition of the lock O shortly before time 900. The second CPU 170 is executing the task B from the time 840 to the time 920, the interrupt Q occurs at the time 870, and the interrupt Q continues until the time 890. The second CPU 170 started acquiring the lock M at time 880, and after acquiring the lock M, uses the shared resource 110 and ends the use of the shared resource 110 after the time 885 has elapsed. Regarding the acquisition of the lock N by the first CPU 160, the number of spins at that time is 300, and the task using the shared resource 110 before that is the interrupt Q. Other lock acquisitions, that is, the number of spins of lock L, lock M, and lock O are zero. If the number of spins is zero, the lock is acquired immediately.

(Structure of buffer)
FIG. 3 and FIG. 4 are diagrams illustrating an example of information stored in the first buffer 151 and the second buffer 152. Here, the information stored in the first buffer 151 and the second buffer 152 when the operation shown in FIG. 2 is performed is shown. Since the configurations of the first buffer 151 and the second buffer 152 are the same, the first buffer 151 will be described as a representative. The first buffer 151 stores a log including one or a plurality of records. Each record of the first buffer 151 includes five fields of an event type 311, an event content 312, a time stamp 313, a waiting time 314, and task information 315. Each record of the first buffer 151 corresponds to each event of the program executed by the first CPU 160.

  The field of the event type 311 stores the type of event that has occurred, for example, “task start”, “lock acquisition”, and the like. The field of the event content 312 stores the target of the generated event, for example, “task A”, “interrupt R”, and the like. For example, if the event type is “task start” and the event content 312 is “task A”, the log indicates an event that the execution of task A has been started in the CPU.

In the field of the time stamp 313, information on the time when the event occurs is stored. The time information is obtained from the time register 121 of the timer 120. In the field of the waiting time 314, information indicating the lock waiting time obtained from the first counter 141, that is, the number of spins is stored. In the field of the task information 315, the value of the task information 112 when the lock acquisition is successful when the spin count is 1 or more is stored. Hereinafter, a value stored in a certain field may be referred to by a field name. For example, "the value stored in the field of the event type 311 is xx" may be described as "event type 311 is xx".
Some fields of each record are recorded under specific conditions or are not recorded under specific conditions.

  The field of the time stamp 313 is not recorded under the following conditions. That is, when the event type 311 is “lock acquisition” and the waiting time 314 is zero (0), no value is recorded in the field of the time stamp 313. In other cases, that is, when the first CPU 160 can acquire the lock in the second and subsequent accesses, a value is recorded in the field of the time stamp 313. If the waiting time for lock acquisition is zero, it is not necessary to record the time, and the overhead required for recording the time is large. In the examples shown in FIG. 3 and FIG. 4, the time stamp 313 is not recorded in the event of the lock L, M, O where the waiting time 314 is zero.

  The field of the waiting time 314 is recorded when the event type 311 is “lock acquisition”. That is, when the event type 311 is other than “lock acquisition”, no value is recorded in the field of the waiting time 314. As described above, since the number of spins is stored in the field of the waiting time 314, recording is not possible in an event other than "lock acquisition" in which spin cannot occur. In the example shown in FIGS. 3 and 4, the task information 315 is recorded only for the event of the lock N whose waiting time 314 is not zero.

In the field of the task information 315, a value is recorded when the event type 311 is "lock acquisition" and the waiting time 314 is other than zero, that is, when the first CPU 160 can acquire the lock by the second or subsequent access. . In other cases, no value is recorded in the field of the task information 315. If the waiting time for lock acquisition is zero, it is not necessary to identify the task that has used the shared resource 110 immediately before.
In FIGS. 2 and 3, the first buffer 151 and the second buffer are described as simple tables, but may have a structure such as a ring buffer. A long record may be used.

(Time conversion table)
FIG. 5 is a diagram illustrating an example of the time conversion table 212. The time conversion table 212 is a correspondence table between the number of spins stored in the field of the waiting time in the first buffer 151 and the second buffer 152 and the real time, and includes fields of the waiting time 321 and the real time 322. The field of the waiting time 321 stores the waiting time, that is, the number of spins, and the field of the real time 322 stores the value of the real time corresponding to the value of the waiting time (number of spins) stored in the waiting time 321. You. In FIG. 5, if the waiting time is zero, the real time is also zero, if the waiting time is “1”, the real time is “5 microseconds”, and if the waiting time is “1 + n”, the real time is real time. Is "5 + 4 * n microseconds".

For example, the following can be understood by using the time conversion table 212 for the lock N shown in FIGS. For lock N, the value of the waiting time stored in the waiting time 314 in FIG. 3 is 300, that is, 1 + 299, so the actual time required to acquire lock N is 5 + 4 * 299 = 11201 microseconds. Furthermore, since acquisition of lock N was started at time 885, it can be seen that lock N was acquired when 1201 microseconds had elapsed from time 885.
The information stored in the time conversion table 212 may be information other than the table format shown in FIG. That is, any type of information may be stored in the time conversion table 212 as long as the information appropriately represents the relationship between the number of spins and real time.

(Analysis result)
FIG. 6 is a diagram illustrating an example of the analysis result 213 output by the log analysis unit 220 of the analysis device 200. The analysis result 213 is information obtained by analyzing the log stored in the collection buffer 211, and details the lock acquisition event in which the waiting time has occurred. Each of the records constituting the analysis result 213 corresponds to a lock acquisition event. The analysis result 213 includes seven fields of a processing CPU 331, a generation processing 332, a lock 333, a time stamp 334, an actual waiting time 335, a cause CPU 336, and a cause processing 337.

  The field of the processing CPU 331 stores the identifier or name of the CPU in which the lock acquisition event has occurred. The field of the occurrence process 332 stores the name of the task or interrupt process that caused the lock acquisition event. The field of the lock 333 stores the name of the lock set for convenience. In the field of the time stamp 334, information on the time when the lock acquisition event occurs is stored. In the field of the actual waiting time 335, the waiting time until the lock obtained by using the time conversion table 212 is stored. The field of the cause CPU 336 stores the identifier or name of the CPU that caused the wait in lock acquisition. The field of the cause process 337 stores the identifier of the task that caused the wait in lock acquisition. The CPU and the task that caused the wait are the CPU holding the lock and the task being executed by the CPU when the lock acquisition was attempted in the event. The CPU and the task that caused the wait are specified from the task information 112.

  The first record in FIG. 6 will be specifically described. This record is generated based on the log of the fourth record in FIG. In order for the first CPU 160 to acquire the lock N at the time 185, a wait of the number of spins 300 occurred. Therefore, in the analysis result 213, “first CPU” is stored in the processing CPU 331, “interrupt R” is generated in the generation processing 332, “lock N” is stored in the lock 333, and “185” is stored in the time stamp 334. Further, since 300 spins correspond to 1201 microseconds according to the time conversion table 212, "1201 microseconds" is stored in the field of the actual waiting time 335. The task that used the shared resource 110 immediately before was interrupt Q, and since the task was executed by the second CPU 170, “second CPU” is stored in the field of the cause CPU 336 and “interrupt Q” is stored in the field of the cause process 337. Is done.

(Overview of operation of analysis system 1)
An outline of the operation of the analysis system 1 will be described. The operation of the analysis system 1 is roughly divided into log collection and analysis. The collection of logs is executed by the electronic control unit 100, and the analysis of logs is executed by the analysis unit 200.
The first CPU 160 and the second CPU 170 of the electronic control unit 100 operate software by executing programs (not shown). These software require the use of shared resources 110. The first CPU 160 and the second CPU 170 store a log of a software event in the log storage unit 150. The stored logs include the start and end of task execution, the start and end of interrupt processing, and the lock acquisition processing for using the shared resource 110. In the present embodiment, since the log of the lock acquisition processing is focused on, the description of the other log recording processing is omitted.

  The first CPU 160 acquires a lock using the first lock acquisition unit 161 and records a log related to the acquired lock in the first buffer 151 using the first counter recording unit 162. The second CPU 170 acquires a lock using the second lock acquisition unit 171 and records a log related to the acquired lock in the second buffer 152 using the second counter recording unit 172. The log output unit 180 outputs the log stored in the log storage unit 150 to the analysis device 200.

The CPU 260 of the analysis device 200 causes the log analysis unit 220 to analyze the log output from the electronic control device 100. The result analyzed by the log analysis unit 220 is stored in the memory 210 as the analysis result 213 and displayed on the display unit 230.
Hereinafter, an operation of acquiring a lock and an operation of storing a log related to the lock in the first CPU 160 will be described with reference to FIG. 7, and an operation of the log analysis unit 220 will be described with reference to FIG. The operation of the second CPU 170 for acquiring the lock and the operation of storing the log related to the lock are the same as the operations of the first CPU 160, and thus description thereof will be omitted.

(Flowchart for lock acquisition and recording)
A lock acquisition operation and a log recording operation related to lock acquisition by the first CPU 160 will be described with reference to FIG. The subject of execution of each step described below is the first CPU 160.
In step S400, the counter value of the first counter 141 is reset to zero. In the following step S401, in order to use the shared resource 110, an attempt is made to acquire a lock using the TEST-and-SET instruction described above. In subsequent step S402, it is determined whether or not the lock acquisition in step S401 is successful. If it is determined that the lock acquisition is successful, the process proceeds to step S406, and if it is determined that the lock acquisition is failed, the process proceeds to step S403.

In step S403, the counter value of the first counter 141 is incremented, that is, increased by one. In a succeeding step S404, it is determined whether or not the counter value of the first counter 141 is "1". If it is determined that the counter value is “1”, that is, if a negative determination is made for the first time in step S402 after execution of step S400, the process proceeds to step S405. When it is determined that the counter value is other than “1”, that is, when the negative determination is made in step S402 after the execution of step S400 for the second time or later, the process returns to step S401. In step S405, a time stamp is obtained from the time register 121, and the process returns to step S401.
In step S406 executed when the lock is successfully acquired, it is determined whether or not the counter value of the first counter 141 is zero. If it is determined to be zero, the process proceeds to step S407, and if it is determined to be other than zero, the process proceeds to step S408.

In step S407, the following information is recorded in the first counter recording unit 162 with the first buffer 151 as a recording target. That is, the type of the event currently being executed in the first CPU 160, that is, “lock acquisition”, the content of the event, and the counter value of the first counter 141 are recorded. In step S408, the following information is recorded in the first counter recording unit 162 with the first buffer 151 as a recording target. That is, the type of the event currently being executed in the first CPU 160, the content of the event, the counter value of the first counter 141, the time stamp acquired in step S405, and the task information 112 are recorded.
In step S409, which is executed when the execution of step S407 or step S408 is completed, information of the task currently being executed in the first CPU 160 is stored in the task information 112, and the flowchart shown in FIG. 7 ends.

(Flowchart of log analysis)
FIG. 8 is a flowchart illustrating the operation of the log analysis unit 220 that analyzes the log collected in the collection buffer 211 and outputs the analysis result 213. The execution subject of each step described below is the CPU 260 of the analyzer 200.
In step S501, one of the CPUs whose logs are stored in the collection buffer 211 is selected as a processing target, and the process proceeds to step S502. As described later, the processing between step S501 and step S509, that is, the processing from step S502 to step S508 is executed for all CPUs whose logs are stored in the collection buffer 211.

In step S502, one of the logs of the CPU selected as the processing target is selected as the processing target, and the process proceeds to step S503. As described later, the processing between step S502 and step S508, that is, the processing from step S503 to step S507 is executed for all logs of the CPU to be processed.
In step S503, it is determined whether or not the event type 311 of the log to be processed is “lock acquisition”. If it is determined that the event type 311 is “lock acquisition”, the process proceeds to step S504. Goes to step S508.

In step S504, it is determined whether or not the waiting time of the log to be processed is “1” or more. If it is determined that it is “1” or more, the process proceeds to step S505. If so, the process proceeds to step S508.
In step S505, the CPU executing the task is specified based on the value of the field of the task information 315 of the log to be processed. In the following step S506, the value of the field of the waiting time 314 of the log to be processed is converted into real time using the time conversion table 212, and the process proceeds to step S507.

  In step S507, the information of the log to be processed is recorded in the analysis result 213. At this time, the values recorded in each field of the analysis result 213 are as follows. The processing CPU 331 is the name of the CPU currently being processed in the loop of steps S502 to S508. The value of the occurrence process 332 is the value of the event content 312 in the log immediately before the log to be processed. The value of the lock 333 is the value of the event content 312 in the log to be processed. The value of the time stamp 334 is the value of the time stamp 331 in the log to be processed. The value of the actual waiting time 335 is the actual time calculated in step S506. The value of the cause CPU 336 is the name of the CPU identified in step S505. The value of the cause process 337 is the value of the task information 315 in the log to be processed.

In a succeeding step S508, it is determined whether or not all logs of the CPU to be processed have been processed. If it is determined that there is an unprocessed log, the process returns to step S503 with one of the unprocessed logs as a processing target. If it is determined that all logs have been processed, the process proceeds to step S509.
In step S509, it is determined whether all CPUs whose logs are stored in the collection buffer 211 have been processed. If it is determined that there is an unprocessed CPU, the process returns to step S502 with one of the unprocessed CPUs as a processing target. If it is determined that all the CPUs have been processed, the flowchart of FIG. 8 ends.

According to the first embodiment, the following operation and effect can be obtained.
(1) The electronic control unit 100 includes a plurality of CPUs, that is, a first CPU 160 and a second CPU 170, and a shared resource 110. Each of the CPUs can exclusively use the shared resource 110 by exclusive control. Each of the CPUs includes an update counter storage unit 140 for storing a counter value, and a log storage unit 150 for storing a log of a program executed by the first CPU 160 and the second CPU 170, including a count value for which counting has been completed. When the CPU accesses the shared resource 110, the CPU updates the counter value stored in the update counter storage unit 140, that is, the first lock acquisition unit 161 and the second lock acquisition unit 171; When the shared resource 110 is not exclusively controlled by another CPU when the shared resource 110 is accessed, a counter record for recording a log including the counter value stored in the update counter storage unit 140 in the log storage unit 150 , Ie, a first counter recording unit 162 and a second counter recording unit 172.

  When the CPU accesses the shared resource 110 and the shared resource 110 is exclusively controlled by another CPU, that is, when the lock variable 111 is “1”, the electronic control device 100 updates the counter value. . Therefore, the occurrence of the access can be recorded as an update of the counter value in the update counter storage unit 140 without causing overhead due to the access to the timer 120. Note that the counter value stored in the update counter storage unit 140 represents the number of times the lock acquisition has been attempted after the second time, that is, the number of spins.

  When the shared resource 110 is not exclusively controlled by another CPU, that is, when the lock variable 111 is zero, the electronic control unit 100 does not access the timer 120 having a large overhead and updates the update counter storage unit. The count value stored in 140 is stored in log storage unit 150. Therefore, the overhead for recording the log is small. This advantage is particularly noticeable when the waiting time is zero. For example, in the calculation of the waiting time, a method of obtaining the time from the timer at the start and end of the waiting time and calculating the difference between the two times as the waiting time is widely performed. Access is performed twice. The time required to acquire the time is longer than the time required to acquire the lock, and the acquisition of the time is performed twice, which causes a problem that the overhead of calculating the waiting time increases. However, according to the present invention, the waiting time can be recorded without causing such a problem.

(2) Each time the CPU accesses the shared resource 110 and executes a predetermined processing unit, that is, every time the spin lock is executed, the CPU of the electronic control unit 100 checks the counter stored in the update counter storage unit 140. Change the value.
Therefore, by recording the number of times of execution of the spin lock whose execution interval and execution time are known, it is possible to record the waiting time without accessing a timer having a large overhead.

(3) The electronic control unit 100 includes a timer 120 that holds time information. When the CPU accesses the shared resource 110 for the first time, if the shared resource 110 is exclusively controlled by another CPU, time information is acquired from the timer 120 and a log further including the time information is stored in the log storage unit 150. To be stored.
Therefore, the time at which the waiting time occurs can be recorded while concealing the overhead of accessing the timer 120. Updating the counter means that the shared resource 110 is being used by another CPU, and the CPU that has attempted to acquire the lock attempts to acquire the lock again after a predetermined time has elapsed. Therefore, even if the CPU that has tried to acquire the lock accesses the timer 120, at least a part of the overhead is hidden. This effect is remarkable when at least one of the first CPU 160 and the second CPU 170 has the following features. That is, the effect is remarkable when the CPU has a feature of issuing an instruction to stop the CPU for a certain period of time in order to prevent bus occupation during spinning.

(4) The shared resource 110 includes an identification information storage unit for storing identification information for identifying a process executed by the CPU, that is, an area for storing task information 112. The counter recording unit, that is, the first counter recording unit 162 and the second counter recording unit 172 store the identification information, that is, the task information 112 from the identification information storage unit when the CPU exclusively controls the shared resource 110 in the second and subsequent accesses. And stores a log further including the task information 112 in the log storage unit 150.
Therefore, the identification information of the process that caused the waiting time, that is, the process that previously used the shared resource 110 can be recorded in the log storage unit 150.

(5) When the exclusive update control of the shared resource 110 is performed, the counter update unit, that is, the first lock acquisition unit 161 and the second lock acquisition unit 171 update the identification information of the identification information storage unit based on the processing executed by the CPU. Update.
Since information on tasks using the shared resource 110 is stored in the task information 112, when a certain CPU cannot use the shared resource 110, the processing that caused the problem, that is, using the shared resource 110 before It is possible to specify the processing that was being performed.

(6) The analysis system 1 includes an electronic control device 100 and an analysis device 200. The analysis device 200 stores a log collection unit 270 to which information stored in the log storage unit 150 of the electronic control device 100 is input, and conversion information for converting a counter value into real time, for example, a time conversion table 212. It includes a storage unit, that is, a memory 210, and a log analysis unit 220 that converts the counter value input to the log collection unit 270 into real time using the conversion information.
Therefore, the analysis device 200 can convert the counter value recorded by the electronic control device 100 into real time. That is, the analysis system 1 converts the recorded spin count into real time using the analysis device 200 while recording the waiting time due to the exclusive control of the shared resource 110 as the spin count to reduce the recording overhead. Can be.

(Modification 1)
The time acquired from the timer 120 may be stored in the waiting time 314 of the first buffer 151 and the second buffer 152. That is, in step S408 of FIG. 7, a time stamp may be obtained from the time register 121 and stored. In this case, the analysis device 200 calculates the actual time spent waiting for lock acquisition by calculating the difference between the time stored in the time stamp 313 and the time stored in the waiting time 314.
According to the first modification, the analysis device 200 has a first advantage that there is no need to include the time conversion table 212 and a second advantage that it is possible to perform more accurate waiting time calculation. Except when the waiting time becomes zero, even if the time is acquired by accessing the time register 121, the influence of the overhead is relatively small and the disadvantage is small.

(Modification 2)
The first counter 141 may be stored in a register of the first CPU 160 or a memory (not shown) included in the first CPU 160. Similarly, the second counter 142 may be stored in a register of the second CPU 170 or a memory (not shown) included in the second CPU 170.
According to the second modification, rewriting is performed in the same CPU that can be accessed at high speed, so that overhead for initializing and updating the counter value can be reduced.

(Modification 3)
The first counter 141 may not be provided independently, and the first buffer 151 may also serve as the first counter 141. In this case, instead of initializing and updating the counter value stored in the first counter 141, the first lock acquiring unit 161 writes zero, which is the initial value of the counter, in the field of the waiting time 314 of the first buffer 151. ,Update. Similarly, the second counter 142 is not provided independently, and the second buffer 152 may also serve as the second counter 142.

(Modification 4)
The electronic control unit 100 may include three or more CPUs. Further, the electronic control unit 100 may include one CPU that is housed in a single package and has a plurality of cores. The multiple cores contained in a single package may be the same or different. Further, the architecture and operation speed of each CPU core may be the same or different.

(Modification 5)
The memory 130 may be independent for each CPU. In this case, the log storage unit 150 and the update counter storage unit 140 exist in the memory 130 for each CPU. Further, the configuration may be divided into a nonvolatile memory for holding a program and a volatile memory for holding data.

(Modification 6)
The electronic control unit 100 includes a third CPU, and the third CPU includes at least one of a first lock acquisition unit 161, a first counter recording unit 162, a second lock acquisition unit 171, and a second counter recording unit 172. May be executed. Further, at least one of the first lock acquisition unit 161, the first counter recording unit 162, the second lock acquisition unit 171, and the second counter recording unit 172 may be executed by a hardware circuit.

(Other modifications)
The above-described first embodiment may be further modified as follows.
(1) The electronic control unit 100 may include a plurality of timers, and refer to a different timer for each CPU. In this case, a correction process is performed, such as recording the difference between the values of the time registers 121 used by the respective CPUs.
(2) The first counter recording unit 162 and the second counter recording unit 172 need not record the task information 112 in step S408 of FIG. In this case, the first lock acquisition unit 161 and the second lock acquisition unit 171 do not need to update the task information 112 in step S409 of FIG. 7, and the first buffer 151 and the second buffer 152 store the task information 315 Field need not be provided.

(3) The first lock acquisition unit 161 and the second lock acquisition unit 171 need not acquire the time stamp regardless of the counter value. That is, after executing step S403 in FIG. 7, the process may return to step S401 without evaluating the counter value.
(4) The electronic control unit 100 may include a plurality of shared resources 110. In this case, each shared resource 110 independently includes a lock variable 111 and task information 112.

(Second embodiment)
A second embodiment of the electronic control unit will be described with reference to FIGS. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and the differences will be mainly described. The points that are not particularly described are the same as in the first embodiment. The present embodiment differs from the first embodiment mainly in that the electronic control device includes a diagnostic unit that converts the count value into real time.

  FIG. 9 is a diagram illustrating a configuration of an electronic control device 100A according to the second embodiment. In the electronic control unit 100A, the log output unit 180 is deleted from the configuration of the electronic control unit 100 in the first embodiment, and a diagnostic unit 900 is added. Further, the memory 130 further stores a time conversion table 212 and an analysis result 213. The configuration and operation that are not particularly described are the same as those of the first embodiment.

  The diagnosis unit 900 represents, as a functional block, a function realized by one of the first CPU 160 and the second CPU 170 executing a program stored in a ROM (not shown). The diagnosis unit 900 analyzes the log stored in the log storage unit 150. When detecting an abnormality by the analysis, for example, when the waiting time is longer than a predetermined time, the diagnosis unit 900 executes a predetermined abnormality processing. The diagnosing unit 900 operates when a predetermined time has elapsed or when a predetermined event that requires diagnosis has occurred.

(Flowchart of diagnosis unit)
FIG. 10 is a flowchart illustrating the operation of the diagnosis unit 900 according to the second embodiment. Hereinafter, differences from the flowchart illustrating the operation of the log analysis unit 220 illustrated in FIG. 8 will be described. The execution subject of each step described below is one of the first CPU 160 and the second CPU 170. Hereinafter, this execution subject is referred to as “CPU”.
Since the processing up to step S507 is the same as that of the log analysis unit 220, the description is omitted. When the execution of step S507 is completed, step S521 is executed.

In step S521, it is determined whether the actual time converted in step S506 is equal to or greater than a predetermined value. When it is determined that the value is equal to or more than the predetermined value, the process proceeds to step S522, and when it is determined that the value is less than the predetermined value, the process proceeds to step S508.
In step S522, a predetermined abnormal time process is executed, and the process proceeds to step S508. The abnormal-time process is, for example, a transition to the execution state of the minimum configuration, or a restart of the electronic control device 100 when the number of times of detecting the abnormality reaches a predetermined threshold.

According to the above-described second embodiment, the following operation and effect can be obtained.
(1) The electronic control unit 100A converts the counter value into real time using the conversion information for converting the count value into time, for example, a storage unit storing the time conversion table 212, that is, the memory 130, and the time conversion table 212. An analysis unit for conversion, that is, a diagnosis unit 900 is provided.
Therefore, the electronic control device 100A can convert the counter value into real time without using the analysis device 200. Thus, the diagnosis using the converted real time can be executed as shown in step S521 in FIG.

(Modification of Second Embodiment)
The second embodiment may be modified as follows.
(1) The diagnosis unit 900 may use a time other than the calculated waiting time for diagnosis. For example, when the task that caused the waiting is not a predetermined task, it may be determined that some abnormality in the execution order has occurred, and this may be diagnosed as an abnormality.
(2) The diagnosis unit 900 need not record the analysis result in the memory 130.
(3) The electronic control unit 100A may further include a log output unit 180.

(Third embodiment)
A third embodiment of the electronic control unit will be described with reference to FIGS. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and the differences will be mainly described. The points that are not particularly described are the same as in the first embodiment. This embodiment is different from the first embodiment mainly in that the number of executions of the basic block is counted instead of the number of spins.

(Basic block)
A basic block is a unit of execution of a program and does not include a branch or a merge in the unit. Since the basic block does not include a branch or a merge, the execution time of the basic block is constant if the execution environment, that is, the CPU and the memory are the same. The present embodiment will be described using three basic blocks (A, B, C). The execution time of each basic block in the electronic control unit 100 is known.

(Constitution)
The hardware configuration of the analysis system 1 is the same as that of the first embodiment. However, each of the first counter 141 and the second counter 142 has three counters (A, B, C) corresponding to the basic blocks A, B, C, respectively. The information stored as the time conversion table 212 is different from that of the first embodiment. Further, a program stored in a ROM (not shown) of the electronic control device 100 is different from that of the first embodiment, and the operations of the first lock acquisition unit 161 and the second lock acquisition unit 171 are different from those of the first embodiment.

  FIG. 11 is a diagram illustrating an example of the structure of the first buffer 151 according to the present embodiment. The configuration of the fields constituting the first buffer 151 is the same as that of the first embodiment, and the value stored in the field of the waiting time 314 is different. That is, in the field of the waiting time 314, the values of the counters A, B, and C stored in the first counter 141 are stored. Other points are the same as in the first embodiment. In the example shown in FIG. 11, the basic block A is executed three times, the basic block B is executed once, and the basic block C is executed twice when the lock M is acquired. The configuration of the second buffer 152 and the information stored in the second buffer 152 are the same as those of the first buffer 151.

FIG. 12 is a diagram illustrating an example of the time conversion table 212A. The time corresponding to each basic block is recorded in the time conversion table 212A. Specifically, the time conversion table 212A includes a field of a basic block number 323 and a field of a time 324. The field of the basic block number 323 stores the identifier of the basic block or the name of the basic block. The time 324 field stores the time required for one execution of the basic block.
According to the examples shown in FIGS. 11 and 12, the waiting time for acquiring the lock M is calculated as 3 * 20 + 1 * 38 + 2 * 19 = 136 microseconds from the execution time of each basic block.

(Operation of lock acquisition unit)
The lock acquisition unit, that is, the first lock acquisition unit 161 and the second lock acquisition unit 171 acquire the lock using the TEST-and-SET instruction in the first embodiment, but in the third embodiment, , A LoadLinked instruction (hereinafter, referred to as “LL instruction”), and a Store Conditional instruction (hereinafter, referred to as “SC instruction”).

  The LL instruction is an instruction that loads a specified memory area and, at the same time, generates a “link” for that area. This “link” disappears when another CPU writes in the same area. The SC instruction is an instruction that stores a value only when a “link” remains in a specified memory area. Confirmation of the remaining "link" in the SC instruction means the following. That is, the remaining “link” indicates that no other CPU has written in the same area between the LL instruction and the SC instruction. That is, this guarantees the atomicity of reading and writing, that is, guaranteeing that reading and writing have succeeded as an integral part.

(flowchart)
FIG. 13 is a flowchart illustrating a lock acquisition operation and a log recording operation related to lock acquisition by the first CPU 160 according to the third embodiment. As shown in FIG. 13, step S451 is the basic block A, step S454 is the basic block B, and step S455 is the basic block C. When each basic block is executed, the counter corresponding to each basic block is updated. The flowchart shown in FIG. 13 corresponds to FIG. 7 in the first embodiment. Hereinafter, differences from FIG. 7 will be mainly described.

In step S400A, the counters A to C of the first counter 141 are reset to zero, and the process proceeds to step S451. In step S451, the lock variable 111 is read using the LL instruction, and the flow advances to step S452. In step S452, the counter A is incremented, that is, the counter value is increased by 1, and the process proceeds to step S453.
In step S453, it is determined whether or not the lock variable 111 read in step S451 is zero. The CPU proceeds to step S455 when determining that it is zero, and proceeds to step S454 when determining that it is not zero.

  In step S454, the link generated in step S451 is discarded. In a succeeding step S403A, the counter B is incremented and the process proceeds to a step S404A. In step S404A, it is determined whether the sum of the counter values of the counters B and C is "1". When it is determined that the counter value is “1”, the process proceeds to step S405, and when it is determined that the counter value is other than “1”, the process returns to step S451. In step S405, a time stamp is obtained from the time register 121, and the process returns to step S451.

In step S455, "1" is written to the lock variable 111 using the SC instruction. In a succeeding step S456, the counter C is incremented. In a succeeding step S457, it is determined whether or not the writing in the step S455 is successful. When it is determined that the writing is successful, the process proceeds to step S406A, and when it is determined that the writing is failed, the process proceeds to step S404A. In the step S406A, it is determined whether or not the counter value of the counter B is zero. If it is determined to be zero, the process proceeds to step S407, and if it is determined to be other than zero, the process proceeds to step S408.
The processing after step S407 is the same as in the first embodiment, and a description thereof will be omitted.

According to the above-described third embodiment, the following operation and effect can be obtained.
(1) When the counter update unit, that is, the first lock acquisition unit 161 and the second lock acquisition unit 171 access the shared resource 110, each time a predetermined processing unit is executed, that is, each basic block is executed. Each time the value of the counter stored in the update counter storage unit 140 and corresponding to each basic block is updated.
Therefore, by recording the number of executions of the basic block whose execution interval and execution time are known, it is possible to record the waiting time without accessing a timer having a large overhead.

(2) The counter updating unit, that is, the first lock acquiring unit 161 and the second lock acquiring unit 171 change the counter value of the counter B or the counter C when the shared resource 110 is exclusively controlled by another CPU. . Therefore, it is possible to record the number of times that the shared resource 110 was accessed but the exclusive control could not be performed.
Unlike the first embodiment, in the third embodiment, when the shared resource 110 is exclusively controlled by another CPU, it is determined in step S453 that it is zero, and in step S457 described later. There are two cases in which it is determined that writing has failed. By using the sum of the counter values of the counter B and the counter C, it is possible to record the number of times the exclusive control could not be performed.
In addition, in step S404A, it is determined whether or not the sum of the counter values of the counters B and C is “1”, and in any case, the time is obtained in the first case where the exclusive control could not be performed. As in the first embodiment, it is possible to obtain the effect of recording the time when the waiting time occurs while hiding the overhead.

(Modification)
In the third embodiment, the number of executions of the basic block is counted. However, the number of times of processing with a finer granularity may be counted, or the number of times of processing with a coarser granularity may be counted. For example, a configuration is conceivable in which counting is performed for each instruction of the CPU as counting at a fine granularity. In this case, the log storage unit 150 stores the execution time of each instruction of the CPU. In the case of counting for each instruction, it is desirable to count using a hardware circuit such as a CPU because realizing this by software has a very high overhead. According to the method of counting for each instruction by hardware, it is not necessary to change software so as to count the number of executions for each basic block, and an effect of relatively reducing overhead can be obtained.

  Also in the first embodiment, the increment processing of the counter stored in the update counter storage unit 140 does not need to be performed by software. For example, a counter may be implemented as one or a plurality of registers of the CPU, and when the CPU executes a specific instruction, the corresponding counter may be added. In this case, for example, the waiting time 314 recorded in the log storage unit 150 in steps S407 and S408 in FIG. 7 is the value of the counter read from the hardware. In this case, in addition to the operation and effect of the first embodiment, an effect of further reducing overhead can be obtained.

Although the program is stored in the ROM (not shown), the program may be stored in the memory 130. Further, the electronic control device 100 may include an input / output interface (not shown), and a program may be read from another device via a medium that can be used by the electronic control device 100 when necessary. Here, the medium refers to, for example, a storage medium detachable from an input / output interface, or a communication medium, that is, a network such as a wired, wireless, or optical network, or a carrier or a digital signal that propagates through the network. In addition, some or all of the functions realized by the program may be realized by a hardware circuit or an FPGA.
The above-described embodiments and modifications may be combined with each other.
Although various embodiments and modified examples have been described above, the present invention is not limited to these contents. Other embodiments that can be considered within the scope of the technical idea of the present invention are also included in the scope of the present invention.

1 analysis system 100, 100A electronic control unit 110 shared resource 111 lock variable 112 task information 120 timer 140 update counter storage unit 150 log storage unit 160 first CPU
161, a first lock acquisition unit 162, a first counter recording unit 170, a second CPU
171, a second lock acquisition unit 172, a second counter recording unit 200, an analyzer 211, collection buffers 212, 212A, a time conversion table 220, a log analysis unit 230, a display unit 900, and a diagnosis unit.

Claims (8)

An electronic control device including a plurality of CPU cores and a shared resource,
Each of the CPU cores can exclusively use the shared resources by exclusive control and can be used,
An update counter storage unit in which a counter value is stored;
A log storage unit for storing a log of a program executed by the CPU core;
A counter updating unit that changes the counter value when the CPU core accesses the shared resource;
When the CPU core accesses the shared resource, if the shared resource is not exclusively controlled by another CPU core, a counter recording unit that records the log including the counter value in the log storage unit. An electronic control device further comprising: The electronic control device according to claim 1,
The electronic control unit, wherein the counter update unit changes the counter value when the CPU core accesses the shared resource and the shared resource is exclusively controlled by another CPU. The electronic control device according to claim 1,
The electronic control unit, wherein the counter updating unit changes the counter value each time the CPU core accesses the shared resource and executes a predetermined processing unit. The electronic control device according to claim 1,
A timer for holding time information;
The counter recording unit acquires time information from the timer when the CPU core accesses the shared resource for the first time, and when the shared resource is exclusively controlled by another CPU core, An electronic control unit that stores the log further including information in the log storage unit. The electronic control device according to claim 1,
The shared resource includes an identification information storage unit that stores identification information for identifying a process executed by the CPU core,
The counter recording unit acquires the identification information from the identification information storage unit when the CPU core exclusively controls the shared resource in a second or subsequent access, and stores the log further including the identification information in the log. Electronic control device to be stored in the storage unit. The electronic control device according to claim 5, wherein
The electronic control unit, wherein the counter updating unit updates the identification information of the identification information storage unit based on a process executed by the CPU core when the CPU core controls the shared resource exclusively. The electronic control device according to any one of claims 1 to 6, wherein
A storage unit that stores conversion information for converting the counter value into time,
An electronic control unit comprising: an analysis unit configured to convert the counter value into real time using the conversion information. An analysis system comprising the electronic control device according to any one of claims 1 to 6, and an analysis device,
The analysis device,
A log collection unit to which the log stored in the log storage unit of the electronic control device is input;
A storage unit that stores conversion information for converting the counter value into real time,
An analysis unit configured to convert the counter value input to the log collection unit into real time using the conversion information.

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