JP4998303B2 - Memory shared data processing system, memory access amount measuring apparatus, and memory access amount measuring method - Google Patents

Description

  The present invention relates to a technique for measuring a memory access amount in a system in which a plurality of processing devices share a memory.

  Conventionally, a system including a plurality of processing devices and a memory has a configuration in which a plurality of processing devices serve as a bus master and share a bus. For example, in a multi-core processor, a processor core is provided as a plurality of processing devices, and the processor core shares a bus as a bus master. Further, in a system having a plurality of units each including a CPU or the like, each unit shares a bus as a bus master with each unit as a processing device.

  In such a configuration, a plurality of bus masters may access the bus at the same time, and if access exceeding the upper limit of the bus bandwidth occurs simultaneously, the hardware causes some bus masters to wait for arbitration of the bus. Therefore, the required performance may not be obtained. Therefore, in order to ensure the required performance, a proposal has been made to measure the bus bandwidth usage rate as shown in FIG. 11 and use it for program tuning or the like.

  FIG. 11 is a diagram showing a configuration for measuring the bus bandwidth usage rate of the multi-core processor 102. The configuration of the multi-core processor 102 in FIG. 11 includes a processor core 104 (core 0 to core N), a DMA 109 (Direct Memory Access Unit), and the like as processing devices (bus masters).

  Each processor core 104 has an interface with the memory unit 103. The processor core 104 includes a processing unit 105 (processing 00, processing 01, processing 02...), A local memory 106, a timer unit 107, an access measurement unit 108, and a DMA 109.

  The memory unit 103 is connected to each processor core 104 and the DMA 109 via a bus, and stores, for example, measurement results output from each access measurement unit 108. The measurement result stored in the memory unit 103 is the access amount of each processor core 104 and DMA 109.

  FIG. 12 shows a measurement flow of the bus bandwidth usage rate using the system configuration (hardware) shown in FIG. In order to measure the access amount of processing executed by each processor core 104, a code for setting and negating a flag is inserted before and after a program (software) to be processed. When a program is executed in each processor core 104 and a code for setting a flag is executed, the flag unit 110 of the access measuring unit 108 is notified of the flag setting as shown in FIG. 12, and the flag unit 110 detects the access amount. An access amount count instruction is notified to the counter unit 111.

  That is, as in the operation flow executed for each processor core 104 shown in FIG. 12, the flag is set in step S21, and the process 00 is executed in step S22. After executing the process, the flag is negated in step S23. Similar processing is executed from step S24 to obtain the access amount of each processing (the access amount (count value) measured by the access amount detection counter unit 111 is held in the count value register unit 112). In this way, each time a memory access is executed, the access amount notified from each processor core 104 is counted and held.

  With the above configuration, each core can acquire the total access amount and can acquire the total access amount. If this value rises to near the upper limit of the bus bandwidth, the user can know that the processing time of each bus master may be extended while waiting for memory access. If the required performance is not achieved, the software is modified to reduce memory access, and tuning is performed to satisfy the required performance.

In order to use a multi-core processor or the like, software development (object-oriented) using a high-level language such as C language is indispensable.
FIG. 13 shows a multiprocessor program using a high-level language and the allocation of processing to each bus master. Allocate processing to the bus master in units of functions and tasks.

  For example, in FIG. 13, a function 00, a function 01, a function 02, a function 10, a function 11, a function 20, and a function 21 constituting a program written in a high-level language are allocated to each bus master. Functions 00 to 02 are assigned to the core 0 indicating the bus master, functions 10 and 11 are assigned to the core 1, and functions 20 and 21 are assigned to the core 2.

  When performing such allocation, 1) change assignment to master, 2) change execution order, 3) variable unit, in order to improve performance degradation due to high bus bandwidth utilization during program development on multi-core processors Therefore, it is necessary to tune the program to change the memory allocation. Therefore, proposals as shown in Patent Documents 1 to 4 have been made.

However, the performance information that can be acquired by the prior art is only the cumulative amount of bus access for each process, and there is a problem that the above 1) to 3) cannot be performed. In order to perform 1) to 3), it is necessary to associate time information common to all bus masters and bus bandwidth usage for each bus master. Specifically, a) bandwidth usage information in units of functions, b) all The function unit start time and end time based on time information common to the bus master, and c) the bus bandwidth usage rate for each variable access needs to be measured.
JP 11-272499 A Japanese Patent Application Laid-Open No. 06-231087 JP 2000-348007 A JP 2006-146922 A

  The present invention has been made in view of the above situation, and by acquiring access time information together with the access amount of each process, in order to avoid performance degradation even if memory access is concentrated, An object of the present invention is to provide a memory access amount measuring device, a memory access amount measuring device, and a memory access amount measuring method for measuring a memory access amount.

  A memory shared data processing system in which a plurality of processing devices according to one aspect of the present invention share a memory, wherein the processing device uses a time notified from a timer for each process executed by the processing device. A time measurement unit that measures an access start time and an end time of the memory; and an access measurement unit that measures an access amount to the memory of the process from the start to the end of the process. .

  With the above configuration, the user can acquire access time information together with the access amount of each process, and based on this result, it is possible to take measures to avoid performance degradation even when memory accesses are concentrated.

  Preferably, the processing device holds a measurement area start address and a measurement area end address as measurement address information as measurement target areas for access to the memory, and an access destination address is stored for each access to the memory in the process. An address comparison unit that instructs the access measurement unit to measure the access amount within a range between the measurement region start address and the measurement region end address may be further provided.

  Preferably, the time measurement unit may hold the start time, the end time, and the access amount measured by the access measurement unit.

  According to the present invention, by acquiring the access time information together with the access amount of each process, it is possible to take measures for avoiding performance degradation even when memory accesses are concentrated.

(Principle explanation)
The present invention can be used in a system including a plurality of processing devices and a memory in which the plurality of processing devices serve as a bus master. For example, a multi-core processor in which processor cores are provided as a plurality of processing devices, and the processing devices share a bus as a bus master. A system having a plurality of units sharing a bus with a unit including a CPU as a processing device and each unit as a bus master.

  The processing device includes a time measurement unit and an access measurement unit, and the time measurement unit measures the access start time and end time to the memory for each process executed by the processing device using the time notified from the timer, The access measurement unit measures the access amount to the memory of each process from the start to the end of each process.

  Through the above measurement, processing information can be acquired in a format that can correspond to functions, tasks, and variables of application software. Specifically, the function unit bandwidth use information, the function unit start time and end time based on time information common to all bus masters, and the bus bandwidth usage rate for each variable access are acquired.

  For example, when developing application software using a high-level language such as C language, the user uses the obtained result to change the function assignment to the bus master, change the function execution order, and change the memory allocation for each variable. This makes it possible to examine performance and avoid performance degradation due to bus access concentration.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Example 1
(Constitution)
The system 1 shown in FIG. 1 is an example in which a plurality of processor cores 4 (cores 0 to N), a DMA 9 (Direct Memory Access Unit), etc. share a bus and a memory unit 3 (SDRAM or the like). It is. The multi-core processor 2 includes a processor core 4, a DMA 9, and a timer unit 10.

Each processor core 4 (processing device) includes a processing unit 5, a local memory 6, a time measurement unit 7, and an access measurement unit 8.
The processing unit 5 is assigned processing 00, 01, 02 to (unit of function or task) in the processor core 4 (core 0). For example, functions constituting a program written in a high-level language are allocated to the processor core 4 (core 0) that is each bus master. Similarly, processing to be executed by the processor cores 4 (core 1) to (core N) is assigned, and each processing unit 5 executes the assigned processing.

The local memory 6 can hold programs, data, processing results (FIG. 1, acquired information), and the like.
The time measuring unit 7 uses the time notified from the timer unit 10 to measure the access start time and access end time to the memory (memory unit 3) of each process when the processor core 4 and the DMA 9 are executed.

  The access measurement unit 8 measures the access amount to the memory (memory unit 3) of each process from the start to the end of the process. It is assumed that this access amount is given to the access measurement unit 8 as control information from the processing unit 5 of each core, for example, every time the memory unit 3 is accessed.

The timer unit 10 broadcasts the time to the processor core 4 and the time measuring unit 7 of the DMA 9 at the time of measurement. The timer unit 10 may use an OS system counter or the like.
The memory unit 3 can hold data, the access start time, the access end time, and the access amount that are measured for the processing of each processor core 4 and the processing of the DMA 9 (FIG. 1, acquired information). These measurement results may be held in the local memory 6 or the like.

FIG. 2 shows configurations of the time measuring unit 7 and the access measuring unit 8.
The time measurement unit 7 includes a plurality of flag units 11, a time acquisition unit 12, and a count value output unit 13.

  The multiple flag unit 11 has multiple flags. As shown in FIG. 2, for example, flags 00 to 0n (n is a natural number of 1 or more) are prepared for the core 0. For example, a special register is used, and the flag is set by rewriting the special register. In addition, the time acquisition unit 12, the count value output unit 13, and the access measurement unit 8 are notified that the flag has been set when an arbitrary flag is set, and the time acquisition unit 12 and the count value that the flag has been negated when the flag is negated The output unit 13 and the access measurement unit 8 are notified.

  The time acquisition unit 12 acquires the time notified from the timer unit 10 when the flag is set (when any flag is set) as the measurement start time. The time notified from the timer unit 10 at the time of flag negation is acquired as the measurement end time. The acquired measurement start time and measurement end time are output to the memory area corresponding to the flag.

  The count value output unit 13 reads data from the count value register unit 14 at the time of flag negation, and writes the count value in the corresponding area. The count value is held in the memory area corresponding to the flag set as the access amount.

  Here, the memory area is a memory allocated to the memory unit 3, the local memory 6, a dedicated memory, and the like. In the case of using a dedicated memory, n measurement start times, measurement end times, and areas capable of holding the access amount are secured, and when the memory unit 3 and the local memory 6 are used, the number of flags is n. An area that can hold the measurement start time, end time, and access amount is secured.

The access measurement unit 8 includes a count value register unit 14 and an access amount detection counter unit 15.
The access amount detection counter unit 15 sets the counter of the access amount detection counter unit 15 to 0 when the flag of the time measurement unit 7 is set, and counts up every time there is access to the memory until it is negated. Count up. The count value is notified to the count value register unit 14.

FIG. 3 shows a processing sequence corresponding to the program of the processor core 4. FIG. 4 shows details of each process.
In FIG. 3, the measurement start time, the measurement end time, and the access amount are stored in the memory by executing steps S1 to S3 for the process 00.

In step S1, time information for process 00 is acquired (measurement start time). Start measuring access amount for each memory access.
In step S2, process 00 is executed.

In step S3, time information for process 00 is acquired (measurement end time). The access amount measurement for each memory access is terminated.
Similarly, steps S4 to S6 are executed to store the measurement start time, measurement end time, and access amount related to process 01 in the memory, and steps S7 to S9 are executed to determine the measurement start time, measurement end time, and access amount of process 02. Save to memory.

The same processing is performed on the other processor cores 4 (cores 1 to N).
Next, FIG. 4 will be described.
In process 00, in order to obtain the access amount, a description for setting a flag is inserted at the beginning of the range of the program whose access amount is to be measured, and a description for negating the flag is inserted at the end of the range to be measured. The code for performing the flag set and the flag negation as described above is described in a program that executes a process that needs to measure an access amount and a DMA.

In step S41, for example, a flag i (0i) corresponding to process i (for example, 0i) is set.
In step S42, when the flag is set, the time acquisition unit 12 stores the time information of the timer unit 10 as the start time in the memory area corresponding to the flag i. i is a number for identifying a process.

  For example, when the processor core 4 (core 0) that executes the process 00 executes the program and the code for setting the flag for the process 00 is executed, it corresponds to the process 00 of the multiple flag unit 11 of the time measuring unit 7. Flag 00 is set. When the flag is set, the time acquisition unit 12 acquires the time information notified from the timer unit 10 as the measurement start time of the process 00. Further, it notifies the count value output unit 13 and the access amount detection counter unit 15 of the access measurement unit 8 that the flag has been set. Here, the measurement start time may be stored in the memory area, but may be stored in the time acquisition unit 12 and stored in the memory area after negation.

In step S43, processing is executed, and the access amount detection counter unit 15 counts up the access amount for each memory access and stores it in the count value register unit 14.
For example, in the case of processing 00, the access measurement unit 8 receives the flag set notification and sets the counter value of the counter that measures the access amount of the access amount detection counter unit 15 to zero. Thereafter, each time the process 00 is executed, the access amount is detected and the counter value is incremented to measure the access amount.

In step S44, the flag i corresponding to the process i is negated.
In step S45, the time acquisition unit stores the time information of the timer unit as an end time in the memory area corresponding to the flag i.

  For example, when the processor core 4 (core 0) that executes the process 00 executes the program and the code that negates the flag for the process 00 is executed, it corresponds to the process 00 of the multiple flag unit 11 of the time measuring unit 7. The time acquisition unit 12 acquires the time when the flag 00 is negated and the time notified from the timer unit 10 is the measurement end time. Further, it notifies the count value output unit 13 and the access amount detection counter unit 15 of the access measurement unit 8 that the flag has been negated. Thereafter, the measurement end time is stored in the memory area.

In step S46, the count value output unit 13 stores the count value of the count value register unit 14 in the memory area corresponding to the read flag i.
For example, in the case of process 00, when the flag 00 for process 00 is negated, the access amount detection counter unit 15 of the access measurement unit 8 stops measuring the access amount, and the value stored in the count value register unit 14 is It is output to the count value output unit 13. The acquired measurement start time, measurement end time, and access amount are collectively held in any of the memory unit 3, the local memory 6, and the dedicated memory.

FIG. 5 illustrates a display using the measurement start time, the measurement end time, and the access amount, and a method for using the display.
FIG. 5 is a graph showing the access amount on the vertical axis and the measurement time on the horizontal axis. By displaying the graph as shown in FIG. 5 based on the measured information, it is possible to visually grasp at which time each process of the processor cores 4 overlaps to use the bus bandwidth to the upper limit. .

In the table shown in FIG. 5, measurement start time, measurement end time, and access amount data stored in a memory using a debugger or the like are read from the memory and displayed on a display unit such as a PC.
Further, the access amount displayed for each process is, for example, displayed as a section by averaging the count values counted between the measurement start time and the measurement end time. In order to acquire a more detailed access amount, a plurality of flags may be provided for each process to measure the measurement start time and the measurement end time.

  In the period from T0 to T1, simultaneously with DMA, the processing 00 (for example, a unit of function or task) of the processor core 4 (core 0) and the processing 10 of the processor core 4 (core 1) are accessing the memory.

In the period from T1 to T2, simultaneously with DMA, the processing 00 of the processor core 4 (core 0) and the processing 11 of the processor core 4 (core 1) are accessing the memory.
In the period from T2 to T3, simultaneously with DMA, the processing 01 of the processor core 4 (core 0) and the processing 11 of the processor core 4 (core 1) are accessing the memory. In this section, the bus bandwidth is approaching its limit.

In the period from T3 to T4, simultaneously with DMA, the process 01 of the processor core 4 (core 0) and the process 12 of the processor core 4 (core 1) are accessing the memory.
In the period from T4 to T5, simultaneously with DMA, the process 02 of the processor core 4 (core 0) and the process 12 of the processor core 4 (core 1) are accessing the memory.

In the period from T5 to T6, the processing 02 of the processor core 4 (core 0) is performing memory access simultaneously with DMA or the like.
From the above graph, it is highly possible that the performance degradation is caused by arbitration of bus access in the sections T2 to T3 where the bus bandwidth is used up to the upper limit. In order to avoid this performance degradation, it is possible to reduce the bus bandwidth to be used by changing the processing (function or task) assignment to each processor core 4 and changing the execution order in the processor core 4.
In the example of FIG. 5, the user can consider soft tuning so as not to exceed the bus bandwidth by replacing the process 12 with the process 11 and executing the process after the process 01 is completed.

(Example 2)
In the second embodiment, an address comparison unit is further provided in the first embodiment, and an access amount, a measurement start time, and a measurement end time with respect to a specified memory area (such as a variable) are measured.
(Constitution)
FIG. 6 shows a system configuration for measuring the access amount, the measurement start time, and the measurement end time for the specified area. The difference between the first embodiment and the second embodiment is that an address comparison unit 16 is added.

  The address comparison unit 16 holds a start address and an end address of a memory area whose access amount is to be measured, detects an address and an access amount when an access to the memory area occurs, and finishes when the address is more than the start address held. If it is less than the address, the access measuring unit 8 is notified of the access amount.

The access measuring unit 8 counts the address amount notified from the address comparing unit 16 when the flag information notified from the time measuring unit 7 is set.
FIG. 7 shows the configuration of the time measurement unit 7, the access measurement unit 8, and the address comparison unit 16 provided for each processor core 4.

The address comparison unit 16 includes an address comparator 17 and a measurement area register 18.
When any of the flags is set, the address comparator 17 compares the memory access destination address with the measurement area register value, and notifies the access amount detection counter unit 15 of the access amount within the range.

  The access amount detection counter unit 15 shown in FIG. 7 counts only when there is a notification from the address comparator 17 in addition to the function shown in the first embodiment. Unless there is a notification, no measurement is performed because the memory area is not set in the measurement area register 18.

The measurement area register 18 holds an address serving as a start point and an end point of a memory area to be measured for processing executed for each processor core 4.
FIG. 8 shows a processing sequence corresponding to the program.

  By executing steps S71 to S73 for process 00, the start point and end point of the address of the memory area to be measured are set, and the measurement start time, the measurement end time, and the access amount to the specified memory area are stored in the memory.

In step S71, time information for process 00 is acquired (measurement start time). The access amount measurement is started every time the specified memory area is accessed.
In step S72, process 00 is executed.

In step S73, time information for process 00 is acquired (measurement end time). Ends the access amount measurement for each access to the specified memory area.
Similarly, steps S74 to S76 are executed to store the measurement start time, measurement end time, and access amount related to process 01 in the memory, and steps S77 to S79 are executed to determine the measurement start time, measurement end time, and access amount of process 02. Save to memory.

The same processing is performed on the other processor cores 4 (cores 1 to N).
Next, FIG. 9 will be described.
In process 00, in order to obtain the access amount of the specified memory area, the address comparison unit 16 is supplied with the start address (start point) and end address (end point) of the memory area whose address amount is to be measured before the description of setting the flag. Insert description to set. Also, a description for setting a flag is inserted at the beginning of the range of the program whose access amount is to be measured, and a description for negating the flag is inserted at the end of the range to be measured. The code for setting, flag set, and flag negation as described above is described in a process that needs to measure the access amount and a program that executes DMA.

In step S91, a measurement address is set.
In step S92, when each processor core 4 executes a program and a description for setting the start address and end address of the memory area whose address amount is to be measured is set in the address comparison unit 16, the start address is stored in the address comparator 17. And the end address are set in the measurement area register 18.

In step S93, the flag i (0i) corresponding to the process i (for example, 0i) is set.
In step S94, when a code for setting an arbitrary flag is executed, a corresponding flag is set in the time measurement unit 7, and as described above, the time information notified from the timer unit 10 is acquired as the measurement start time. The access measurement unit 8 is notified that i has been set. Here, i is a number for identifying a process.

In step S95, the address comparison unit 16 compares the access destination address with the start point and end point addresses held in the measurement area register 18 during memory access during flag setting. If the access destination address is not less than the start point and less than the end point, the access amount is notified to the access amount detection counter unit 15.

  In step S96, the process is executed, and the access amount detection counter unit 15 receives a flag set notification and sets a counter for counting the access amount to zero. Further, every time the memory is accessed, the address comparator 17 notifies the access amount detection counter unit 15 that the memory has been accessed. The access amount detection counter unit 15 counts up the access amount for each memory access and stores it in the count value register unit 14.

  For example, in the case of processing 00, the access measurement unit 8 receives the flag set notification and sets the counter value of the counter that measures the access amount of the access amount detection counter unit 15 to 0. Thereafter, if there is a notification from the address comparator 17 when the processing 00 is executed, the access amount is detected and the counter value is incremented every time the memory is accessed, and the access amount is measured.

In step S97, the flag i corresponding to the process i is negated.
In step S98, the time acquisition unit 12 stores the time information of the timer unit 10 as a measurement end time in the memory area corresponding to the flag i.

In step S99, the count value output unit 13 stores the count value of the count value register unit 14 in the memory area corresponding to the read flag i.
For example, in the case of process 00, when the flag 00 for process 00 is negated, the access amount detection counter unit 15 of the access measurement unit 8 stops measuring the access amount to the target memory area, and the measured count value is the count value. The count value is read to the register unit 14 and the count value is output to the count value output unit 13. The acquired measurement start time, measurement end time, and access amount are held in the memory unit 3, the local memory 6, or the dedicated memory as a set.

  By doing the above, for example, the band usage information (access amount) for each measurement section of the measurement section specified in the application software that is operated by hardware, and the measurement start time and measurement end time of the measurement section processing are measured as a set can do.

  The graph shown in FIG. 10 is displayed based on the band usage information (address start point and end point) of the measurement section, the measurement start time and measurement end time of the measurement section processing, and the access amount to the specified memory area. The vertical axis in FIG. 10 indicates the designated memory area, and the horizontal axis indicates the access amount. In the table shown in FIG. 10, the bandwidth usage information, the measurement start time, the measurement end time, and the access amount data of the measurement section are read from the memory and displayed on a display unit such as a PC using a debugger or the like.

The graph shown in FIG. 10 displays access to the memory area of the processor core 4 (core 1) for each area.
It shows how much memory access has been made to area 1 of the memory area. Similarly, for the areas 2 to 4, how much memory access has been made to each area is shown. That is, the total access amount in the area. By visualizing in this way, it can be seen in FIG. 10 that the amount of access to the area 2 is larger than in other areas, and the user can examine the graph.

As a result, by using the measurement interval on the application program to be measured as the unit of parallelization of application programs for multiprocessors such as functions and tasks, it is possible to avoid performance degradation due to memory access concentration using measurement information Program tuning can be performed.

For example, since the access amount for each variable can be acquired, the access amount for one bus can be reduced by arranging a variable having a large bus access amount in an area using another bus such as the local memory 6. And performance degradation can be avoided.
The present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the gist of the present invention.

(Appendix 1)
A memory shared data processing system in which a plurality of processing devices share a memory,
The processor is
A time measuring unit for measuring a start time and an end time for each process executed by the processing device using a time notified from a timer;
An access measurement unit that measures the amount of access to the memory of the process between the start and end of the process;
A memory shared data processing system comprising:
(Appendix 2)
The processor is
A measurement area start address and a measurement area end address as measurement target areas for access to the memory are stored as measurement address information, and an access destination address is the measurement area start address and the measurement for each access to the memory in the process. The memory shared data processing system according to claim 1, further comprising an address comparison unit that instructs the access measurement unit to measure the access amount within a range between area end addresses.
(Appendix 3)
The time measuring unit is
The memory shared data processing system according to appendix 1 or 2, wherein the start time, the end time, and the access amount measured by the access measurement unit are held.
(Appendix 4)
An access amount measuring means for measuring an access amount to a memory common to the plurality of processing devices for each of the plurality of processing devices and within a time range instructed by the processing devices;
An access amount storage means for storing the result of the measurement for each processing device and for each time range;
A memory access amount measuring apparatus comprising:
(Appendix 5)
Measure the access amount to the memory common to the plurality of processing devices for each of the plurality of processing devices and for each time range instructed by the processing devices,
Storing the result of the measurement for each processing device and for each time range;
And a memory access amount measuring method.
(Appendix 6)
The time measuring unit is
A flag indicating measurement start and measurement end is used to measure the access amount for each process, and when the flag is set, the access measurement unit is notified of the start of measurement of the access amount, and the flag is negated. The memory shared data processing system according to claim 1, wherein the access measurement unit is notified of the end of measurement of the access amount.

1 is a diagram illustrating a system configuration of Embodiment 1. FIG. It is a figure which shows the time measurement part and access measurement part of the processor core of Example 1. FIG. FIG. 3 is a flowchart showing the operation of the first embodiment. FIG. 6 is a flowchart illustrating the operation of each process according to the first embodiment. It is a figure which shows the graph produced | generated based on the access amount of each process, measurement start time, and measurement end time. FIG. 3 is a diagram illustrating a system configuration of a second embodiment. It is a figure which shows the time measurement part of the processor core of Example 2, an access measurement part, and an address comparison part. FIG. 6 is a flowchart showing the operation of the second embodiment. FIG. 10 is a flowchart illustrating the operation of each process according to the second embodiment. It is a figure which shows the graph produced | generated based on the address of the memory area of each process, access amount, measurement start time, and measurement end time. It is a figure which shows the conventional system configuration. It is a figure which shows the flow which shows the access measurement part and operation | movement of the conventional processor core. It is an image diagram when the function is assigned to the bus master

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 System 2 Multi-core processor 3 Memory part 4 Processor core 5 Processing part 6 Local memory 7 Time measurement part 8 Access measurement part,
9 DMA
DESCRIPTION OF SYMBOLS 10 Timer part 11 Multiple flag part 12 Time acquisition part 13 Count value output part 14 Count value register part 15 Access amount detection counter part 16 Address comparison part 17 Address comparator 18 Measurement area register

Claims (4)

A memory shared data processing system in which a plurality of processing devices share a memory,
The processing device uses a time notified from a timer to measure a start time and an end time for each process executed in the processing device, and
An access measurement unit that measures the amount of access to the memory of the process between the start and end of the process;
A measurement area start address and a measurement area end address as measurement target areas for access to the memory are stored as measurement address information, and an access destination address is the measurement area start address and the measurement for each access to the memory in the process. An address comparison unit that instructs the access measurement unit to measure the amount of access if it is a range between region end addresses;
A memory shared data processing system comprising: The memory shared data processing system according to claim 1, wherein the time measurement unit holds the start time, the end time, and the access amount measured by the access measurement unit. An access amount measuring means for measuring an access amount to a memory common to the plurality of processing devices for each of the plurality of processing devices and within a time range instructed by the processing devices;
An access amount storage means for storing the result of the measurement for each processing device and for each time range;
The measurement area start address and the measurement area end address as the measurement target area for accessing the memory are held as measurement address information, and the access destination address is the measurement area start address and the measurement area end address for each access to the memory. Address comparison means for instructing the access amount measurement means to measure the access amount in the range between
A memory access amount measuring apparatus comprising: Measure the access amount to the memory common to the plurality of processing devices for each of the plurality of processing devices and for each time range instructed by the processing devices,
The result of the measurement is stored for each processing device and for each time range,
The measurement area start address and the measurement area end address as the measurement target area for accessing the memory are held as measurement address information, and the access destination address is the measurement area start address and the measurement area end address for each access to the memory. Instruct the measurement of the access amount if the range is between
And a memory access amount measuring method.

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