JP5561241B2 - Microcomputer - Google Patents

Description

  The present invention relates to a microcomputer virtually mounting a plurality of cores.

  In recent years, in order to cope with the increase in the number of ECU development steps accompanying the increase in the number of electronic control devices (hereinafter referred to as ECUs) mounted on vehicles, the functions of a plurality of ECUs are referred to as single microcomputers (hereinafter referred to as microcomputers). A method for improving the efficiency of ECU development by integrating the system into the system has been studied (for example, see Non-Patent Document 1).

"Fiscal Year 2007 Report", page 4, [online], DENSO Corporation, [Search on April 22, 2011], Internet <URL: http://www.denso.co.jp/en/investors /financial/report/files/business2008#3.pdf>

  By the way, the function of ECU (hereinafter referred to as ECU function) has different operation start conditions and operation stop conditions for each function. For example, a function that starts when the IG switch is turned on and stops when the IG switch is turned off, and a function that starts when the vehicle battery power is supplied to the ECU and continues until the power supply stops and so on.

  Note that the operation start and operation stop of the ECU function are often realized by the operation start and operation stop of the microcomputer, respectively. However, when a plurality of ECU functions having different operation start conditions and operation stop conditions are integrated into a single microcomputer, the operation start conditions and the operation stop conditions cannot be satisfied for all ECU functions integrated in the single microcomputer. If the ECU function operates in a state where the operation start condition set in the function is not satisfied, there is a possibility of causing a malfunction. For this reason, it is necessary to correct the control logic for the ECU function that does not match the operation start condition and the operation stop condition of the integration destination microcomputer, and there is a problem that the man-hour for ECU development increases.

  The present invention has been made in view of these problems, and an object of the present invention is to provide a technique capable of suppressing an increase in development man-hours when integrating a plurality of ECU functions into a single microcomputer.

The microcomputer according to claim 1, which has been made to achieve the above object, is mounted on a vehicle-mounted control device , and a plurality of cores are virtually created by using a single core resource in a time-sharing manner. Whether or not the core activation means satisfies a core activation condition set in advance for each of the plurality of virtual cores, with the core virtually operating in the microcomputer as a virtual core. If it is determined that the core start condition is satisfied, a process for starting the virtual core corresponding to the satisfied core start condition is executed, and the core stop unit is set in advance for each of the plurality of virtual cores. If the determined core stop condition is satisfied, and if it is determined that the core stop condition is satisfied, the behavior of the virtual core corresponding to the satisfied core stop condition is determined. That perform a process to stop. The microcomputer according to claim 1 is characterized in that it gives priority to the core activation means but can execute other processes in parallel.

  Since the microcomputer configured as described above operates as if a plurality of cores (virtual cores) exist virtually, a plurality of ECU functions are assigned by assigning each of the plurality of ECU functions to each virtual core. Can be integrated into a single microcomputer. Then, the core activation unit and the core stop unit perform activation and operation stop for each of the plurality of virtual cores. For this reason, for virtual cores whose starting and stopping of the microcomputer are not the core starting condition and the core stopping condition (hereinafter referred to as a starting / stopping condition different core), the core starting condition and the core corresponding to the starting / stopping condition different core If the stop condition is set on the core starter side and the core stop means side, the control logic correction corresponding to the difference between the core start condition and the core stop condition is different from that of the microcomputer. It becomes unnecessary, and the amount of correction is reduced compared to the case where the control logic is corrected on the core side where the start / stop conditions differ. Thereby, the increase in the development man-hour at the time of integrating several ECU function into a single microcomputer using several virtual cores can be suppressed.

  Further, in the microcomputer according to claim 1, as described in claim 2, the microcomputer is executed by the core activation means within a preset priority period after activation immediately after the microcomputer is activated. Processing may be executed with priority over other processing.

  For example, by assigning a single core resource only to the core startup means within the post-startup priority period and operating multiple virtual cores after the post-startup priority period ends, the cores within the post-startup priority period The activation means may be executed with priority.

  In the microcomputer configured as described above, since the core activation means is preferentially executed within the priority period after activation immediately after the microcomputer is activated, the virtual core that needs to be activated immediately after the microcomputer is activated Generation | occurrence | production of the situation where starting will be delayed for execution of processes other than a core starting means can be suppressed.

2 is a block diagram showing a configuration of a microcomputer 1. FIG. It is a flowchart which shows a hypervisor process. It is a flowchart which shows a core manager process. It is a timing chart explaining the procedure of starting and operation stop of virtual cores 21-24.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a microcomputer (hereinafter referred to as a microcomputer) 1 according to the present embodiment.

  The microcomputer 1 is mounted on a vehicle, and as shown in FIG. 1, a microcomputer core (hereinafter simply referred to as a core) 11 including an arithmetic unit and a register for executing a program, and an IG switch signal or the like from the outside. And an I / O port 12 having a function of inputting various switch signals.

  Of these, the core 11 is configured to be activated when power is supplied from an in-vehicle battery (not shown). In addition, the core 11 uses the CPU virtualization technology that operates so that a plurality of cores exist virtually by using the resources of the core 11 in a time-sharing manner in units of clocks. , 23, 24 are operated in parallel.

Furthermore, the core 11 is equipped with a function 30 (hereinafter referred to as a hypervisor 30) for managing the operation state of each virtual core when the microcomputer power is turned on.
The virtual core 21 is equipped with a function 31 (hereinafter referred to as a core manager 31) for managing the operation state of each virtual core except when the microcomputer power is turned on. Each of the cores 22, 23, and 24 is equipped with, for example, a power control function 32, a start control function 33, and a charge control function 34.

  The hypervisor process and the core manager process executed by the hypervisor 30 mounted on the core 11 of the microcomputer 1 and the core manager 31 mounted on the virtual core 21 configured as described above are shown in FIGS. Will be described. FIG. 2 is a flowchart showing the hypervisor process, and FIG. 3 is a flowchart showing the core manager process.

  The hypervisor process is a process that starts when the core 11 is activated upon receiving power supply from the in-vehicle battery. When this hypervisor process is executed, the core 11 first proceeds to S10 as shown in FIG. Thus, it is determined whether or not the core activation condition for the virtual core 22 is satisfied. Note that the core activation condition of the virtual core 22 in the present embodiment is that the microcomputer 1 is supplied with power from the in-vehicle battery.

  If the core activation condition of the virtual core 22 is satisfied (S10: YES), the operation state of the virtual core 22 is set to “activated” in S20, and the process proceeds to S40. On the other hand, if the core activation condition of the virtual core 22 is not satisfied (S10: NO), the operation state of the virtual core 22 is set to “stop” in S30, and the process proceeds to S40.

  When the process proceeds to S40, it is determined whether or not the core activation condition of the virtual core 23 is satisfied. Note that the core activation condition of the virtual core 23 in the present embodiment is that the IG switch is on.

  If the core activation condition for the virtual core 23 is satisfied (S40: YES), the operation state of the virtual core 23 is set to “activated” in S50, and the process proceeds to S70. On the other hand, when the core activation condition of the virtual core 23 is not satisfied (S40: NO), the operation state of the virtual core 23 is set to “stop” in S60, and the process proceeds to S70.

  In S70, it is determined whether or not the core activation condition for the virtual core 24 is satisfied. Note that the core activation condition of the virtual core 24 in the present embodiment is that the IG switch is on.

  If the core activation condition for the virtual core 24 is satisfied (S70: YES), the operation state of the virtual core 24 is set to “activated” in S80, and the process proceeds to S100. On the other hand, when the core activation condition of the virtual core 24 is not satisfied (S70: NO), the operation state of the virtual core 24 is set to “stop” in S90, and the process proceeds to S100.

  When the process proceeds to S100, the core 11 is shifted to the virtual core mode, and the hypervisor process is terminated. The virtual core mode is a mode in which the virtual cores 21, 22, 23, and 24 are operated in parallel. In other words, only the hypervisor process is executed until the hypervisor process ends after the core 11 is activated, and no processes other than the hypervisor process are executed.

  When the virtual core mode is entered, the virtual core 21 and the virtual core whose operation state is set to “activated” in the processing of S10 to S90 among the virtual cores 22, 23, and 24 are activated, and the activated virtual core is activated. Operate in parallel.

  Next, the core manager process is a process that is started when the virtual core 21 is activated. When this core manager process is executed, the virtual core 21 first starts the virtual core in S210 as shown in FIG. It is determined whether or not 22 is operating. If the virtual core 22 is operating (S210: YES), it is determined in S220 whether or not the core stop condition for the virtual core 22 is satisfied. Note that the core stop condition of the virtual core 22 in the present embodiment is that the microcomputer 1 does not receive power supply from the in-vehicle battery.

  If the core stop condition for the virtual core 22 is satisfied (S220: YES), the operation state of the virtual core 22 is set to “stop” in S230, and the process proceeds to S260. As a result, the virtual core 22 stops operating. On the other hand, when the core stop condition of the virtual core 22 is not established (S220: NO), the process proceeds to S260.

  If the operation of the virtual core 22 is stopped in S210 (S210: NO), it is determined in S240 whether the core activation condition for the virtual core 22 is satisfied. If the core activation condition for the virtual core 22 is satisfied (S240: YES), the operation state of the virtual core 22 is set to “activated” in S250, and the process proceeds to S260. As a result, the virtual core 22 is activated. On the other hand, when the core activation condition of the virtual core 22 is not established (S240: NO), the process proceeds to S260.

  In S260, it is determined whether or not the virtual core 23 is operating. If the virtual core 23 is operating (S260: YES), it is determined in S270 whether or not the core stop condition for the virtual core 23 is satisfied. Note that the core stop condition of the virtual core 23 in the present embodiment is that the IG switch is off.

  If the core stop condition for the virtual core 23 is satisfied (S270: YES), the operation state of the virtual core 23 is set to “stop” in S280, and the process proceeds to S310. As a result, the virtual core 23 stops operating. On the other hand, when the core stop condition of the virtual core 23 is not established (S270: NO), the process proceeds to S310.

  If the operation of the virtual core 23 is stopped at S260 (S260: NO), it is determined at S290 whether the core activation condition for the virtual core 23 is satisfied. If the core activation condition for the virtual core 23 is satisfied (S290: YES), the operation state of the virtual core 23 is set to “activated” in S300, and the process proceeds to S310. As a result, the virtual core 23 is activated. On the other hand, when the core activation condition of the virtual core 23 is not established (S290: NO), the process proceeds to S310.

  In S310, it is determined whether or not the virtual core 24 is operating. If the virtual core 24 is operating (S310: YES), it is determined in S320 whether or not the core stop condition for the virtual core 24 is satisfied. Note that the core stop condition of the virtual core 24 in the present embodiment is that the IG switch is off.

  If the core stop condition for the virtual core 24 is satisfied (S320: YES), the operation state of the virtual core 24 is set to “stop” in S330, and the process proceeds to S210. Repeat the process. As a result, the virtual core 24 stops operating. On the other hand, when the core stop condition of the virtual core 24 is not satisfied (S320: NO), the process proceeds to S210 and the above-described processing is repeated.

  If the operation of the virtual core 24 is stopped in S310 (S310: NO), it is determined in S340 whether the core activation condition for the virtual core 24 is satisfied. If the core activation condition for the virtual core 24 is satisfied (S340: YES), the operation state of the virtual core 24 is set to “activated” in S350, and the process proceeds to S210. Repeat the process. As a result, the virtual core 24 is activated. On the other hand, when the core activation condition of the virtual core 24 is not satisfied (S340: NO), the process proceeds to S210 and the above-described processing is repeated.

  Next, activation and operation stop of the virtual cores 21 to 24 after the microcomputer 1 is activated will be described with reference to FIG. FIG. 4 is a timing chart for explaining the procedure for starting and stopping the operation of the virtual cores 21 to 24.

  As shown in FIG. 4, when a vehicle-mounted battery is connected and power is supplied to the microcomputer 1 (see time t1), the microcomputer 1 is activated and starts operating (see time t2). Thereby, hypervisor processing is started. Then, the operating states of the virtual cores 22, 23, and 24 are set to “start”, “stop”, and “stop” by the hypervisor process, respectively. Therefore, when the hypervisor process ends, the core 11 enters the virtual core mode. The virtual cores 21 and 22 perform the parallel operation (see time t3).

  After that, when the IG switch is turned on (see time t4), the operating state of the virtual cores 23 and 24 is set to “started” by the core manager process executed by the virtual core 21, so the virtual cores 23 and 24 are started. Thus, the virtual cores 21, 22, 23, and 24 perform a parallel operation. Further, when the IG switch is turned off (see time t5), the operating state of the virtual cores 23 and 24 is set to “stop” by the core manager process. The cores 21 and 22 perform a parallel operation.

  In the microcomputer 1 configured as described above, the resources of the single core 11 are used in a time-sharing manner so that a plurality of virtual cores exist virtually, and the plurality of virtual cores 22, 23, It is determined whether or not a preset core activation condition is established for each of 24, and when it is determined that the core activation condition is established, a process of activating a virtual core corresponding to the established core activation condition (S10 to S10) S100, S240, S250, S290, S300, S340, and S350), and whether or not a core stop condition set in advance for each of the plurality of virtual cores 22, 23, and 24 is satisfied is determined. When it is determined that the condition is satisfied, processing for stopping the operation of the virtual core corresponding to the satisfied core stop condition is executed (S220, S230, S270). S280, S320, S330).

  In the microcomputer 1 configured as described above, the hypervisor process and the core manager process start and stop the operation of each of the plurality of virtual cores 22, 23, and 24. For this reason, for cores whose activation and deactivation of the microcomputer 1 are not the core activation condition and the core deactivation condition (hereinafter referred to as different cores for activation and deactivation conditions), the core activation condition and the core deactivation corresponding to this activation / deactivation condition difference core If the conditions are set in the hypervisor process and the core manager process, the correction of the control logic corresponding to the difference in the core start condition and the core stop condition from the microcomputer 1 becomes unnecessary on the start / stop condition different core side, The amount of correction is reduced compared to the case where the control logic is corrected on the core side where the start / stop conditions differ. Thereby, the increase in the development man-hour at the time of integrating a some ECU function into the microcomputer 1 using a some virtual core can be suppressed.

  Further, the microcomputer 1 executes only the hypervisor process and does not execute any process other than the hypervisor process within a period from when the microcomputer 1 starts up until the hypervisor process ends. As a result, it is possible to suppress the occurrence of a situation in which the activation of the virtual cores 21 and 22 that need to be activated immediately after the microcomputer is activated is delayed due to the execution of processes other than the hypervisor process.

  In the embodiment described above, the processes of S10 to S100, S240, S250, S290, S300, S340, and S350 are the core activation means in the present invention, and the processes of S220, S230, S270, S280, S320, and S330 are the core in the present invention. The period from the start of the stop means and the microcomputer 1 to the end of the hypervisor processing is the priority period after startup in the present invention.

As mentioned above, although one Embodiment of this invention was described, this invention is not limited to the said embodiment, As long as it belongs to the technical scope of this invention, a various form can be taken.
For example, in the above-described embodiment, the core 11 does not execute any processing other than the hypervisor processing until the hypervisor processing is completed after the microcomputer 1 is activated. However, by executing the hypervisor processing with priority. In the core 11, hypervisor processing and processing other than hypervisor processing may be operated in parallel.

In the above embodiment, the microcomputer 1 is shown with four virtual cores mounted thereon, but the number of virtual cores is not limited to this and may be two or more.
In the above embodiment, the core activation condition is information from outside the microcomputer such as “receiving power from an in-vehicle battery” or “IG switch is on”. The information is not limited, and information inside the microcomputer (for example, the state of internal resources) may be used, or information from outside the microcomputer and information inside the microcomputer may be used in combination.

  DESCRIPTION OF SYMBOLS 1 ... Microcomputer, 11 ... Core, 12 ... I / O port 21, 22, 23, 24 ... Virtual core, 30 ... Hypervisor, 31 ... Core manager

Claims (2)

A microcomputer that is mounted on a control device mounted on a vehicle and that operates as if multiple cores exist virtually by using a single core resource in a time-sharing manner,
With the core virtually existing in the microcomputer as a virtual core, it is determined whether a preset core activation condition is established for each of the plurality of virtual cores, and the core activation condition is established A core activation unit that executes a process of activating the virtual core corresponding to the established core activation condition when it is determined;
It is determined whether a preset core stop condition is satisfied for each of the plurality of virtual cores, and when it is determined that the core stop condition is satisfied, the virtual core corresponding to the satisfied core stop condition is determined. and a core stop means for executing a process for stopping the operation,
A microcomputer characterized in that priority is given to the core starting means, but other processing can be executed in parallel . The microcomputer is
2. The process executed by the core starting means is prioritized over other processes within a preset post-start priority period immediately after the microcomputer is started. Microcomputer.

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