JP5884788B2 - Microcomputer - Google Patents

Description

  The present invention relates to a microcomputer equipped with a reconfigurable device.

  Conventionally, in order to cope with an increase in the number of ECU development steps accompanying an increase in the number of electronic control units (hereinafter referred to as ECUs) mounted on a vehicle, a plurality of ECU functions are referred to as a single microcomputer (hereinafter referred to as a microcomputer). A method for improving the efficiency of ECU development by integrating the system into the system has been studied (see, for example, Non-Patent Document 1).

  In recent years, it has become possible to mount a reconfigurable device typified by an FPGA in a microcomputer, thereby increasing the feasibility of a technology that integrates the functions of a plurality of ECUs into a single microcomputer. . Because special functions required for each functional field of the ECU are formed in the reconfigurable device installed in the microcomputer, each function of multiple ECUs can be handled with a single microcomputer. It is.

"Fiscal Year 2007 Report", page 4, [online], DENSO Corporation, [Search July 2, 2013], Internet <URL: http://www.denso.co.jp/en/investors /financial/report/files/business2008#3.pdf>

  However, when a reconfigurable device in which a plurality of special functions are formed is installed in a microcomputer, processing requests for a specific function among a plurality of functions are frequently issued, so that processing of a specific function can be performed. If executed centrally, there is a concern that processing of other functions cannot be executed.

  The present invention has been made in view of these problems, and an object of the present invention is to suppress the occurrence of a situation in which a process corresponding to another process request cannot be executed when a certain process request is issued frequently. And

The present invention made to achieve the above object is a microcomputer equipped with a reconfigurable device.
In the microcomputer of the present invention, the reconfigurable device has one request source as a first request source among a plurality of request sources that issue processing requests to the reconfigurable device, A first process execution unit configured to execute a process corresponding to a first process request issued from the first request source, with one request source different from the first request source as a second request source; And a second process execution unit configured to execute a process corresponding to the second process request issued from the second request source.

  The microcomputer of the present invention is information indicating the upper limit of the number of times that the first process execution unit executes the process corresponding to the first process request within a preset arbitration unit period that is repeated at regular intervals. Based on the upper limit information and the second upper limit information, which is information indicating the upper limit of the number of times the second process execution unit executes the process corresponding to the second process request within the arbitration unit period, the first process request is supported. The arbitration function is determined by hardware so as to determine whether or not to cause the first process execution unit to execute the process and whether or not to cause the second process execution unit to execute the process corresponding to the second process request. Arbitration circuit is provided.

  The microcomputer of the present invention configured as described above limits the number of times the first process execution unit executes the process corresponding to the first process request within the arbitration unit period to a value equal to or less than the value indicated by the first upper limit information. Can do. Similarly, the microcomputer of the present invention can limit the number of times the second process execution unit executes the process corresponding to the second process request within the arbitration unit period to a value equal to or less than the value indicated by the second upper limit information.

  For this reason, even if the first processing request is frequently issued, the portion exceeding the value indicated by the first upper limit information is not executed by the first processing execution unit, and the processing of the first processing execution unit is not executed. Can be assigned to the process corresponding to the second process request. Conversely, even if the second processing request is frequently issued, the portion exceeding the value indicated by the second upper limit information is not executed by the second processing execution unit, and the processing of the second processing execution unit is not executed. Can be assigned to the process corresponding to the first process request.

  The restriction on the number of times the first process execution unit executes and the restriction on the number of times the second process execution unit executes are performed for each arbitration unit period. For this reason, the shorter the arbitration unit period, the shorter the period during which the processing corresponding to the second processing request cannot be executed when the first processing request is issued frequently. The first process request that exceeds the value indicated by the first upper limit information within the arbitration unit period is not executed by the first process execution unit, and can be assigned to the process corresponding to the second process request within the arbitration unit period. Because it can. Similarly, the shorter the arbitration unit period, the shorter the period during which processing corresponding to the first processing request cannot be executed when the second processing request is issued frequently.

  As described above, the microcomputer of the present invention can suppress the occurrence of a situation in which a processing request corresponding to another processing request cannot be executed when a certain processing request is frequently issued.

2 is a block diagram showing a configuration of a microcomputer 1. FIG. 3 is a block diagram illustrating a configuration of an arbitration circuit 4. FIG. It is a flowchart which shows the procedure of an arbitration process. 3 is a timing chart showing the operation of the microcomputer 1. It is a block diagram which shows that the processing request from one core is concentrated. It is a figure explaining the worst execution time. It is a block diagram which shows that the processing request is issued simultaneously from two cores.

Embodiments of the present invention will be described below with reference to the drawings.
As shown in FIG. 1, the microcomputer (hereinafter referred to as a microcomputer) 1 includes a core group 2, a reconfigurable device 3, an arbitration circuit 4, and a bus 5.

The core group 2 includes microcomputer cores (hereinafter simply referred to as cores) 11, 12, and 13 including an arithmetic unit and a register for executing a program.
The reconfigurable device 3 is an integrated circuit device that can freely change the hardware configuration and connection. In the present embodiment, the reconfigurable device 3 is, for example, an FPGA (Field Programmable Gate Array). The reconfigurable device 3 includes function units 21, 22 and 23 and a data storage unit 24.

  The functional units 21, 22, and 23 are configured by circuits having functions corresponding to the cores 11, 12, and 13, respectively. The data storage unit 24 stores arbitration data (accepting upper limit value, priority, reset determination value described later) set in advance for use when the arbitration circuit 4 executes processing.

  The arbitration circuit 4 is configured by hardware and is connected to the reconfigurable device 3 so as to be able to input and output data. The arbitration circuit 4 executes processing for arbitrating processing requests from the cores 11, 12, and 13 to the reconfigurable device 3.

The bus 5 connects the cores 11, 12, and 13 and the arbitration circuit 4 to each other so that data communication is possible.
As illustrated in FIG. 2, the arbitration circuit 4 includes a request reception unit 31, an arbitration data storage unit 32, a timing unit 33, an accepted number storage unit 34, a request determination unit 35, a holding unit 36, and a processing result transmission unit 37. .

The request receiving unit 31 receives a processing request from the cores 11, 12, and 13 to the reconfigurable device 3 via the bus 5.
The arbitration data storage unit 32 stores the arbitration data acquired from the data storage unit 24 of the reconfigurable device 3.

The timer 33 is a timer that automatically increments (adds 1) every 1 ms, for example. When the value is set to 0 at a certain point, the timer 33 increments from 0 again at that point.
The acceptance number storage unit 34 stores the number of processing requests accepted by the arbitration circuit 4 (hereinafter referred to as the request acceptance number) for each of the cores 11, 12, and 13. Hereinafter, the request acceptance numbers corresponding to the core 11, the core 12, and the core 13 are also referred to as a first request acceptance number, a second request acceptance number, and a third request acceptance number, respectively.

  The request determination unit 35 is based on the arbitration data stored in the arbitration data storage unit 32, the value of the timing unit 33, the request acceptance number stored in the acceptance number storage unit 34, and the like. Determines whether to accept or hold the received processing request, and outputs the accepted processing request to the reconfigurable device 3. A specific procedure for determination by the request determination unit 35 will be described later (see FIG. 3).

The holding unit 36 temporarily stores the processing request held by the request determination unit 35.
The processing result transmission unit 37 transmits the processing result output from the reconfigurable device 3 to the cores 11, 12, and 13 via the bus 5.

Next, processing executed by the arbitration circuit 4 (hereinafter referred to as arbitration processing) will be described.
When the arbitration process is executed, the arbitration circuit 4 first determines whether or not a processing request from the cores 11, 12, and 13 has been received in S10, as shown in FIG. If a processing request is received (S10: YES), it is determined in S20 whether there is a pending processing request. If there is no pending processing request (S20: NO), it is determined in S30 whether there are a plurality of received processing requests.

  Here, when the number of received processing requests is one (S30: NO), in S40, the request acceptance number corresponding to the core that is the request source of the received processing request is a preset acceptance upper limit value. It is judged whether it is less than. For example, when a processing request from the core 11 is received, it is determined whether or not the first request acceptance number is less than the acceptance upper limit value of the core 11. The acceptance upper limit value is set for each of the cores 11, 12, and 13 by the arbitration data. In this embodiment, the acceptance upper limit values of the cores 11, 12, and 13 are 3, 2, and 1, respectively.

  If the request acceptance number is less than the acceptance upper limit value (S40: YES), the processing request received in S10 is output to the reconfigurable device 3 in S50, and further output in S50 in S60. 1 is added to the request acceptance number corresponding to the core that is the request source of the processed request.

  Thereafter, in S70, it is determined whether or not the processing result corresponding to the processing request output in S50 is input from the reconfigurable device 3. Here, when the processing result has not been input (S70: NO), the processing of S70 is repeated to wait until the processing result is input. On the other hand, when the processing result is input (S70: YES), in S80, the input processing result is transmitted to the core that is the request source of the processing request output in S50 via the bus 5, and the processing proceeds to S210. Transition.

  If the request acceptance number is equal to or greater than the acceptance upper limit value at S40 (S40: NO), the processing request received at S10 is suspended at S90, and the process proceeds to S210. Note that the processing request held in S90 is stored in the holding unit 36.

  If there are a plurality of processing requests received at S30 (S30: YES), one processing is selected from the plurality of processing requests received at S100 based on the first selection condition set in advance. Select a request. The first selection condition of the present embodiment is “a processing request whose request source is a core having the highest priority among cores whose request acceptance number is less than the acceptance upper limit value”. The priority is set for each of the cores 11, 12, and 13 by the arbitration data. In the present embodiment, the priorities of the cores 11, 12, and 13 are 1, 2, and 3, respectively.

  For example, when processing requests from the cores 11, 12, and 13 are received and the number of requests accepted by the cores 11, 12, and 13 is less than the upper limit of acceptance, the processing request from the core 11 having the highest priority is received. Selected. Further, when a processing request is received from the cores 11, 12, and 13, and the number of requests accepted by the core 11 is equal to or greater than the upper limit of acceptance and the number of requests accepted of the cores 12 and 13 is less than the upper limit of acceptance, the request A processing request from the core 12 having the highest priority among the cores whose acceptance numbers are less than the acceptance upper limit value is selected.

  Thereafter, in S110, the processing request selected in S100 is output to the reconfigurable device 3, and in S120, the request acceptance number corresponding to the core that is the request source of the processing request output in S110 is incremented by one. In S130, the processing requests received in S10 other than those output in S110 are suspended, and the process proceeds to S70. Note that the processing request held in S130 is stored in the holding unit 36.

  If there is a pending processing request at S20 (S20: YES), the processing request received at S10 is suspended at S140. Note that the processing request held in S140 is stored in the holding unit 36.

  Thereafter, in S150, one processing request is selected from among the pending processing requests based on the preset second selection condition. The second selection condition of the present embodiment is “the processing request with the earliest timing stored in the holding unit 36 among the core processing requests whose request acceptance number is less than the acceptance upper limit value”. Thereafter, in S160, it is determined whether there are a plurality of processing requests selected in S150.

  If there is one selected processing request (S160: NO), the process proceeds to S180. On the other hand, if there are a plurality of selected processing requests (S160: YES), one processing request is selected from the plurality of processing requests selected in S150 based on the third selection condition set in advance in S170. Select. The third selection condition of the present embodiment is “a processing request whose request source is a core having the highest priority among the processing requests selected in S150”.

  In S180, one processing request selected in S150 or S170 is output to the reconfigurable device 3, and in S190, the request acceptance number corresponding to the core that is the request source of the processing request output in S180 is set to 1. Add, and proceed to S70.

  If no processing request is received at S10 (S10: NO), it is determined at S200 whether there is a pending processing request. If there is no pending processing request (S200: NO), the process proceeds to S210. On the other hand, when there is a pending process request (S200: YES), the process proceeds to S150 and the above process is repeated.

  In S210, it is determined whether or not the count value of the time measuring unit 33 is equal to or greater than a reset determination value preset by the arbitration data. The reset determination value corresponds to an arbitration unit period described later (see FIG. 4). Here, when the count value of the time measuring unit 33 is less than the reset determination value (S210: NO), the process proceeds to S10 and the above process is repeated. On the other hand, when the count value of the time measuring unit 33 is equal to or greater than the reset determination value (S210: YES), the requested acceptance number of the cores 11, 12, and 13 is reset (set to 0) in S220, and the process proceeds to S230. Thus, the count value of the timer 33 is reset (set to 0). Then, the arbitration process is temporarily terminated and restarted from the process of S10.

Next, a specific example of the operation of the microcomputer 1 configured as described above will be described.
As shown in FIG. 4, it is assumed that the core 11 first issues a processing request within the arbitration unit period (see processing request R1). At this time, the requested acceptance number of the core 11 is 0 and is smaller than the acceptance upper limit value of the core 11 (3 in the present embodiment). Therefore, the arbitration circuit 4 accepts a processing request from the core 11 (requires acceptance of the request acceptance A1). reference). Thereby, the request acceptance number of the core 11 is set to 1 (see the request acceptance number N1).

  Next, it is assumed that the core 12 issues a processing request (see processing request R2). Since the request acceptance number of the core 12 at this time is 0 and smaller than the acceptance upper limit value of the core 12 (2 in the present embodiment), the arbitration circuit 4 accepts the processing request from the core 12 (request acceptance A2 is set). reference). Thereby, the request acceptance number of the core 12 is set to 1 (see the request acceptance number N2).

  Next, it is assumed that the core 13 issues a processing request (see processing request R3). Since the request acceptance number of the core 13 at this time is 0 and smaller than the acceptance upper limit value of the core 13 (1 in the present embodiment), the arbitration circuit 4 accepts a processing request from the core 13 (requires acceptance of the request acceptance A3). reference). Thereby, the request acceptance number of the core 13 is set to 1 (refer to the request acceptance number N3).

  Next, it is assumed that the core 11 and the core 12 issue processing requests simultaneously (see processing requests R4 and R5). In this case, since the priority of the core 11 (1 in the present embodiment) is higher than the priority of the core 12 (2 in the present embodiment), the arbitration circuit 4 accepts a processing request from the core 11 (request acceptance). A processing request from the core 12 is suspended (see request suspension H5). Thereby, the request acceptance number of the core 11 is set to 2 (refer to the request acceptance number N4).

  Then, after the functional unit 21 of the reconfigurable device 3 outputs the processing result corresponding to the processing request of the core 11, the arbitration circuit 4 receives the pending processing request (see request acceptance A5). Since the pending processing request is a processing request from the core 12, the request acceptance number of the core 12 is set to 2 (see the request acceptance number N5).

  Next, it is assumed that the core 13 issues a processing request (see processing request R6). Since the number of requests accepted by the core 13 at this time is 1 and equal to the acceptance upper limit value of the core 13, the arbitration circuit 4 holds the processing request from the core 13 (see request holding H6).

  Thereafter, it is assumed that the core 11 issues a processing request (see processing request R7). At this time, the number of requests accepted by the core 11 is 7, which is smaller than the acceptance upper limit value of the core 11 (3 in the present embodiment), so the arbitration circuit 4 accepts a processing request from the core 11 (requires the request acceptance A7). reference). Thereby, the request acceptance number of the core 11 is set to 3 (refer to the request acceptance number N7).

  Then, when the arbitration unit period elapses, the request acceptance numbers of the cores 11, 12, and 13 are reset (see reset RS), and the next arbitration unit period is started. As a result, the arbitration circuit 4 accepts the pending processing request (see request acceptance A6). Since the pending processing request is a processing request from the core 13, the request acceptance number of the core 13 is set to 1 (see the request acceptance number N6).

  In the microcomputer 1 configured as described above, the reconfigurable device 3 is configured to be able to execute processing corresponding to a processing request issued from the core 11 (hereinafter referred to as a first processing request). 21, a functional unit 22 configured to execute processing corresponding to a processing request issued from the core 12 (hereinafter referred to as a second processing request), and a processing request issued from the core 13 (hereinafter referred to as “second processing request”). And a functional unit 23 configured to be able to execute processing corresponding to the third processing request).

  In addition, the microcomputer 1 accepts an upper limit of acceptance (hereinafter referred to as a first acceptance upper limit) indicating the upper limit of the number of times that the function unit 21 executes processing corresponding to the first processing request within a preset arbitration unit period that is repeated at regular intervals. Value), an acceptance upper limit value indicating the upper limit of the number of times the function unit 22 executes processing corresponding to the second processing request within the arbitration unit period (hereinafter referred to as the second acceptance upper limit value), and within the arbitration unit period. Based on the acceptance upper limit value (hereinafter referred to as the third acceptance upper limit value) indicating the upper limit of the number of times the function unit 23 executes the process corresponding to the third process request, the function unit 21 performs the process corresponding to the first process request. An arbitration function that determines whether the function unit 22 executes the process corresponding to the second process request, and whether the function unit 23 executes the process corresponding to the third process request. Hardware Comprising an arbitration circuit 4 constituted.

  As described above, the microcomputer 1 can limit the number of times the functional unit 21 executes the process corresponding to the first process request within the arbitration unit period to the first reception upper limit value or less. Similarly, the microcomputer 1 can limit the number of times the function units 22 and 23 execute processing corresponding to the second and third processing requests within the arbitration unit period to a value equal to or less than the value indicated by the second and third acceptance upper limit values. .

  Therefore, as shown in FIG. 5, the first processing request from the core 11 (see the arrow AL1 in FIG. 5) rather than the second and third processing requests from the cores 12 and 13 (see the arrows AL2 and AL3 in FIG. 5). Even if a large number of references) are issued, the portion exceeding the first acceptance upper limit value is not executed by the function unit 21, and the portion corresponding to the second and third processing requests corresponding to the portion where the processing of the function unit 21 is not executed Can be assigned to. Further, even if the second processing request is frequently issued, the portion exceeding the second acceptance upper limit value is not executed by the function unit 22, and the portion that the processing of the function unit 22 is not executed is determined as the first and third processing. Can be assigned to processing corresponding to the request.

  And the restriction | limiting of the frequency | count which the function parts 21, 22, and 23 perform is performed for every arbitration unit period. For this reason, the shorter the arbitration unit period, the shorter the period during which the processing corresponding to the second and third processing requests cannot be executed when the first processing requests are issued frequently. The first processing request exceeding the first acceptance upper limit value within the arbitration unit period is not executed by the functional unit 21, and can be assigned to the processing corresponding to the second and third processing requests within the arbitration unit period. It is. Similarly, the shorter the arbitration unit period, the shorter the period during which the processing corresponding to the first and third processing requests cannot be executed when the second processing request is issued frequently.

As described above, the microcomputer 1 can suppress the occurrence of a situation in which a process corresponding to another process request cannot be executed due to a certain process request being issued frequently.
In the arbitration circuit 4, the number of times (first request acceptance number) determined to cause the function unit 21 to execute the process corresponding to the first process request within the arbitration unit period, and the second process request within the arbitration unit period. The number of times determined to cause the function unit 22 to execute the process (second request acceptance number) and the number of times determined to cause the function unit 23 to execute the process corresponding to the third process request within the arbitration unit period (third request) (Acceptance number) (S60, S120, S190, S210, S220). Further, in the arbitration circuit 4, the function unit 21 is caused to execute processing corresponding to the first processing request by preventing the first, second, and third request acceptance numbers from exceeding the first, second, and third acceptance upper limit values. No, whether to make the function unit 22 execute the process corresponding to the second process request, and whether to make the function part 23 execute the process corresponding to the third process request (S30, S40, S100). , S150, S170). Further, the arbitration circuit 4 holds the first, second, and third processing requests that exceed the first, second, and third acceptance upper limit values during the arbitration unit period (S90). Further, in the arbitration circuit 4, when the first, second, and third processing requests for the first, second, and third acceptance upper limit values are held within the arbitration unit period, the first, second, and third processings are suspended. After the arbitration unit period in which the request is suspended has elapsed, it is determined whether to execute the suspended first, second, and third processing requests based on the first, second, and third acceptance upper limit values (S150 to S170). ).

  As described above, the first, second, and third processing requests that are suspended due to exceeding the acceptance upper limit value are executed after the arbitration unit period has elapsed. Thereby, as will be described below, the worst execution time of the cores 11, 12, and 13 can be easily estimated.

  The worst execution time of the cores 11, 12, and 13 receives the processing result corresponding to the processing request from the reconfigurable device 3 through the arbitration circuit 4 after the cores 11, 12, and 13 issue the processing request. This is the maximum value of the time required to complete the process. Specifically, as shown in FIG. 6, the worst execution time of the cores 11, 12, and 13 is the sum of the worst communication time, the worst arbitration time, and the worst IO processing time. The worst communication time is the maximum time required for the cores 11, 12, and 13 to perform data communication with the arbitration circuit 4. The worst arbitration time is the maximum value of time required for the arbitration circuit 4 to arbitrate processing requests from the cores 11, 12, and 13. The worst IO processing time is the maximum value of the time required from when the arbitration circuit 4 outputs a processing request until the processing result is input from the reconfigurable device 3.

  The worst arbitration time is the sum of the arbitration unit period and the worst IO processing time by another core. For example, when the processing request of the core 12 is held at the initial stage in the arbitration unit period and the processing request of the core 11 is accepted immediately before the end of the arbitration unit period, even if the next arbitration unit period is started, Until the processing corresponding to the processing request of the core 11 accepted in the previous arbitration unit period is completed, the processing corresponding to the processing request of the core 12 suspended in the previous arbitration unit period cannot be executed. For this reason, the worst arbitration time of the core 12 can be, for example, the sum of the arbitration unit period and the worst IO processing time of the core 11.

  Thus, since the worst arbitration time of the cores 11, 12, and 13 can be the sum of the arbitration unit period and the worst IO processing time by other cores, the worst execution time of the cores 11, 12, and 13 can be reduced. Can be easily estimated.

  In addition, in the arbitration circuit 4, when at least two of the first processing request, the second processing request, and the third processing request are held, the holding timings are held in order based on the holding timing. Which of the first, second, and third processing requests is to be executed first is determined (S150). Thereby, it is possible to cause the reconfigurable device 3 to process the pending processing requests in the order in which the processing requests are issued.

  Further, in the arbitration circuit 4, when at least two of the first processing request, the second processing request, and the third processing request are issued simultaneously, the arbitration circuit 4 is based on the priority set in advance for the first, second, and third processing requests. Which of the first, second, and third processing requests is prioritized is determined (S100). Thereby, it is possible to cause the reconfigurable device 3 to preferentially execute processing with high priority. For example, as shown in FIG. 7, when the first processing request from the core 11 (see arrow AL11 in FIG. 7) and the second processing request from the core 12 (see arrow AL12 in FIG. 7) are issued simultaneously. The reconfigurable device 3 executes the process corresponding to the first process request with priority over the process corresponding to the second process request.

  In the embodiment described above, the core 11 is the first request source in the present invention, the core 12 is the second request source in the present invention, the function unit 21 is the first process execution unit in the present invention, and the function unit 22 is the first request source in the present invention. 2 processing execution part, the 1st acceptance upper limit is the 1st upper limit information in the present invention, and the 2nd acceptance upper limit is the 2nd upper limit information in the present invention.

  The processing of S60, S120, S190, S210, and S220 is counting means in the present invention, the processing of S30, S40, S100, and S150 to S170 is execution determining means in the present invention, and the processing of S90 is holding means in the present invention. One request acceptance number is the first process decision number in the present invention, and the second request acceptance number is the second process decision number in the present invention.

As mentioned above, although one Embodiment of this invention was described, this invention is not limited to the said embodiment, As long as it belongs to the technical scope of this invention, a various form can be taken.
For example, in the above embodiment, the reconfigurable device 3 is an FPGA. However, the present invention is not limited to this. For example, the reconfigurable device 3 may be a CPLD (Complex Programmable Logic Device).

  In the above-described embodiment, the second selection condition is the order in which processing requests are issued and the third selection condition is priority. However, the second selection condition is priority and the third selection condition is the processing request. You may make it be an issue order.

  Moreover, in the said embodiment, although what stored the data for arbitration in the data storage part 24 of the reconfigurable device 3 was shown, storage of the data for arbitration is not limited to the reconfigurable device 3, For example, The arbitration data may be stored in a register or memory mounted on the microcomputer 1.

  In the above embodiment, the arbitration data stored in the data storage unit 24 sets the priority of the processing request. However, the arbitration circuit 4 seems to set the priority of the processing request in advance. It may be. For example, the arbitration circuit 4 may be set in advance so that the priority of processing requests from the cores 11, 12, and 13 are 1, 2, and 3, respectively. That is, the processing to be executed by the cores 11, 12, and 13 may be determined based on the priority set in the arbitration circuit 4.

  DESCRIPTION OF SYMBOLS 1 ... Microcomputer, 3 ... Reconfigurable device, 4 ... Arbitration circuit, 11, 12, 13 ... Core, 21, 22, 23 ... Functional part

Claims (4)

A microcomputer (1) equipped with a reconfigurable device (3),
The reconfigurable device is
One request source among a plurality of request sources that issue processing requests to the reconfigurable device is a first request source, and one of the plurality of request sources that is different from the first request source A first process execution unit (21) configured to execute a process corresponding to a first process request issued from the first request source, using the request source as a second request source, and the second request A second process execution unit (22) configured to execute a process corresponding to the second process request issued from the source,
The microcomputer is
First upper limit information, which is information indicating an upper limit of the number of times the first process execution unit executes a process corresponding to the first process request within a preset arbitration unit period that is repeated at regular intervals; and the arbitration Based on the second upper limit information, which is information indicating the upper limit of the number of times the second process execution unit executes the process corresponding to the second process request within the unit period, the process corresponding to the first process request is performed. An arbitration function for determining whether or not to cause the first process execution unit to execute and to determine whether or not to cause the second process execution unit to execute a process corresponding to the second process request is configured by hardware. A microcomputer comprising the arbitration circuit (4). The arbitration circuit is:
A first process decision number, which is the number of times that the first process execution unit has decided to execute the process corresponding to the first process request within the arbitration unit period, and the second process request within the arbitration unit period. Counting means (S60, S120, S190, S210, S220) for counting the second process determination number, which is the number of times determined to cause the second process execution unit to execute the corresponding process;
The first process decision number does not exceed the number of times indicated by the first upper limit information, and the second process decision number does not exceed the number of times indicated by the second upper limit information. Execution to determine whether or not to cause the first process execution unit to execute a process corresponding to the process request, and to determine whether or not to cause the second process execution unit to execute a process corresponding to the second process request Determining means (S30, S40, S100, S150 to S170);
The first processing request that exceeds the number indicated by the first upper limit information within the arbitration unit period and the second processing request that exceeds the number indicated by the second upper limit information within the arbitration unit period Holding means (S90) for holding at least
The execution determining means is the number indicated by the second upper limit information within the first processing request and the arbitration unit period for the amount exceeding the number indicated by the first upper limit information within the arbitration unit period by the holding means. When at least one of the second processing requests exceeding the amount is held, after the arbitration unit period in which the holding means holds the first processing request and the second processing request has elapsed, Based on the first upper limit information and the second upper limit information, the first processing request and the hold for the number exceeding the number indicated by the first upper limit information within the arbitration unit period for which the hold has been performed are performed. In addition, it is determined whether or not to execute processing corresponding to the processing request for the second processing request that exceeds the number indicated by the second upper limit information within the arbitration unit period. 1. The microcomputer according to 1. Pewter. The execution determining means is
When both the first processing request and the second processing request are held by the holding means, the priority set in advance for each of the first processing request and the second processing request, or the holding means Deciding which of the first processing request and the second processing request held by the holding means to execute the processing corresponding to the processing request first based on the timing held by The microcomputer according to claim 2, characterized in that: The arbitration circuit is:
When the first processing request from the first request source and the second processing request from the second request source are issued simultaneously, the first processing request and the second processing request are set in advance. The microcomputer according to any one of claims 1 to 3, wherein which of the first processing request and the second processing request is to be prioritized is determined based on the priority that has been set. .

Images