CN116795490A - vCPU scheduling method, device, equipment and storage medium - Google Patents

Abstract

The embodiment of the invention provides a vCPU scheduling method, device, equipment and storage medium, which are used for scheduling vCPU of a type1 virtual machine, wherein the method comprises the following steps: configuring the vCPU of the first virtual machine as a master vCPU and the vccpus of other virtual machines as slave vcpus; when any virtual machine is trapped into the hypervisor due to idle, the current vCPU of the virtual machine is moved out of a dispatching queue of a physical CPU core of the virtual machine; when the current vCPU is the main vCPU, the current vCPU is scheduled when the next time of the scheduling timer of the current vCPU expires; when the current vCPU is the slave vCPU, the current vCPU is added to the scheduling queue on the physical CPU core when its scheduling timer next expires. According to the technical scheme provided by the embodiment of the invention, the master vCPU runs other vCPUs when the master vCPU is idle, so that the running time of the master vCPU is ensured, and the real-time performance of the corresponding virtual machine is improved.

Description

vCPU scheduling method, device, equipment and storage medium

Technical Field

The scheme belongs to the field of computer operating systems, and particularly relates to a vCPU scheduling method, device, equipment and storage medium.

Background

At present, in the Type1 virtualization scheme, dynamic scheduling of the vCPU of the virtual machine is already supported, but the dynamic scheduling method is basically based on time slice polling, that is, when a single physical CPU core schedules a plurality of vccpus, each vCPU is allocated to have the same fixed scheduling time slice, when the vCPU consumes the own time slice, the vCPU is switched to the next vCPU to operate, although the method can schedule a plurality of vccpus, the operation time of the vCPU corresponding to a certain host virtual machine cannot be ensured, so that when the vCPU corresponding to the host virtual machine needs to obtain operation, other vccpus are operated, and the operation cannot be obtained, thereby reducing the real-time performance of the host virtual machine.

Disclosure of Invention

In view of this, an embodiment of the present invention provides a vCPU scheduling method, apparatus, device, and storage medium, where the vCPU scheduling method is used to schedule a vCPU of a type1 virtual machine, and the method includes: configuring the vCPU of the first virtual machine as a master vCPU, configuring the vCPUs of other virtual machines as slave vCPUs, wherein each physical CPU core of the master vCPU is at least in one physical CPU core corresponding to the slave vCPU; when any virtual machine is trapped into the hypervisor due to idle, the current vCPU of the virtual machine is moved out of a dispatching queue of a physical CPU core of the virtual machine; when the current vCPU is the main vCPU, the current vCPU is scheduled when the next time of the scheduling timer of the current vCPU expires; when the current vCPU is the slave vCPU, the current vCPU is added to the scheduling queue on the physical CPU core after the next expiration of the scheduling timer of the current vCPU. According to the technical scheme provided by the embodiment of the invention, the master vCPU runs other vCPUs when the master vCPU is idle, so that the running time of the master vCPU is ensured, and the real-time performance of the corresponding virtual machine is improved.

In a first aspect, an embodiment of the present invention provides a vCPU scheduling method, configured to schedule a vCPU of a type1 virtual machine, including: configuring the vCPU of the first virtual machine as a master vCPU, configuring the vCPUs of other virtual machines as slave vCPUs, wherein each physical CPU core of the master vCPU is at least in one physical CPU core corresponding to the slave vCPU; when any virtual machine is trapped into the hypervisor due to idle, the current vCPU of the virtual machine is moved out of a dispatching queue of a physical CPU core of the virtual machine; when the current vCPU is the main vCPU, the current vCPU is scheduled when the next time of the scheduling timer of the current vCPU expires; when the current vCPU is the slave vCPU, the current vCPU is added to the scheduling queue on the physical CPU core when its scheduling timer next expires.

By setting the master-slave relationship of the vCPUs, the master vCPU always operates when the master vCPU is not idle, the master vCPU is scheduled when the scheduling timer of the master vCPU expires, the slave vCPU is added into the scheduling queue to schedule according to the queue when the master vCPU is idle and the scheduling timer of the slave vCPU expires, so that the running time of the master vCPU is ensured, and the real-time performance of the corresponding virtual machine is improved.

In one possible implementation manner of the first aspect, when the current vCPU is the master vCPU, the current vCPU is moved out of the scheduling queue of its physical CPU core and then the next slave vCPU in the scheduling queue of its physical CPU core is scheduled.

By the above, the slave vCPU is scheduled when the master vCPU is idle by the above method.

In a possible implementation manner of the first aspect, when the current vCPU is a slave vCPU, after the current vCPU is shifted out of the scheduling queue of the physical CPU core, the physical CPU core schedules the next slave vCPU when the scheduling queue of the physical CPU core exists in the next slave vCPU, and otherwise, the physical CPU core enters an idle state.

By the method, the slave vCPUs are scheduled according to the scheduling queue when the master vCPU is idle.

In a possible implementation manner of the first aspect, the scheduling the current vCPU when the next expiration of the scheduling timer of the current vCPU specifically includes: the current vCPU is scheduled by a temporal event of the hypervisor when its schedule timer next expires.

From above, the master vCPU is scheduled in time by the hypervisor's time event when the master vCPU's schedule timer next expires.

In a possible implementation manner of the first aspect, the adding the current vCPU to the scheduling queue on the physical CPU core when the next expiration of the scheduling timer of the current vCPU specifically includes: and adding the current vCPU scheduling timer to the scheduling queue on the physical CPU core when the next expiration of the current vCPU scheduling timer through the hypervisor timeout queue.

By the above, the slave CPU is added to the scheduling queue on the physical CPU core by the hypervisor timeout queue when the next expiration of the slave CPU's scheduling timer, and the slave CPU is scheduled according to the scheduling queue when the master vCPU is idle.

In one possible implementation manner of the first aspect, when any virtual machine is trapped into the hypervisor due to idle, the method specifically includes: when any virtual machine is idle, its idle thread is trapped into the hypervisor by running WFI instructions.

Therefore, any virtual machine is trapped into the hypervisor because of being idle, the hypervisor is not trapped when not being idle, and the main vCPU always runs when not being idle, so that the instantaneity of the virtual machine is ensured.

In a second aspect, an embodiment of the present invention provides a vCPU scheduling apparatus, configured to schedule vCPU of a type1 virtual machine, including: the configuration module is used for configuring the vCPU of the first virtual machine as a master vCPU, configuring the vCPUs of other virtual machines as slave vCPUs, and at least one slave vCPU corresponds to each physical CPU core of the master vCPU; the idle module is used for moving the current vCPU of any virtual machine out of a dispatching queue of a physical CPU core of the virtual machine when any virtual machine is trapped into the hypervisor because of idle; the main vCPU scheduling module is used for scheduling the current vCPU when the scheduling timer of the current vCPU is expired next when the current vCPU is the main vCPU; the slave vCPU scheduling module is used for adding the current vCPU to a scheduling queue on the physical CPU core when the scheduling timer of the current vCPU expires next time when the current vCPU is the slave vCPU.

By setting the master-slave relationship of the vCPUs, the master vCPU always operates when the master vCPU is not idle, the master vCPU is scheduled when the scheduling timer of the master vCPU expires, the slave vCPU is added into the scheduling queue to schedule according to the queue when the master vCPU is idle and the scheduling timer of the slave vCPU expires, so that the running time of the master vCPU is ensured, and the real-time performance of the corresponding virtual machine is improved.

In one possible implementation manner of the second aspect, the master vCPU scheduling module is further specifically configured to, when the current vCPU is the master vCPU, shift the current vCPU out of the scheduling queue of the physical CPU core and schedule the next slave vCPU in the scheduling queue of the physical CPU core.

By the above, the slave vCPU is scheduled when the master vCPU is idle by the above device.

In a possible implementation manner of the second aspect, the slave vCPU scheduling module is further specifically configured to, when the current vCPU is a slave vCPU, schedule a next slave vCPU when the next slave vCPU exists in the scheduling queue of the physical CPU core after the current vCPU is moved out of the scheduling queue of the physical CPU core, and otherwise, enter the idle state.

By the device, the slave vCPUs are scheduled according to the scheduling queue when the master vCPU is idle.

In a possible implementation manner of the second aspect, the main vCPU scheduling module schedules the current vCPU when a scheduling timer of the current vCPU expires next, specifically includes: the current vCPU is scheduled by a temporal event of the hypervisor when its schedule timer next expires.

From above, the master vCPU is scheduled in time by the hypervisor's time event when the master vCPU's schedule timer next expires.

In one possible implementation manner of the second aspect, the slave vCPU scheduling module adds the current vCPU to the scheduling queue on the physical CPU core when the scheduling timer of the current vCPU expires next, specifically including: and adding the current vCPU scheduling timer to the scheduling queue on the physical CPU core when the next expiration of the current vCPU scheduling timer through the hypervisor timeout queue.

From above, it is added to the dispatch queue on the physical CPU core by the hypervisor timeout queue upon the next expiration of the slave's dispatch timer.

In a possible implementation manner of the second aspect, the idle module is specifically configured to trap an idle thread into a hypervisor by running a WFI instruction when any virtual machine is idle.

Therefore, any virtual machine is trapped into the hypervisor because of being idle, the hypervisor is not trapped when not being idle, and the main vCPU always runs when not being idle, so that the instantaneity of the virtual machine is ensured.

In a third aspect, embodiments of the present invention provide an operating system, which when executed by a computer, causes the computer to perform any of the methods of the first aspect.

In a fourth aspect, embodiments of the present invention provide a computing device comprising: a bus; a communication interface connected to the bus; at least one processor coupled to the bus; and at least one memory coupled to the bus and storing program instructions that, when executed by the at least one processor, cause the at least one processor to perform any of the embodiments of the first aspect of the invention.

In a fifth aspect, embodiments of the present invention provide a computer readable storage medium having stored thereon program instructions which when executed by a computer cause the computer to perform any of the embodiments of the first aspect of the present invention.

Drawings

FIG. 1 is a flow chart of a vCPU scheduling method according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating a relationship between a physical CPU and a vCPU in a second embodiment of a vCPU scheduling method according to the present invention;

FIG. 3 is a flow chart of a second embodiment of a vCPU scheduling method according to the present invention;

FIG. 4 is a schematic diagram of an embodiment of a vCPU scheduler according to the present invention;

FIG. 5 is a schematic diagram of a computing device according to embodiments of the invention.

Detailed Description

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

In the following description, references to the terms "first/second/third, etc." or module a, module B, module C, etc. are used merely to distinguish between similar objects or between different embodiments, and do not represent a particular ordering of the objects, it being understood that particular orders or precedence may be interchanged as permitted so that embodiments of the invention described herein can be implemented in an order other than that illustrated or described herein.

In the following description, reference numerals indicating steps such as S110, S120, … …, etc. do not necessarily indicate that the steps are performed in this order, and the order of the steps may be interchanged or performed simultaneously as allowed.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein is for the purpose of describing embodiments of the invention only and is not intended to be limiting of the invention.

The embodiment of the invention provides a vCPU scheduling method, device, equipment and storage medium, which are used for scheduling vCPU of a type1 virtual machine, wherein the method comprises the following steps: configuring the vCPU of the first virtual machine as a master vCPU, configuring the vCPUs of other virtual machines as slave vCPUs, wherein each physical CPU core of the master vCPU is at least in one physical CPU core corresponding to the slave vCPU; when any virtual machine is trapped into the hypervisor due to idle, the current vCPU of the virtual machine is moved out of a dispatching queue of a physical CPU core of the virtual machine; when the current vCPU is the main vCPU, the current vCPU is scheduled when the next time of the scheduling timer of the current vCPU expires; when the current vCPU is the slave vCPU, the current vCPU is added to the scheduling queue on the physical CPU core when its scheduling timer next expires. According to the technical scheme provided by the embodiment of the invention, the master vCPU runs other vCPUs when the master vCPU is idle, so that the running time of the master vCPU is ensured, and the real-time performance of the corresponding virtual machine is improved.

First, a use scenario of an embodiment of the present invention is described, where the embodiment of the present invention is used for scheduling vCPU of a type1 virtual machine. the Hypervisor of the type1 virtual machine is directly built on a hardware bare machine, and runs each virtual machine on the hardware bare machine, wherein one virtual machine is a main virtual machine (a first virtual machine in each embodiment) and needs higher real-time performance.

Embodiments of the present invention are described below with reference to the accompanying drawings.

First, a first embodiment of a vCPU scheduling method according to the present invention will be described with reference to fig. 1.

Fig. 1 shows a flow of a vCPU scheduling method embodiment one, including steps S110 to S150.

S110: the vCPU of the first virtual machine is configured as a master vCPU, and the vCPUs of other virtual machines are configured as slave vCPUs, wherein each physical CPU core of the master vCPU is at least in a corresponding physical CPU core of one slave vCPU.

The first virtual machine is a virtual machine with high real-time requirements, and the corresponding vCPU needs to be scheduled in time so as to improve the real-time performance of the first virtual machine.

S120: when any virtual machine gets trapped in the hypervisor because of idle, the current vCPU of that virtual machine is moved out of its physical CPU core's dispatch queue.

Wherein the current vCPU of the virtual machine is moved out of its physical CPU core's dispatch queue, i.e., the vCPU's dispatch is stopped.

It should be noted that, when the virtual machine of the main vCPU is not idle in the present invention, the main vCPU runs all the time and does not sink into the hypervisor to reschedule. When the virtual machine of the slave vCPU is not idle and is not preempted by the master virtual machine, the slave vCPU is scheduled according to the scheduling queue, and is not actively trapped into the hypervisor to be rescheduled, but the physical CPU core running from the slave vCPU is preempted by the master CPU, so that the slave vCPU pauses running.

It should be noted that, in the present invention, each vCPU has a scheduling Timer (Timer), which is different from the conventional time polling scheduling period, and is generally smaller than the conventional time polling scheduling period, and is set according to the real-time requirement of the virtual machine corresponding to the vCPU, where the size of the virtual machine is reversely set according to the real-time requirement of the corresponding virtual machine, the real-time requirement of the first virtual machine is high, and the scheduling Timer period of the vCPU is short. The hypervisor will trigger some schedule related events for the corresponding vCPU after the schedule timer expires. The time at which the current vCPU's schedule timer next expires is also obtained in some embodiments.

In some embodiments, in a virtual machine using an ARM architecture CPU, WFI instructions are run by idle threads of its operating system while the virtual machine is idle to be trapped in the hypervisor.

S130: it is determined whether the current vCPU is the master vCPU. If yes, step S140 is run, otherwise step S150 is run.

S140: when the current vCPU is the master vCPU, the current vCPU is scheduled when the current vCPU's schedule timer next expires.

The scheduling timer of the present invention does not exist in the existing polling scheduling method, the next expiration time of the scheduling timer of the current vCPU cannot be obtained, and the current vCPU is not necessarily scheduled, i.e. the main vCPU is not necessarily scheduled, at the time corresponding to the next expiration time of the scheduling timer of the current vCPU. The invention affirmatively schedules the main vCPU when the next expiration of the scheduling timer of the main vCPU, thereby scheduling the main vCPU in real time when the first virtual machine needs to run.

In some embodiments, in the event that the next expiration of the vCPU's schedule timer is added in the Hypervisor's time event, the current vCPU is scheduled by the time event trigger when the current vCPU's schedule timer next expires.

In some embodiments, the next vCPU in the scheduling queue on the corresponding physical CPU core of the current vCPU is also scheduled in this step before the next expiration of the master vCPU's scheduling timer.

By the method, when the current vCPU is the main vCPU, the current vCPU is scheduled when the next schedule timer of the current vCPU expires, the main vCPU does not need to wait for scheduling according to a traditional time polling scheduling period, so that the main vCPU is scheduled in real time, and simultaneously, the main vCPU always operates if not idle after being scheduled, also does not need to operate at intervals according to the traditional time polling scheduling period, and the instantaneity of the corresponding first virtual machine is improved.

S150: when the current vCPU is the slave vCPU, the current vCPU is added to the scheduling queue on the physical CPU core after the next scheduled time of the current vCPU expires.

When the next expiration of the slave vCPU schedule timer, the slave vCPU is added into a schedule queue on the physical CPU core, and if the corresponding master vCPU on the physical CPU core is running at the moment, the master vCPU always runs, and the slave vCPU is certainly not scheduled; and if the corresponding master vCPU on the physical CPU core is not running at the moment, scheduling according to the position of the slave vCPU in a scheduling queue.

In some embodiments, the timeout queue of the Hypervisor is added with the next expired timeout event of the current vCPU's schedule timer, which adds the current vCPU to the schedule queue on the physical CPU core for scheduling in accordance with the schedule queue.

In some embodiments, the next slave vCPU is scheduled in this step when the physical CPU core's scheduling queue exists for the next slave vCPU before the slave vCPU's scheduling timer expires next, otherwise the physical CPU core enters an idle state.

When the current vCPU is the slave vCPU, the current vCPU is added into a scheduling queue on the physical CPU core when the next scheduling timer of the current vCPU expires, so that the slave vCPU is scheduled according to the scheduling queue when the master vCPU is not busy, and the scheduling implementation property of the master vCPU is improved.

In summary, a master-slave relationship of the vCPU is set in the embodiment of the vCPU scheduling method, different processes are performed on the master-slave vCPU, the master vCPU operates all the time when the master vCPU is not idle, the slave vCPU is scheduled when the master vCPU is idle and the master vCPU is scheduled when the scheduling timer expires, the slave vCPU is added into the scheduling queue to schedule according to the queue when the slave vCPU is idle and the scheduling timer expires, so that the running time of the master vCPU is ensured, and the real-time performance of the corresponding virtual machine is improved.

A second embodiment of a vCPU scheduling method according to the present invention is described below with reference to fig. 2 and 3.

The second embodiment of the vCPU scheduling method is an implementation of the first embodiment of the vCPU scheduling method in a specific scenario, and has all the advantages of the first embodiment of the vCPU scheduling method.

The second usage scenario of the vCPU scheduling method embodiment is a scenario in which the physical CPU of the ARM architecture is subjected to the tyrp 1 virtualization.

Fig. 2 shows a relationship between a physical CPU and vCPU in a second embodiment of a vCPU scheduling method, where the physical CPU has 4 physical CPU cores, that is, CPU0, CPU1, CPU2, and CPU3, respectively, the first virtual machine has vCPU10, vCPU10 is a main vCPU, and runs on CPU0, and the second virtual machine has 4 vccpus, that is, vCPU20, vCPU21, vCPU22, and vCPU23, that are slave vcpus, that run on CPU0, CPU1, CPU2, and CPU3, respectively, and that will run two vccpus on CPU 0.

Fig. 3 shows a flow of a vCPU scheduling method embodiment two, including steps S210 to S280.

S210: the vCPU10 of the first virtual machine is configured as a master vCPU and each vCPU of the second virtual machine is configured as a slave vCPU.

S220: when any virtual machine is idle, its idle thread runs WFI instructions trapped in the hypervisor.

S230: in hypervisor, the current vCPU is moved out of its physical CPU core's dispatch queue at the WFI trap and the next expiration time of its dispatch timer is obtained.

S240: it is determined whether the current vCPU is the master vCPU10. If yes, step S250 is run, otherwise step S270 is run.

Wherein, the vCPU10 is the main vCPU, and whether the current vCPU is the vCPU10 or not is judged, or whether the current vCPU is the main vCPU or not is judged.

S250: adding the next expired time event of the schedule timer of vCPU10 in the hypervisor time event and scheduling the next slave vCPU in the schedule queue of CPU 0.

Wherein the time event is to schedule the vCPU10 when the next expiration of the schedule timer of the vCPU10, and the vCPU10 is the master vCPU, that is, the master vCPU is scheduled when the next expiration of the schedule timer of the master vCPU, so that the master vCPU is scheduled in time.

Wherein, because the slave vCPU on CPU0 is vCPU20, the next slave vCPU in the scheduling queue of the scheduling CPU0, i.e., the scheduling vCPU20 (slave vCPU) when the vCPU10 (master vCPU) is idle.

S260: the vCPU10 is scheduled at CPU0 upon the next expiration of the vCPU 10's schedule timer.

S270: and adding a timeout event of the next expiration of the scheduling timer of the current vCPU in a hypervisor timeout queue, and entering an idle state.

Wherein the timeout event adds the current vCPU to the dispatch queue upon a next expiration of the current vCPU's dispatch timer.

The present step is executed no matter whether the current vCPU is the vCPU20, the vCPU21, the vCPU22 or the vCPU23, and slave vcpus of the CPUs 0, 1, 2 and 3 correspond to the vCPU20, 21, 22 and 23 respectively, that is, only one slave vCPU enters an idle state before the next expiration of the schedule timer of the current vCPU.

S280: adding the current vCPU to a dispatch queue upon a next expiration of the current vCPU's dispatch timer

Wherein, if the current vCPU is the slave vCPU20, running on the CPU0, when the next expiration of the scheduling timer of the slave vCPU, if at this time the CPU0 runs the vCPU10, i.e. runs the master vCPU, the vCPU20 must not be scheduled, if at this time the vCPU10 is idle, the vCPU20 is scheduled according to the scheduling queue; if the current vCPU is other slave vCPUs and the physical CPU cores corresponding to the other slave vCPUs have no master vCPU, the current vCPU is scheduled according to a scheduling queue.

An embodiment of a vCPU scheduler of the present invention is described below in conjunction with fig. 4.

The embodiment of the vCPU scheduling device operates the method of the first embodiment of the vCPU scheduling method, and has all the advantages of the first embodiment of the vCPU scheduling method.

Fig. 4 shows that an embodiment of a vCPU scheduler includes: configuration module 410, idle module 420, master-slave determination module 430, master vCPU scheduling module 440, and slave vCPU scheduling module 450.

The configuration module 410 is configured to configure the vCPU of the first virtual machine as a master vCPU, and the vccpus of the other virtual machines as slave vccpus, where each physical CPU core of the master vCPU is at least in a corresponding physical CPU core of one slave vCPU. For specific principles and advantages, please refer to step S110 of a vCPU scheduling method according to an embodiment.

The idle module 420 is configured to, when any virtual machine is trapped in the hypervisor due to idle, move the current vCPU of the virtual machine out of the dispatch queue of its physical CPU core. For specific principles and advantages, please refer to step S120 of a vCPU scheduling method according to an embodiment.

The master-slave determination module 430 is configured to determine whether the current vCPU is a master vCPU. If so, the master vCPU scheduling module 440 is run, otherwise the slave vCPU scheduling module 450 is run. For specific principles and advantages, please refer to step S130 of a vCPU scheduling method according to an embodiment.

The primary vCPU scheduling module 440 is configured to schedule the current vCPU when the current vCPU is the primary vCPU and the scheduling timer of the current vCPU expires next. For specific principles and advantages, please refer to step S140 of a vCPU scheduling method according to an embodiment.

The slave vCPU scheduling module 450 is configured to add the current vCPU to the scheduling queue on the physical CPU core when the scheduling timer of the current vCPU expires next when the current vCPU is the slave vCPU. For specific principles and advantages, please refer to step S150 of a vCPU scheduling method embodiment one.

The embodiment of the invention also provides an operating system which is executed by a computer to enable the computer to execute the method of the first embodiment of the vCPU scheduling method or the second embodiment of the vCPU scheduling method.

An embodiment of the present invention further provides a computing device, which is described in detail in fig. 5 below.

The computing device 500 includes a processor 510, a memory 520, a communication interface 530, and a bus 540.

It should be appreciated that the communication interface 530 in the computing device 500 shown in this figure may be used to communicate with other devices.

Wherein the processor 510 may be coupled to a memory 520. The memory 520 may be used to store the program codes and data. Accordingly, the memory 520 may be a storage unit internal to the processor 510, an external storage unit independent of the processor 510, or a component including a storage unit internal to the processor 510 and an external storage unit independent of the processor 510.

Optionally, computing device 500 may also include a bus 540. The memory 520 and the communication interface 530 may be connected to the processor 510 via a bus 540. Bus 540 may be a peripheral component interconnect standard (Peripheral Component Interconnect, PCI) bus or an extended industry standard architecture (EFStended Industry Standard Architecture, EISA) bus, among others. The bus 540 may be classified as an address bus, a data bus, a control bus, or the like. For ease of illustration, only one line is shown in the figure, but not only one bus or one type of bus.

It should be appreciated that in embodiments of the present invention, the processor 510 may employ a central processing unit (central processing unit, CPU). The processor may also be other general purpose processors, digital signal processors (digital signal processor, DSP), application specific integrated circuits (application specific integrated circuit, ASIC), off-the-shelf programmable gate arrays (field programmable gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. Or the processor 510 may employ one or more integrated circuits for executing associated programs to carry out the techniques provided by embodiments of the present invention.

The memory 520 may include read only memory and random access memory, and provides instructions and data to the processor 510. A portion of the processor 510 may also include non-volatile random access memory. For example, processor 510 may also store information of the device type.

When the computing device 500 is running, the processor 510 executes computer-executable instructions in the memory 520 to perform the operational steps of the various method embodiments.

It should be understood that the computing device 500 according to the embodiments of the present invention may correspond to a respective subject performing the methods according to the embodiments of the present invention, and that the above and other operations and/or functions of the respective modules in the computing device 500 are respectively for implementing the respective flows of the methods according to the embodiments of the present method, and are not repeated herein for brevity.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the method embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the decoding method according to the embodiments of the present invention. The storage medium includes various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk.

The embodiments of the present invention also provide a computer-readable storage medium having stored thereon a computer program for performing the operational steps of the method embodiments when executed by a processor.

The computer storage media of embodiments of the invention may take the form of any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the above embodiments, but may include many other equivalent embodiments without departing from the spirit of the invention, which fall within the scope of the invention.

Claims (10)

1. A vCPU scheduling method, characterized by being used for scheduling a vCPU of a type1 virtual machine, comprising:

configuring the vCPU of the first virtual machine as a master vCPU, configuring the vCPUs of other virtual machines as slave vCPUs, wherein each physical CPU core of the master vCPU is at least in the physical CPU core corresponding to one slave vCPU;

when any virtual machine is trapped into the hypervisor due to idle, the current vCPU of the virtual machine is moved out of a dispatching queue of a physical CPU core of the virtual machine;

when the current vCPU is a main vCPU, the main vCPU is scheduled when the next time of the scheduling timer of the current vCPU expires;

when the current vCPU is the slave vCPU, the current vCPU is added to the scheduling queue on the physical CPU core when its scheduling timer next expires.

2. The method of claim 1, wherein when the current vCPU is the master vCPU, the current vCPU is moved out of its physical CPU core's dispatch queue and then the next slave vCPU in its physical CPU core's dispatch queue is dispatched.

3. The method of claim 1, wherein when the current vCPU is a slave vCPU, after the current vCPU is moved out of the scheduling queue of the physical CPU core, the physical CPU core is further scheduled when there is a next slave vCPU in the scheduling queue of the physical CPU core, and otherwise the physical CPU core enters an idle state.

4. The method according to claim 1, wherein said scheduling the current vCPU when the current vCPU's scheduling timer next expires, specifically comprises:

the current vCPU is scheduled by a temporal event of the hypervisor when its schedule timer next expires.

5. The method according to claim 2, wherein said adding the current vCPU's schedule timer to the schedule queue on the physical CPU core when it next expires, specifically comprises:

and adding the current vCPU scheduling timer to the scheduling queue on the physical CPU core when the next expiration of the current vCPU scheduling timer through the hypervisor timeout queue.

6. The method according to any one of claims 1 to 5, wherein when any one virtual machine gets involved in a hypervisor due to idle, the method specifically comprises:

when any virtual machine is idle, its idle thread is trapped into the hypervisor by running WFI instructions.

7. A vCPU scheduler for scheduling a type1 virtual machine, comprising:

the configuration module is used for configuring the vCPU of the first virtual machine as a master vCPU, configuring the vCPUs of other virtual machines as slave vCPUs, and at least one slave vCPU corresponds to each physical CPU core of the master vCPU;

the idle module is used for moving the current vCPU of any virtual machine out of a dispatching queue of a physical CPU core of the virtual machine when any virtual machine is trapped into the hypervisor because of idle;

the main vCPU scheduling module is used for scheduling the current vCPU when the scheduling timer of the current vCPU is expired next when the current vCPU is the main vCPU;

the slave vCPU scheduling module is used for adding the current vCPU to a scheduling queue on the physical CPU core when the scheduling timer of the current vCPU expires next time when the current vCPU is the slave vCPU.

8. An operating system which, when executed by a computer, causes the computer to perform the method of any of claims 1 to 6.

9. A computing device, comprising:

a bus;

a communication interface connected to the bus;

at least one processor coupled to the bus; and

at least one memory coupled to the bus and storing program instructions that, when executed by the at least one processor, cause the at least one processor to perform the method of any of claims 1 to 6.

10. A computer readable storage medium, characterized in that it has stored thereon program instructions, which when executed by a computer, cause the computer to perform the method of any of claims 1 to 6.