CN113918336A - FreeRTOS task running method and device based on multi-core CPU - Google Patents

FreeRTOS task running method and device based on multi-core CPU Download PDF

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CN113918336A
CN113918336A CN202111197347.6A CN202111197347A CN113918336A CN 113918336 A CN113918336 A CN 113918336A CN 202111197347 A CN202111197347 A CN 202111197347A CN 113918336 A CN113918336 A CN 113918336A
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task
core
target core
global
target
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张雷正
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Beijing Eswin Computing Technology Co Ltd
Haining Eswin IC Design Co Ltd
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Beijing Eswin Computing Technology Co Ltd
Haining Eswin IC Design Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5022—Mechanisms to release resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/48—Indexing scheme relating to G06F9/48
    • G06F2209/484—Precedence
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/50—Indexing scheme relating to G06F9/50
    • G06F2209/5021—Priority

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Abstract

The invention discloses a method and a device for running a task of a FreeRTOS (real-time operating system) based on a multi-core CPU (central processing unit), and relates to the technical field of embedded real-time operating systems, so that the FreeRTOS real-time operating system supports the multi-task running of the multi-core CPU. The main technical scheme of the invention is as follows: if the target core occupies the spin lock to access the global task ready list, determining a first task according to the priority of the tasks in the global task ready list and the core task ready list, wherein the tasks which are not bound with the cores are stored in the global task ready list, and each core has a core task ready list corresponding to the core and stores the tasks bound with the cores; the target core runs a first task and releases the spin lock; when the target core runs the first task, if other cores preempt the spin lock to access the global task ready list, the second task can be determined according to the priority of the tasks in the global task ready list and the core task ready list of the second task, and the second task is run.

Description

FreeRTOS task running method and device based on multi-core CPU
Technical Field
The invention relates to the technical field of embedded real-time operating systems, in particular to a method and a device for running tasks of a FreeRTOS (real-time operating system) based on a multi-core CPU (central processing unit).
Background
As a lightweight Operating System, the open source embedded Real Time Operating System (FreeRTOS) has functions including: task management, time management, semaphore, message queue, memory management, recording function, software timer, corotation and the like, and the FreeRTOS is adopted, so that the resources of a CPU can be more reasonably and effectively utilized, the design of application software is simplified, the development time of a system is shortened, and the real-time performance and the reliability of the system are better ensured.
Currently, the FreeRTOS can support CPUs in a variety of architectures, including the RiscV architecture. RiscV, RISC-V (the English pronunciation is "risk-five"), is a completely new instruction set architecture originally invented in 2010 by developers of the department of computer science, Krste Asanovic, Andrew Waterman and Yunsule, of the department of EECS, university of California, Berkeley, Inc. Where "RISC" represents the reduced instruction set and where "V" represents the fifth generation instruction set designed by Berkeley division from RISCI.
However, the existing FreeRTOS real-time operating system can only run on a single-core CPU, but does not support a multi-core CPU, and for example, for multiple created tasks, it cannot support true simultaneous running, so that the performance of the CPU cannot be fully exerted on the multi-core CPU.
Disclosure of Invention
In view of this, the present invention provides a method and an apparatus for running a task by a FreeRTOS based on a multicore CPU, and mainly aims to support simultaneous multi-task running when a FreeRTOS real-time operating system runs on the multicore CPU, so as to ensure that the multicore CPU fully exerts the performance of the CPU.
In order to achieve the above purpose, the present invention mainly provides the following technical solutions:
the first aspect of the application provides a FreeRTOS task running method based on a multi-core CPU, which comprises the following steps:
initializing and configuring a multi-core CPU, wherein the multi-core comprises a target core and at least one other core;
if the target core occupies the spin lock to access the global task ready list, the target core determines a first task according to the priority of the tasks in the global task ready list and the core task ready list of the target core, the global task ready list stores the tasks which are not bound with the cores, and each core has a corresponding core task ready list and is used for storing the tasks bound with the cores;
the target core runs the first task and releases the spin lock;
and when the target core runs the first task, if the other cores preempt the spin lock to access the global task ready list, the other cores determine a second task according to the priority of the tasks in the global task ready list and the core task ready list of the other cores and run the second task.
In some variations of the first aspect of the present application,
the target core determines a first task according to the priority of the tasks in the global task ready list and the core task ready list of the target core, and the method comprises the following steps: the target core
Comparing the tasks in the global task ready list with the tasks in the core task ready list, and determining the task with the highest task running priority as a first task;
the other cores determine a second task according to the priorities of the tasks in the global task ready list and the core task ready list of the other cores, and the method comprises the following steps: said other core
And comparing the tasks in the global task ready list with the tasks in the core task ready list to determine the task with the highest task running priority as a second task.
In some modified embodiments of the first aspect of the present application, the comparing the task in the global task-ready list with the task in the core task-ready list includes:
acquiring a first priority identification corresponding to a highest priority task in the global task ready list;
the target core or the other cores acquire a second priority identification corresponding to the task with the highest priority in the table from a core task ready table of the target core or the other cores;
and comparing the first priority identification with the second priority identification to obtain a higher priority identification, wherein the task corresponding to the higher priority identification is the task with the highest task running priority.
In some variations of the first aspect of the present application, while the target core is running the first task, the method further comprises:
if the time length of the target core waiting for the trigger message corresponding to the first task reaches a preset threshold value, adding the first task into a blocking list of the target core;
when the other core monitors the trigger message, the other core releases a semaphore to the target core, wherein the semaphore is used for informing the target core of releasing a blocked signal;
and if the first task does not have a binding relationship with the target core, the target core releases the first task from the blocking list and returns the first task to the global task ready list after acquiring the semaphore.
In some variations of the first aspect of the present application, if the first task is in a binding relationship with the target core, the method further includes:
after the target core acquires the semaphore, releasing the first task from the blocking list and adding the first task into a core task ready table of the target core;
the other cores transmit the trigger message to the target core and trigger an inter-core interrupt instruction, wherein the inter-core interrupt instruction is used for informing the target core of task switching;
according to the inter-core interrupt instruction, the target core acquires the first task from the core task ready table;
and according to the trigger message, the target core reruns the first task.
In some variations of the first aspect of the present application, the method further comprises:
when the target core receives a timed interrupt instruction, the target core stops running the current task;
and according to the timed interruption instruction, the target core executes task switching operation.
In some modified embodiments of the first aspect of the present application, the performing, by the target core, a task switching operation according to the timed interrupt instruction includes:
the target core acquires the authority of accessing the global task ready list by preempting the spin lock;
the target core compares the task in the global task ready list with the task in the core task ready list of the target core to determine a third task with the highest task running priority at present;
and the target core runs the third task and releases the spin lock.
A second aspect of the present application provides a FreeRTOS task running device based on a multicore CPU, the device including:
the system comprises a configuration unit, a processing unit and a control unit, wherein the configuration unit is used for initializing and configuring a multi-core CPU, and the multi-core comprises a target core and at least one other core;
the determining unit is used for enabling the target core to determine a first task according to the priority of the tasks in the global task ready list and the core task ready list of the target core when the target core occupies the spin lock to access the global task ready list, wherein the global task ready list stores the tasks which are not bound with the cores, and each core is provided with a core task ready list corresponding to the core and used for storing the tasks bound with the cores;
the running unit is used for enabling the target core to run the first task and release the spin lock;
the determining unit is further configured to, when the target core runs the first task and the other cores preempt the spin lock to access the global task ready table, enable the other cores to determine a second task according to priorities of tasks in the global task ready table and the core task ready table of the other cores;
the execution unit is further configured to cause the other cores to execute the second task.
In some modified embodiments of the second aspect of the present application, the determining unit includes: a comparison module and a determination module, wherein,
the comparison module is used for comparing the tasks in the global task ready list with the tasks in the core task ready list of the target core;
the determining module is used for determining the task with the highest task running priority as a first task;
the comparison module is also used for enabling the other cores to compare the tasks in the global task ready list with the tasks in the core task ready list of the other cores;
the determining module is further configured to determine that the task with the highest task running priority is the second task.
In some variations of the second aspect of the present application, the comparison module comprises:
the obtaining submodule is used for obtaining a first priority identification corresponding to a task with the highest priority in the global task ready list;
the obtaining submodule is further configured to enable the target core or the other cores to obtain, from a core task ready table of the target core or the other cores, a second priority identifier corresponding to a highest priority task in the table;
a comparison submodule for comparing the first priority identifier with the second priority identifier;
the obtaining submodule is further configured to obtain a higher priority identifier, where a task corresponding to the higher priority identifier is a task with a highest task running priority.
In some variations of the second aspect of the present application, the apparatus comprises:
the adding unit is used for adding the first task into a blocking list of the target core when the target core runs the first task and the time length of the target core waiting for the trigger message corresponding to the first task reaches a preset threshold value;
a release unit, configured to, when the other core monitors the trigger message, enable the other core to release a semaphore to the target core, where the semaphore is used to notify the target core to release a blocked signal;
and the returning unit is used for releasing the first task from the blocking list and returning the first task to the global task ready list after the target core acquires the semaphore when the first task does not have a binding relationship with the target core.
In some variations of the second aspect of the present application, the apparatus further comprises:
the adding unit is further configured to, when the first task has a binding relationship with the target core, release the first task from the blocking list and add the first task to a core task ready table of the target core after the target core acquires the semaphore;
a transmitting unit, configured to enable the other cores to transmit the trigger message to the target core and trigger an inter-core interrupt instruction, where the inter-core interrupt instruction is used to notify the target core of task switching;
an obtaining unit, configured to enable the target core to obtain the first task from the core task ready table according to the inter-core interrupt instruction;
the running unit is further configured to cause the target core to run the first task again according to the trigger message.
In some variations of the second aspect of the present application, the apparatus further comprises:
a termination unit, configured to cause the target core to terminate running a current task when the target core receives a timer interrupt instruction;
and the switching unit is used for enabling the target core to execute task switching operation according to the timed interrupt instruction.
In some modified embodiments of the second aspect of the present application, the switching unit includes:
an obtaining module, configured to enable the target core to obtain a right to access the global task ready list by preempting the spin lock;
the determining module is used for enabling the target core to determine a third task with the highest task running priority at present by comparing the task in the global task ready list with the task in the core task ready list of the target core;
and the running module is used for enabling the target core to run the third task and release the spin lock.
A third aspect of the present application provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a multicore CPU based FreeRTOS task execution method as described above.
A fourth aspect of the present application provides an electronic device, comprising: the processor executes the computer program to realize the FreeRTOS task running method based on the multi-core CPU.
By the technical scheme, the technical scheme provided by the invention at least has the following advantages:
the invention provides a method and a device for running a task by a FreeRTOS (free real time operating system) based on a multi-core CPU (central processing unit). firstly, the multi-core CPU is required to be initialized and configured, a plurality of cores acquire the authority of accessing a global task ready list by preempting a spin lock, so that the core which preempts the spin lock can be called a target core, and the core waiting for the release of the spin lock is called other cores. Therefore, each core has the opportunity to seize the spin lock to acquire the right of accessing the global task ready list, and then each core can determine to select one task according to the priority of the tasks in the global task ready list and the core task ready list, so that each core can independently run the selected task. Only when the spin lock is preempted, only one core executes the operation, but because the spin lock is released after the target core acquires the selected task, namely the selected task is executed and the spin lock is released, the spin lock is not occupied for a long time and the operation of acquiring the tasks by other cores is not delayed, so that the aim that a plurality of cores can simultaneously and independently execute the corresponding tasks is realized. Compared with the prior art, the method solves the problem that the conventional FreeRTOS real-time operating system does not support the multi-core CPU, and for the FreeRTOS real-time operating system running on the multi-core CPU, the method really realizes the simultaneous running of multiple tasks and ensures that the multi-core CPU fully exerts the performance of the CPU.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a flowchart of a method for operating a task by a multi-core CPU-based FreeRTOS according to an embodiment of the present invention;
FIG. 2 is a flowchart of another method for operating a task by a multi-core CPU-based FreeRTOS according to an embodiment of the present invention;
FIG. 3 is a block diagram of a FreeRTOS task execution device based on a multi-core CPU according to an embodiment of the present invention;
fig. 4 is a block diagram of another apparatus for performing task running by a multi-core CPU-based FreeRTOS according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
The embodiment of the invention provides a method for running a task of a FreeRTOS based on a multi-core CPU, as shown in figure 1, the method can support simultaneous running of multiple tasks when a FreeRTOS real-time operating system runs on the multi-core CPU, and the embodiment of the invention provides the following specific steps:
101. and initializing and configuring a multi-core CPU, wherein the multi-core comprises a target core and at least one other core.
In the embodiment of the present invention, the cores of the CPU acquire the right to access the global task ready table by preempting the spinlock, and thus the core that preempts the spinlock may be referred to as a target core, and the core that waits for the spinlock to be released may be referred to as another core.
In the embodiment of the invention, a pre-written startup file can be used for initializing the CPU, the startup file can be pre-written in the chip, the file can be directly run when the chip runs, the startup file mainly aims at the initialization of the chip, and for the embodiment of the invention, the initialization of the core of the multi-core CPU is mainly aimed at, namely, the startup file is used for carrying out some configuration on the multi-core CPU.
The process for initializing the multi-core CPU by using the boot file mainly comprises the following steps: initializing each core to allocate own stack space, specifically, storing at least one data table in a start-up file, and recording how much stack space each core allocates in the data table so as to complete initialization operation of resource allocation in the cores according to the data table; in addition, it is necessary to set clocks, such as the operating frequency of the CPU, and the operating frequency of each peripheral (such as a video card), which are equivalent to the initialization of the peripheral clock.
In the embodiment of the present invention, for a multi-core CPU, any one of a plurality of cores may be used as a first core, and the corresponding other cores are used as second cores, and the terms "first" and "second" are merely convenient for distinguishing one core from other cores. The initialization operation described above may be performed using the first core while the second core is in a wait state. Waiting for the first core to complete initialization operations, the first core will send a message to the second core, informing the second core to: the first core completes the initialization operation. The second core may directly copy the relevant configuration information on the first core to complete the initial configuration on the own core. Therefore, for the embodiment of the invention, only the initialization operation of any core needs to be executed by using the startup file, so that the time and the processing cost for initializing and configuring the multi-core CPU are greatly saved.
It should be noted that, in the embodiment of the present invention, only the concept of "first core" and "second core" is introduced in the initialization phase of the multi-core CPU, and after the initialization phase is completed, the operating principle of each core in the multi-core CPU is the same.
102. And if the target core preempts the spin lock to access the global task ready list, the target core determines a first task according to the priority of the tasks in the global task ready list and the core task ready list of the target core.
The global task ready list stores at least two tasks to be run, each task is designed according to actual task requirements, for example, one task is that a keyboard key A is pressed down to execute 'turn on/off' light. The tasks stored in the global task ready table are not pre-bound with a certain core, and different priorities can be set for each task in the table, so that the tasks in the table can be acquired by the core according to the priorities. In addition, each core is provided with a corresponding core task ready list for storing tasks bound with the core, each task in the list has the same design method as the tasks in the global task ready list, and the core task ready list can also add priority to each task so that the tasks in the list can be acquired by the core according to the priority.
In the embodiment of the present invention, the global task ready table may be stored in a memory, for example, for a 4G or 8G memory bank, a 1G space may be partitioned to store the global task ready table, and then each core of the CPU may access the space to obtain a task to be executed from the global task ready table. However, it should be noted that only one core is allowed to access the global task ready table to obtain a task at the same time, which uses a spin lock, which is a lock introduced specifically for preventing multiprocessor concurrency and is largely applied to interrupt processing and the like in the core.
Specifically, in the embodiment of the present invention, for multiple cores of a CPU, a task scheduler can be used to acquire a task from a global task ready table only when a spin lock is acquired, there is only one spin lock, and only when one core releases the spin lock is waited, other cores can acquire the spin lock. Therefore, by using the spin lock, the phenomenon that task switching can be performed simultaneously due to the simultaneous operation of a plurality of cores can be avoided, the problem that the operation of the system is wrong due to the fact that the core data are damaged is also avoided, and the purpose of protecting the core data is achieved.
The task scheduler mentioned above is a scheduler running under the FreeRTOS real-time operating system, and for the embodiment of the present invention, there is only one task scheduler, but there are multiple interfaces. After the multi-core CPU is initialized in step 101, which CPU core is started first may create the task scheduler, and each core may be connected to the task scheduler through the interface, enter the task scheduler, and use the task scheduler to acquire a task, perform task switching, control the running state of the task, and the like.
In the embodiment of the present invention, if a target core preempts a spin lock, it acquires the right to access the global task ready table, and it can access its own core task ready table, so that the target core can determine to select a task according to the priorities of the tasks in the global task ready table and its own core task ready table, and can be identified as a "first task", and the word "first task" and the following "second task" are convenient for distinguishing different tasks acquired by different cores.
103. The target core runs the first task and releases the spin lock.
In the embodiment of the invention, a plurality of cores of the CPU acquire the right to access the global task ready table by preempting the spin lock, so that the core preempting the spin lock can be called a target core, and the core waiting for the spin lock to be released is called other cores. After the target core acquires the first task, the target core runs the first task and can actively release the spin lock to give the opportunity of acquiring the spin lock, so that the target core runs the task without influencing the time of acquiring the spin lock by other cores and without influencing other cores to acquire other tasks.
104. And when the target core runs the first task, if other cores seize the spin lock to access the global task ready list, the other cores determine a second task according to the priority of the tasks in the global task ready list and the core task ready list of the other cores and run the second task.
In the embodiment of the invention, when the target core runs the first task, the spin lock is not occupied, but the spin lock is released, so that if other cores preempt the spin lock, the authority of accessing the global task ready list can be acquired. After the access authority is acquired, other cores can select one task according to the priorities of the tasks in the global task ready list and the core task ready list, the operation is the same as the operation of selecting the task by comparing the two task ready lists by the target core, and the task selected by the other cores is marked as a second task for distinguishing. After the second task is acquired, other cores can run the second task and release the spin lock, and the opportunity of acquiring the spin lock is given.
For the embodiment of the invention, each core in the multi-core CPU has the opportunity of preempting the spin lock and accessing the global task ready list, and then each core can select one task to be operated by comparing the global task ready list with the core task ready list, thereby realizing that a plurality of tasks can be deployed on a plurality of cores to operate at the same time and fully exerting the performance of the CPU.
In the above, an embodiment of the present invention provides a method for a FreeRTOS running task based on a multi-core CPU, where first, the multi-core CPU needs to be initialized and configured, and multiple cores acquire a right to access a global task ready table by preempting a spin lock, so that a core that preempts the spin lock may be referred to as a target core, and a core that waits for the spin lock to be released is referred to as another core. Therefore, each core has the opportunity to seize the spin lock to acquire the right of accessing the global task ready list, and then each core can determine to select one task according to the priority of the tasks in the global task ready list and the core task ready list, so that each core can independently run the selected task. Only when the spin lock is preempted, only one core executes the operation, but because the spin lock is released after the target core acquires the selected task, namely the selected task is executed and the spin lock is released, the spin lock is not occupied for a long time and the operation of acquiring the tasks by other cores is not delayed, so that the aim that a plurality of cores can simultaneously and independently execute the corresponding tasks is realized. Compared with the prior art, the method and the device solve the problem that the conventional FreeRTOS real-time operating system does not support the multi-core CPU, and for the FreeRTOS real-time operating system running on the multi-core CPU, the embodiment of the invention really realizes the support of simultaneous multi-task running and ensures that the multi-core CPU fully exerts the performance of the CPU.
In order to describe the above embodiments in more detail, another method for running a task by a FreeRTOS based on a multi-core CPU is further provided in the embodiments of the present invention, as shown in fig. 2, the following specific steps are provided for the embodiments of the present invention:
201. and initializing and configuring a multi-core CPU, wherein the multi-core comprises a target core and at least one other core.
In the embodiment of the present invention, the statement of this step refers to step 101, and is not described herein again.
202. And if the target core preempts the spin lock to access the global task ready list, the target core determines a first task according to the priority of the tasks in the global task ready list and the core task ready list of the target core.
Tasks which are not bound with the cores are stored in the global task ready list, and each core is provided with a corresponding core task ready list for storing the tasks bound with the cores.
In the embodiment of the present invention, under the FreeRTOS, no matter whether a core runs an initial task or obtains a new task due to task switching, each core selects a current highest priority task by comparing a global task ready list and a core task ready list, and the specific implementation steps may include the following:
firstly, after a target core preempts a spin lock and acquires the right of accessing a global task ready list, acquiring a first priority identification corresponding to a highest priority task in the list from the global task ready list.
And secondly, the target core acquires a second priority identification corresponding to the task with the highest priority in the table from a core task ready table of the target core.
And finally, comparing the first priority identification with the second priority identification to obtain a higher priority identification, wherein the task corresponding to the higher priority identification is the task with the highest task running priority.
For the embodiment of the invention, the task priority identifiers in different tables are adopted for comparison, so that the task with the current highest priority identifier in the two tables is judged, and the task is not directly extracted from the two tables for comparison, thereby avoiding the waste of processing resources caused by repeated extraction or replacement of the task, and improving the efficiency of identifying the task with the current highest priority identifier.
203. The target core runs the first task and releases the spin lock.
In the embodiment of the present invention, it should be added to this step that the task-based design is: after the target core acquires the task, the task is executed on the target core, but the completion of the task execution needs to be triggered by a 'message'. For example, the task "keyboard key a is pressed, and 'light on/off' is performed.
Then the target core will run the task after it has been retrieved, but will wait for a trigger message (i.e. detect that "keyboard key a is pressed") and, if it receives this trigger message, will be able to perform the task (i.e. perform "light on/off"). Then, if the task running on the target core has not received the corresponding trigger message and the waiting time reaches the preset threshold, the task is added to the blocking list in the target core.
It should be noted that, in the embodiment of the present invention, because multiple cores in a CPU all have a preemption spinlock to obtain an access right to access a global task ready table, each core can obtain a current highest priority task by comparing the global task ready table with its own core task ready table, and each core can obtain and run the task, that is, at this time, although a task on a target core is entered into an intra-core blocking list, the target core can still obtain the task, and other cores can also obtain and run the task, and the target core or other cores are still working.
Therefore, if the other core detects the above-mentioned trigger message (i.e. the trigger message required by the task on the target core), the other core releases a semaphore to the target core, and the semaphore is used to notify the target core to release the blocked signal. When the target core receives the semaphore, the task previously placed in the intra-core blocking list is released, but the following two cases exist for the subsequent operation:
in one case, if the released task does not have a binding relationship with the target core, the target core releases the task from the block list and returns the task to the global task ready table after acquiring the semaphore. Then the task cannot be immediately run, and only when a certain core obtains the access right to access the global task ready list and compares the global task ready list with the self-core task ready list to select the current highest-priority task as the task, the task can be extracted from the global task ready list by the certain core and put into the certain core, and when the certain core runs the task, the corresponding trigger message is required to be waited.
In another case, if the released task is bound to the target core, after the target core acquires the semaphore, the task is released from the block list and added to the core task ready table of the target core. The other cores transmit the trigger message to the target core and trigger an inter-core interrupt instruction, the inter-core interrupt instruction is used for informing the target core of task switching, namely informing the target core to stop other tasks currently running, but according to the inter-core interrupt instruction, the target core obtains a task (namely a task released before) from a core task ready list, and according to the trigger message, the target core reruns the task.
204. And when the target core runs the first task, if other cores seize the spin lock to access the global task ready list, the other cores determine a second task according to the priority of the tasks in the global task ready list and the core task ready list of the other cores and run the second task.
In the embodiment of the invention, under the FreeRTOS, no matter a core runs an initial task or acquires a new task due to task switching, each core selects the current highest-priority task by comparing a global task ready list with a self-core task ready list. Accordingly, the other cores also determine that the task with the highest task running priority is the second task by comparing the task in the global task ready list with the task in the core task ready list, and the specific implementation steps are as follows:
firstly, acquiring a first priority identifier corresponding to a highest priority task in a global task ready list; secondly, the target core or other cores acquire a second priority identification corresponding to the task with the highest priority in the list from a core task ready list of the target core or other cores; and finally, comparing the first priority identification with the second priority identification to obtain a higher priority identification, wherein the task corresponding to the higher priority identification is the task with the highest task running priority.
It should be noted that the specific implementation step of the other cores for acquiring the second task is actually the same as the specific implementation step of the target core for acquiring the first task, so details of the corresponding steps are stated and are not described herein again.
205. When the target core receives the timed interrupt instruction, the target core terminates running the current task.
In the embodiment of the present invention, the interrupt instruction types are divided into two types: one is a software interrupt and the other is a timed interrupt. The software interrupt type interrupt instruction refers to an inter-core interrupt instruction, such as the target core mentioned above, which receives the inter-core interrupt instruction to suspend other tasks currently running, but acquires a previously released blocked task from the core task ready table and runs the task. But the timed interrupt type corresponds to the timed interrupt instruction, the periodic interrupt instruction set by the FreeRTOS, the timed interrupt type corresponds to the interrupt control implemented by the timer, and the timer interrupt is generated by the system tick for periodically checking whether the task switching and the system delay function maintenance are required.
206. And according to the timed interrupt instruction, the target core executes task switching operation.
In the embodiment of the present invention, the step may further include: the target core acquires the authority of accessing the global task ready list by preempting the spin lock; the target core compares the task in the global task ready list with the task in the core task ready list of the target core to determine a third task with the highest task running priority at present; the target core runs a third task and releases the spin lock. This "third task" is conveniently used to identify a "first task" and a "second task" as distinguished from the above.
In the following, with reference to a specific exemplary scenario, the explanation step 205 and 206 may include the following steps:
illustratively, the target core is running a task a, which is always looped if no other events are interrupted, and the purpose of the timer interrupt is to interrupt the task a and switch it to another task. Specifically, a timing device (e.g., a timer) may be set on the chip to trigger once every 1 millisecond, and for a target core running the task a, when the timer triggers timer interrupt, the task a running by the target core is interrupted, and regardless of whether the task a is running completely, another task to be run is obtained from the global task ready table or the target core task ready table, specifically, the standard according to which the another task to be run is obtained is still: each core obtains the current highest priority task by comparing the task in the global task ready list with the task in the task ready list of the core.
For a further example, the task a is "do a summation operation, the continuous natural number is accumulated from 1 to 10000", when the target core runs the task a, if 1000 is accumulated, the target core receives a timed interrupt instruction at this time, no matter whether the task a is executed completely, the target core stops running the task a, and executes a task switching operation to obtain another task, specifically, which task is to be obtained, the spinlock needs to be obtained again to obtain the right to access the global task ready list, the task in the global task ready list is compared with the task in the core task ready list to obtain the current highest priority task, and if the task is the task B, the target core obtains the task B and runs the task B.
Further, as an implementation of the methods shown in fig. 1 and fig. 2, an embodiment of the present invention provides a FreeRTOS task execution device based on a multicore CPU. The embodiment of the apparatus corresponds to the embodiment of the method, and for convenience of reading, details in the embodiment of the apparatus are not repeated one by one, but it should be clear that the apparatus in the embodiment can correspondingly implement all the contents in the embodiment of the method. The device is applied to enable a FreeRTOS real-time operating system to run on a multi-core CPU, and particularly as shown in FIG. 3, the device comprises:
a configuration unit 301, configured to initialize and configure a multi-core CPU, where the multi-core includes a target core and at least one other core;
a determining unit 302, configured to, when the target core occupies the spin lock to access the global task ready table, enable the target core to determine a first task according to priorities of tasks in the global task ready table and a core task ready table of the target core, where the global task ready table stores tasks that are not bound to cores, and each core has a core task ready table corresponding to the core and is used to store tasks bound to the core;
a running unit 303, configured to enable the target core to run the first task and release the spin lock;
the determining unit 302 is further configured to, while the target core runs the first task, when the other cores preempt the spin lock to access the global task ready table, enable the other cores to determine a second task according to priorities of tasks in the global task ready table and the core task ready table of the other cores;
the running unit 303 is further configured to cause the other cores to run the second task.
Further, as shown in fig. 4, the determining unit 302 includes: a comparison block 3021 and a determination block 3022,
the comparing module 3021 is configured to compare the task in the global task ready table with the task in the core task ready table of the target core;
the determining module 3022 is configured to determine that the task with the highest task running priority is the first task;
the comparing module 3021 is further configured to compare the task in the global task ready table with the task in the core task ready table of the other core;
the determining module 3022 is further configured to determine that the task with the highest task running priority is the second task.
Further, as shown in fig. 4, the comparing module 3021 includes:
an obtaining submodule 30211, configured to obtain, from the global task ready table, a first priority identifier corresponding to a highest priority task in the table;
the obtaining sub-module 30211 is further configured to enable the target core or the other core to obtain, from a core task ready table of the target core or the other core, a second priority identifier corresponding to a highest priority task in the table;
a comparison submodule 30212, configured to compare the first priority identifier with the second priority identifier;
the obtaining submodule 30212 is further configured to obtain a higher priority identifier, where a task corresponding to the higher priority identifier is a task with the highest task running priority.
Further, as shown in fig. 4, the apparatus includes:
an adding unit 304, configured to add, when the target core runs the first task, the first task to a blocking list of the target core when a duration that the target core waits for the trigger message corresponding to the first task reaches a preset threshold;
a releasing unit 305, configured to, when the other core monitors the trigger message, enable the other core to release a semaphore to the target core, where the semaphore is used to notify the target core to release a blocked signal;
a returning unit 306, configured to, when the first task does not have a binding relationship with the target core, release the first task from the blocking list and return the first task to the global task ready table after the target core acquires the semaphore.
Further, as shown in fig. 4, the apparatus further includes:
the adding unit 304 is further configured to, when the first task has a binding relationship with the target core, release the first task from the blocking list and add the first task to a core task ready table of the target core after the target core acquires the semaphore;
a transmitting unit 307, configured to enable the other cores to transmit the trigger message to the target core and trigger an inter-core interrupt instruction, where the inter-core interrupt instruction is used to notify the target core of task switching;
an obtaining unit 308, configured to enable the target core to obtain the first task from the core task ready table according to the inter-core interrupt instruction;
the running unit 303 is further configured to cause the target core to run the first task again according to the trigger message.
Further, as shown in fig. 4, the apparatus further includes:
a termination unit 309, configured to, when the target core receives the timer interrupt instruction, cause the target core to terminate running the current task;
a switching unit 310, configured to enable the target core to perform task switching operation according to the timer interrupt instruction.
Further, as shown in fig. 4, the switching unit 310 includes:
an obtaining module 3101, configured to enable the target core to obtain a right to access the global task ready list by preempting the spin lock;
a determining module 3102, configured to compare the task in the global task ready list with the task in the core task ready list of the target core, and determine a third task with a current highest task running priority;
a running module 3103 configured to cause the target core to run the third task and release spin lock.
In summary, embodiments of the present invention provide a method and an apparatus for running a task by a FreeRTOS based on a multi-core CPU, where first, the multi-core CPU needs to be initialized and configured, and a plurality of cores acquire a right to access a global task ready table by preempting a spin lock, so that a core that preempts the spin lock may be referred to as a target core, and a core that waits for the spin lock to be released may be referred to as another core. Therefore, each core has the opportunity to seize the spin lock to acquire the right of accessing the global task ready list, and then each core can determine to select one task according to the priority of the tasks in the global task ready list and the core task ready list, so that each core can independently run the selected task. Only when the spin lock is preempted, only one core executes the operation, but because the spin lock is released after the target core acquires the selected task, namely the selected task is executed and the spin lock is released, the spin lock is not occupied for a long time and the operation of acquiring the tasks by other cores is not delayed, so that the aim that a plurality of cores can simultaneously and independently execute the corresponding tasks is realized. Compared with the prior art, the method and the device solve the problem that the conventional FreeRTOS real-time operating system does not support the multi-core CPU, and for the FreeRTOS real-time operating system running on the multi-core CPU, the embodiment of the invention really realizes the support of simultaneous multi-task running and ensures that the multi-core CPU fully exerts the performance of the CPU.
The FreeRTOS task running device based on the multi-core CPU comprises a processor and a memory, wherein the configuration unit, the determination unit, the running unit and the like are stored in the memory as program units, and the processor executes the program units stored in the memory to realize corresponding functions.
The processor comprises a kernel, and the kernel calls the corresponding program unit from the memory. One or more than one kernel can be set, and the FreeRTOS real-time operating system is operated on the multi-kernel CPU by adjusting kernel parameters, so that the simultaneous operation of multiple tasks is really supported, and the performance of the multi-kernel CPU is fully exerted.
The embodiment of the invention provides a computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, and when the computer program is executed by a processor, the method for running the task by the FreeRTOS based on the multi-core CPU is realized.
An embodiment of the present invention provides an electronic device, including: the processor executes the computer program to realize the FreeRTOS task running method based on the multi-core CPU.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a device includes one or more processors (CPUs), memory, and a bus. The device may also include input/output interfaces, network interfaces, and the like.
The memory may include volatile memory in a computer readable medium, Random Access Memory (RAM) and/or nonvolatile memory such as Read Only Memory (ROM) or flash memory (flash RAM), and the memory includes at least one memory chip. The memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims (10)

1. A FreeRTOS task running method based on a multi-core CPU is characterized by comprising the following steps:
initializing and configuring a multi-core CPU, wherein the multi-core comprises a target core and at least one other core;
if the target core occupies the spin lock to access the global task ready list, the target core determines a first task according to the priority of the tasks in the global task ready list and the core task ready list of the target core, the global task ready list stores the tasks which are not bound with the cores, and each core has a corresponding core task ready list and is used for storing the tasks bound with the cores;
the target core runs the first task and releases the spin lock;
and when the target core runs the first task, if the other cores preempt the spin lock to access the global task ready list, the other cores determine a second task according to the priority of the tasks in the global task ready list and the core task ready list of the other cores and run the second task.
2. The method of claim 1,
the target core determines a first task according to the priority of the tasks in the global task ready list and the core task ready list of the target core, and the method comprises the following steps: the target core
Comparing the tasks in the global task ready list with the tasks in the core task ready list, and determining the task with the highest task running priority as a first task;
the other cores determine a second task according to the priorities of the tasks in the global task ready list and the core task ready list of the other cores, and the method comprises the following steps: said other core
And comparing the tasks in the global task ready list with the tasks in the core task ready list to determine the task with the highest task running priority as a second task.
3. The method of claim 2, wherein comparing the global task-ready task with the own core task-ready task comprises:
acquiring a first priority identification corresponding to a highest priority task in the global task ready list;
the target core or the other cores acquire a second priority identification corresponding to the task with the highest priority in the table from a core task ready table of the target core or the other cores;
and comparing the first priority identification with the second priority identification to obtain a higher priority identification, wherein the task corresponding to the higher priority identification is the task with the highest task running priority.
4. The method of claim 1, wherein while the target core is running the first task, the method further comprises:
if the time length of the target core waiting for the trigger message corresponding to the first task reaches a preset threshold value, adding the first task into a blocking list of the target core;
when the other core monitors the trigger message, the other core releases a semaphore to the target core, wherein the semaphore is used for informing the target core of releasing a blocked signal;
and if the first task does not have a binding relationship with the target core, the target core releases the first task from the blocking list and returns the first task to the global task ready list after acquiring the semaphore.
5. The method of claim 4, wherein if the first task has a binding relationship with the target core, the method further comprises:
after the target core acquires the semaphore, releasing the first task from the blocking list and adding the first task into a core task ready table of the target core;
the other cores transmit the trigger message to the target core and trigger an inter-core interrupt instruction, wherein the inter-core interrupt instruction is used for informing the target core of task switching;
according to the inter-core interrupt instruction, the target core acquires the first task from the core task ready table;
and according to the trigger message, the target core reruns the first task.
6. The method of claim 1, further comprising:
when the target core receives a timed interrupt instruction, the target core stops running the current task;
and according to the timed interruption instruction, the target core executes task switching operation.
7. The method of claim 6, wherein the target core performs a task switch operation according to the timed interrupt instruction, comprising:
the target core acquires the authority of accessing the global task ready list by preempting the spin lock;
the target core compares the task in the global task ready list with the task in the core task ready list of the target core to determine a third task with the highest task running priority at present;
and the target core runs the third task and releases the spin lock.
8. A multi-core CPU-based FreeRTOS task execution apparatus, the apparatus comprising:
the system comprises a configuration unit, a processing unit and a control unit, wherein the configuration unit is used for initializing and configuring a multi-core CPU, and the multi-core comprises a target core and at least one other core;
the determining unit is used for enabling the target core to determine a first task according to the priority of the tasks in the global task ready list and the core task ready list of the target core when the target core occupies the spin lock to access the global task ready list, wherein the global task ready list stores the tasks which are not bound with the cores, and each core is provided with a core task ready list corresponding to the core and used for storing the tasks bound with the cores;
the running unit is used for enabling the target core to run the first task and release the spin lock;
the determining unit is further configured to, when the target core runs the first task and the other cores preempt the spin lock to access the global task ready table, enable the other cores to determine a second task according to priorities of tasks in the global task ready table and the core task ready table of the other cores;
the execution unit is further configured to cause the other cores to execute the second task.
9. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when executed by a processor, implements the multicore CPU based FreeRTOS task execution method according to any one of claims 1 to 7.
10. An electronic device, comprising: memory, processor and computer program stored on the memory and executable on the processor, the processor implementing the multicore CPU based FreeRTOS run task method according to any one of claims 1 to 7 when executing the computer program.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114880075A (en) * 2022-05-11 2022-08-09 科东(广州)软件科技有限公司 Method and device for scheduling tasks among virtual cores of user-mode virtual machine
CN116225728A (en) * 2023-05-09 2023-06-06 北京星辰天合科技股份有限公司 Task execution method and device based on coroutine, storage medium and electronic equipment

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114880075A (en) * 2022-05-11 2022-08-09 科东(广州)软件科技有限公司 Method and device for scheduling tasks among virtual cores of user-mode virtual machine
CN114880075B (en) * 2022-05-11 2023-01-06 科东(广州)软件科技有限公司 Method and device for scheduling task between virtual cores of user-mode virtual machine
CN116225728A (en) * 2023-05-09 2023-06-06 北京星辰天合科技股份有限公司 Task execution method and device based on coroutine, storage medium and electronic equipment
CN116225728B (en) * 2023-05-09 2023-07-14 北京星辰天合科技股份有限公司 Task execution method and device based on coroutine, storage medium and electronic equipment

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