WO2010109609A1

WO2010109609A1 - Processing device and vehicle engine control device

Info

Publication number: WO2010109609A1
Application number: PCT/JP2009/055963
Authority: WO
Inventors: 和千男小林
Original assignee: トヨタ自動車株式会社
Priority date: 2009-03-25
Filing date: 2009-03-25
Publication date: 2010-09-30

Abstract

Provided is a processing device including a plurality of processors which perform a distributed process of a plurality of tasks to be executed cyclically in a predetermined order. The plurality of tasks include: a first task executed by a first processor and a second task to be executed by a second processor after the first task. Start of the first task is limited according to a graph expressing the execution state of the second task.

Description

Processing device and vehicle engine control device

The present invention relates to a processing device or the like that performs distributed parallel processing with a plurality of processors on a plurality of tasks that should be periodically executed in a predetermined order.

Conventionally, in a configuration using a single-core microcomputer, a crank counter value (a crank counter value stored in another second storage means) that latches inconsistency in crank synchronization processing due to multiple interrupts is used for crank synchronization processing. A technique for preventing this is known (for example, see Patent Document 1).
JP 62-10453 A

By the way, when a recently proposed multi-core microcomputer is used, the overall processing speed can be increased by performing distributed parallel processing of a plurality of tasks by a plurality of processors. However, when multiple tasks are periodically distributed and parallel processed by multiple processors, the execution of some of the multiple tasks is delayed due to, for example, other high-priority task processing, and shifted to the next cycle. As a result, there is a risk of inconsistency between tasks (between functions) (incorrect processing order).

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a processing device and a vehicle engine control device that can appropriately prevent inconsistencies between tasks in a configuration in which a plurality of tasks are periodically distributed and parallel processed by a plurality of processors. .

In order to achieve the above object, according to one aspect of the present invention, there is provided a processing device for performing distributed parallel processing with a plurality of processors on a plurality of tasks to be periodically executed in a predetermined order,
The plurality of tasks are a first task executed by a first processor and a second task executed after the first task, and a second task executed by the second processor Including
A processing device is provided, wherein activation of the first task is limited based on a flag indicating an execution state of the second task.

According to the present invention, it is possible to obtain a processing device and a vehicle engine control device that can appropriately prevent inconsistencies between tasks in a configuration in which a plurality of tasks are periodically distributed and parallel processed by a plurality of processors.

It is a block diagram which shows the main structures of one Example of the processing apparatus 10 by this invention. It is a figure which shows the sequence at the time of normal. It is a figure which shows the sequence (sequence by a comparative example) when inconsistency arises in the processing order of the crank synchronous process 1 and the crank synchronous process 2 in case there exists execution of a high priority task. It is a figure which shows the one aspect | mode of the problem which arises when there exists the dependence of the order of the crank synchronization process 1 and the crank synchronization process 2, and is a figure which shows the sequence at the time of normal. It is a figure which shows the one aspect | mode of the problem which arises when there exists dependence of the order of the crank synchronization process 1 and the crank synchronization process 2, and when the high priority task is executed, the crank synchronization process 1 and the crank synchronization process 2 The sequence when a contradiction occurs in the processing order is shown. It is a figure which shows the other one aspect | mode of the problem which arises when there exists dependence of the order of the crank synchronous process 1 and the crank synchronous process 2, and is a figure which shows the sequence at the time of normal. It is a figure which shows another one aspect | mode of the problem which arises when there exists the dependence of the order of the crank synchronization process 1 and the crank synchronization process 2, and the crank synchronization process 1 and the crank synchronization process when there is execution of a high priority task 2 shows a sequence when a contradiction occurs in the processing order 2. It is a figure which shows the sequence by a present Example in case there exists execution of a high priority task.

Explanation of symbols

10 processor 20 master core 30 slave core 40 shared RAM
50 NE sensor

Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the main configuration of an embodiment of a processing apparatus 10 according to the present invention. As shown in FIG. 1, the processing apparatus 10 of this embodiment includes a multicore microcomputer capable of parallel processing. That is, the processing device 10 includes a master core 20, a slave core 30, and a shared RAM 40. The shared RAM 40 can reference / write data from either the master core 20 or the slave core 30. Note that a crank task 2 activation flag, which will be described later, is set in the shared RAM 40.

The processing device 10 is connected to an NE sensor 50 that outputs an electrical signal corresponding to the rotation of the crankshaft of the engine. The processing device 10 functions as a vehicle engine control device (EFI / ECU) that performs various controls of the vehicle engine in a state where the NE sensor 50 is connected. The NE sensor 50 supplies (inputs) an NE sensor signal to the processing device 10 at every predetermined rotation angle (for example, 10 degrees) of the crankshaft.

The master core 20 and the slave core 30 perform engine control processing in cooperation with each other. The engine control process includes a crank counter process that specifies a crank position from the NE sensor signal, and a crank synchronization process that is executed in synchronization with the crank counter process. The crank synchronization process generally includes a plurality of crank synchronization processes, and here, as an example, includes three crank synchronization processes. Hereinafter, these three crank synchronization processes are referred to as crank synchronization processes 1, 2, and 3.

In this example, the master core 20 executes crank counter processing (crank height task), crank synchronization processing 1 and crank synchronization processing 3 (crank task 1). Further, the slave core 30 executes crank synchronization processing 2 (crank task 2). The crank synchronization process 1 and the crank synchronization process 2 have a relationship that depends on the processing order. In other words, the crank synchronization process 1 and the crank synchronization process 2 are in a relationship in which one uses the processing result of the other, and therefore there is a relationship in which the reliability of the processing result becomes worse when there is a contradiction in the processing order (about this) Will be described later with reference to FIGS. 4 and 5.) As long as the crank synchronization process 1 and the crank synchronization process 2 are in a relationship that depends on the processing order, the contents of each process may be arbitrary.

In this example, the slave core 30 executes a high priority task other than the crank synchronization process in addition to the crank task 2. The high priority task is a task having a higher priority than the crank synchronization process 2 (crank task 2), for example, a task for communication with the outside and a task for processing fuel injection timing (ignition / energization timing). Good. The high priority task may be a task that is executed regularly or irregularly.

FIG. 2 is a diagram showing a normal sequence.

In the normal state, as shown in FIG. 2, in the master core 20, the crank height task is woken up with the input of the NE sensor signal as a trigger, the crank counter process is executed, and the crank synchronization process 1 is woken up at the end of the crank counter process. The crank synchronization process 1 is executed after the crank counter process. In the master core 20, the crank synchronization processes 2 and 3 are woken up at the end of the crank synchronization process 1. As a result, in the master core 20, the crank synchronization process 3 is executed after the crank synchronization process 1, and in the slave core 30, the crank synchronization process 2 is executed after the crank synchronization process 1. In this way, the crank height task, the crank task 1 and the crank task 2 are executed in a cycle corresponding to the input cycle of the NE sensor signal.

According to the sequence shown in FIG. 2, a plurality of crank synchronization processes are distributed and processed in parallel in the slave core 30 and the slave core 30, so that highly sophisticated and complicated engine control processes can be efficiently executed in a short time. it can.

However, in the configuration in which the crank synchronization process 2 is simply woken up at the end of the crank synchronization process 1, the crank synchronization process 1 and the crank synchronization process 2 are caused by the presence of a high priority task, for example, as shown in FIG. There is a risk of inconsistency in the processing order.

Specifically, in the example shown in FIG. 3, the crank synchronization process 2 is woken up at the end of the crank synchronization process 1 in the period (k), but at the time of wakeup, a high priority task is executed in the slave core 30. Yes. For this reason, as indicated by symbol Y1 in FIG. 3, in the slave core 30, the execution of the crank synchronization process 2 is waited until the end of the high priority task. In the example illustrated in FIG. 3, the high priority task ends after the start of the crank synchronization process 1 in the next cycle (k + 1). Such a situation is particularly likely to occur when the processing time required for a high priority task is long or when the engine speed is high. In such a situation, when the crank synchronization process 1 is executed in response to the input of the NE sensor signal of the next period (k + 1), as shown by reference numeral Y2 in FIG. 3, the crank synchronization process 1 and the crank synchronization process are performed. An area where a contradiction occurs in the processing order 2 is created.

If there is a contradiction between the processing order of the crank synchronization process 1 and the crank synchronization process 2, the reliability of the processing result is caused by the dependence on the processing order of the crank synchronization process 1 and the crank synchronization process 2. Deteriorate.

For example, in the example illustrated in FIG. 4, the crank synchronization process 1 is a process that calculates only the interval time between NE sensor signals, and the crank synchronization process 2 is controlled using the interval time calculated in the crank synchronization process 1. This is a process of calculating the amount. Therefore, the crank synchronization process 1 should be executed after the crank synchronization process 2 in the previous cycle and should not be executed before the crank synchronization process 2 in the previous cycle. In this relationship, when there is a contradiction in the processing order of the crank synchronization process 1 and the crank synchronization process 2 as described above, as shown in FIG. 4B, the normal sequence shown in FIG. As can be seen, in the crank synchronization process 2, the interval time between NE sensor signals having a period different from the interval time between NE sensor signals that should be referred to is referred to. More specifically, in the example shown in FIG. 4B, the crank synchronization process 2 in the cycle (k−1) is put into a standby state by the high priority task in the cycle (k−1), and the cycle (k−1) ) Is synchronized until the execution of the crank synchronization process 1 of the period (k). For this reason, the interval time between NE sensor signals referred to in the crank synchronization process 2 in the cycle (k−1) is the interval time between NE sensor signals originally calculated in the crank synchronization process 1 in the cycle (k−1). However, it is the interval time between NE sensor signals (interval time between NE sensor signals at the previous NE sensor signal timing) calculated in the crank synchronization processing 1 of the period (k). End up. As a result, in the control amount calculated in the crank synchronization process 2, an error corresponding to the difference between the NE sensor signal interval times calculated in the period (k) and the period (k + 1) occurs.

In the example shown in FIG. 5, the crank synchronization process 1 calculates, for example, another predetermined control amount based on the control amount data calculated in the crank synchronization process 2 at the previous NE sensor signal timing (previous cycle). It is processing to do. Therefore, the crank synchronization process 1 should be executed after the crank synchronization process 2 in the previous cycle and should not be executed before the crank synchronization process 2 in the previous cycle. In this relationship, when there is a contradiction in the processing order between the crank synchronization process 1 and the crank synchronization process 2 as described above, as shown in FIG. 5B, the normal sequence shown in FIG. As can be seen, in the crank synchronization process 1, control amount data having a period different from that of the control amount data that should be referred to is referred to. More specifically, in the example shown in FIG. 5B, the crank synchronization process 2 of the cycle (k−1) is put into a standby state by the high priority task at the cycle (k−1), and the cycle (k−1) ) Is synchronized until the execution of the crank synchronization process 1 of the period (k). Therefore, when the crank synchronization process 1 of the period (k) is executed, the result (control amount data) of the crank synchronization process 2 of the period (k−1) that should be referred to does not exist, and the crank of the period (k) In the synchronization process 1, the control amount data of the crank synchronization process 2 in the cycle (k-2) (control amount data at the timing of the previous NE sensor signal) is referred to. As a result, in the control amount calculated in the crank synchronization process 1, an error corresponding to the difference between the control amount data calculated in the cycle (k-2) and the cycle (k-2) occurs.

Therefore, in this embodiment, a crank task 2 activation flag indicating whether or not the crank task 2 is activated and terminated is set, and activation of the crank task 1 is controlled according to the state of the crank task 2 activation flag. Thus, the occurrence of inconsistencies in the processing order as described above is prevented.

Specifically, in this embodiment, the occurrence of contradictions in processing order is prevented by the following procedure.
(1) When the NE sensor signal is input, the master core 20 wakes up the crank height task and performs crank counter processing.
(2) After the crank counter processing, the master core 20 refers to the crank task 2 activation flag in the shared RAM 40 and activates the crank task 1 only when the crank task 2 activation flag is off. When the crank task 2 activation flag is on, the crank task 1 is set to the standby state (Wait state) and the crank height task is ended. When the crank task 2 activation flag is switched from on to off, the crank task 1 transitions from the standby state to the execution state (RUN state), and the crank task 1 is executed.
(3) The crank synchronization process 1 is performed in the crank task 1 by the master core 20, and the crank task 2 is woken up after the process. At the same time, the master core 20 accesses the shared RAM 40 and sets the crank task 2 activation flag to ON. Thereafter, the crank synchronization process 3 is performed in the crank task 1 by the master core 20.
(4) When the crank task 2 is woken up in the above (3), the crank task 2 is executed by the slave core 30. After the processing, the shared RAM 40 is accessed and the crank task 2 activation flag is set to OFF.

FIG. 6 is a diagram showing a sequence of the above-described processing according to the present embodiment. In FIG. 6, the high priority task is generated in the same manner as the comparative example shown in FIG. However, according to the present embodiment, as shown in the lowermost stage of FIG. 6, even if the crank task 2 of the cycle (k) enters a standby state due to the high priority task and the execution is delayed until the next cycle (k + 1), the cycle ( The crank task 2 activation flag is kept on until the crank task 2 of k) is woken up and ended. Accordingly, during this period, the crank task 1 of the cycle (k + 1) is in a standby state and is not executed. Then, the crank task 1 of the cycle (k + 1) is executed when the crank task 2 of the cycle (k) ends and the crank task 2 activation flag is turned off. Thus, according to the present embodiment, inconsistency in the processing order of the crank synchronization process 1 and the crank synchronization process 2 is prevented.

According to the processing apparatus 10 of the present embodiment described above, the following excellent effects are achieved, among others.

As described above, even when the crank synchronization process 1 and the crank synchronization process 2 that depend on the processing order are distributed by the multi-core microcomputer, the crank synchronization process 1 is performed based on the crank task 2 activation flag indicating the state of the crank synchronization process 2. By controlling the start-up, it is possible to prevent a region where the contradiction occurs in the processing order of the crank synchronization process 1 and the crank synchronization process 2. Thereby, the problems as described above with reference to FIGS. 4 and 5 can be appropriately prevented, and a highly reliable processing result can be obtained. In addition, since the dependency on the processing order of the crank synchronization process 1 and the crank synchronization process 2 is maintained, the conventional software configuration (that is, a software configuration assuming a single core microcomputer) is drastically used for distributed parallel processing by a multicore microcomputer. It is not necessary to perform a complete review, and the function review man-hours and software development man-hours can be reduced.

The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

For example, in the above-described embodiment, the processing order contradiction between the crank synchronization processes of the engine is prevented. However, the present invention can also be applied to prevent the processing order contradiction between other processes. is there. For example, in the motor control, the present invention can be similarly applied to a plurality of processes (tasks) to be executed in synchronization with the rotation angle of the motor when there is a dependency on the processing order as described above. It is.

In the above-described embodiment, two cores (master core 20 and slave core 30) are used. However, three or more cores (for example, one master core 20 and two or more slave cores 30) may be used. Is possible. In this case, when each task of the master core 20 and the slave core 30 is dependent on the above-described processing order, the above-described flag may be set between two tasks depending on the processing order. The same applies when each task of the plurality of slave cores 30 has dependency on the processing order described above, and the above-described flag may be set between two tasks having dependency on the processing order.

Claims

A processing device that performs distributed parallel processing with a plurality of processors on a plurality of tasks to be periodically executed in a predetermined order,
The plurality of tasks are a first task executed by a first processor and a second task executed after the first task, and a second task executed by the second processor Including
The processing apparatus, wherein activation of the first task is restricted based on a flag indicating an execution state of the second task.
The flag is set to the first state when the second task is woken up or when the execution of the first task is completed, and is set to the second state when the execution of the second task is completed,
The processing device according to claim 1, wherein activation of the first task is prohibited in a first state of the flag and permitted in a second state of the flag.
The processing apparatus according to claim 1, wherein the plurality of tasks are periodically executed in synchronization with an input period of a predetermined signal input at a non-constant time period.
4. The processing apparatus according to claim 3, wherein the predetermined signal is a signal of an NE sensor representing an engine crank angle, and is generated at every predetermined crank rotation angle.
The processing apparatus according to claim 4, wherein the first task and the second task are crank synchronization processing synchronized with a crank angle of an engine.
The processing apparatus according to claim 1, wherein the second task is a task that is woken up at the end of the first task.
A first and second processor;
A shared memory capable of data reference and data writing from any of the first and second processors;
An NE sensor for detecting the crank angle of the engine,
The plurality of tasks are a first task executed by a first processor and a second task executed after the first task, and a second task executed by the second processor And the first task and the second task are crank synchronization processes executed in a cycle synchronized with a predetermined crank rotation angle based on an output signal of the NE sensor,
The first processor is configured to access the memory and set a flag to a first state at the time of wake-up processing of the second task or when execution of the first task is completed,
The second processor is configured to access the memory upon completion of execution of the second task and set the flag to a second state;
The first processor refers to the memory, and waits for activation of the first task when the flag is in the first state, and the flag is changed from the first state to the second state. An engine control device for a vehicle configured to activate the first task when the state is reached.