JP6243266B2 - Electronic control device and memory diagnostic method - Google Patents

Description

  The present invention relates to an electronic control device mounted on a vehicle such as an automobile and a memory diagnosis method thereof.

  Some models of electronic control units (ECUs) mounted on vehicles such as automobiles perform memory diagnosis when the system is started. And the technique which shortens the time concerning initialization processing and memory diagnostic processing at the time of starting of a system by parallel processing using a plurality of processors is proposed (for example, refer to patent documents 1).

JP-A-6-325007

  However, if parallel processing is simply performed, the processing time varies depending on the processor specifications and the like, the end time tends to vary, and a waiting time tends to occur.

  Accordingly, an object of the present invention is to provide a technique capable of improving the efficiency of memory diagnosis in an electronic control device mounted on a vehicle such as an automobile.

An electronic control device according to the present invention is an electronic control device including a plurality of arithmetic devices and a memory for storing data, and each arithmetic device divides the memory into a plurality of areas and performs a predetermined memory diagnosis. During execution of multiple periodic jobs, the memory area allocated based on the processing capacity of each arithmetic unit in any job is individually diagnosed, and the memory diagnosis result is abnormal. In such a case, another arithmetic device different from the arithmetic device that diagnosed the abnormality performs the memory diagnosis again on the memory area diagnosed as abnormal.

  According to the present invention, it is possible to provide a technique capable of improving the efficiency of memory diagnosis.

It is a figure which shows the hardware structural example of an electronic controller. It is a figure explaining an example of the memory diagnosis in the conventional multi-core processor. It is a figure explaining an example of the process of the memory diagnosis in 1st Embodiment. It is a figure explaining an example of the timing chart of the memory diagnosis in 1st Embodiment. It is a figure explaining an example of the process of the memory diagnosis in 2nd Embodiment. It is a figure explaining an example of the process of the memory diagnosis in 3rd Embodiment. It is a figure explaining an example of the timing chart of the memory diagnosis in 3rd Embodiment. It is a figure explaining the timing chart example of the memory diagnosis in 4th Embodiment. It is a figure explaining an example of the process of the memory diagnosis in 5th Embodiment. It is a flowchart which shows an example of the process of the memory diagnosis in 5th Embodiment. It is a flowchart of the subroutine which shows an example of the process of the memory diagnosis in 5th Embodiment. It is a figure explaining an example of the process of the memory diagnosis in 5th Embodiment. It is a flowchart of the subroutine which shows an example of the process of the memory diagnosis in 5th Embodiment. It is a figure explaining an example of the process of the memory diagnosis in 6th Embodiment. It is a figure explaining an example of the timing chart of the memory diagnosis in 6th Embodiment. It is a flowchart which shows an example of the process of the memory diagnosis in 6th Embodiment. It is a figure explaining an example of the process of the memory diagnosis in 8th Embodiment.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings.
First, a hardware configuration example of the electronic control device will be described.
An electronic control device 100 shown in FIG. 1 is a device that is mounted on, for example, an automobile and electronically controls an engine, an automatic transmission, a fuel pump, and the like.
The electronic control device 100 includes a processor 1, a ROM (Read Only Memory) 2, a RAM (Random Access Memory) 3, and a bus 4. The processor 1, ROM 2, and RAM 3 are connected to each other via a bus 4.

  The processor 1 performs overall control of the electronic control device 100. Here, the processor 1 has a plurality of CPU cores (for example, the first core 11 and the second core 12) mounted in one CPU package, and the processing speed is increased by physically increasing the number of CPU cores. It is a multi-core processor that aims to The processor 1 shown in FIG. 1 exemplifies a dual core having two CPU cores. However, the present invention is not limited to this. For example, a triple core having three CPU cores and a quad core having four CPU cores are provided. It may be. Further, more CPU cores may be mounted. The CPU core (for example, the first core 11 and the second core 12) is an example of an arithmetic device.

  The ROM 2 is a non-volatile semiconductor memory such as a flash ROM that retains data even when power supply is cut off. The ROM 2 includes a first core area 21 and a second core area 22. In the first core area 21 and the second core area 22, for example, a memory area targeted for memory diagnosis is set according to the processing capability of the processor 1 (the first core 11, the second core 12, etc.).

  The RAM 3 is, for example, a memory serving as a temporary work area for data used for arithmetic processing and the like, and is a volatile memory whose stored contents disappear when power supply is interrupted. More specifically, the RAM 3 is a storage device that can perform operations such as reading and writing on a memory cell at an arbitrary address based on address information such as an address. Note that the RAM 3 may be, for example, a dynamic RAM or a static RAM. The bus 4 includes, for example, a memory access bus.

  In addition, the electronic control device 100 realizes various functions through the cooperation of hardware such as the processor 1, the ROM 2, and the RAM 3, and software such as a control program. This control program includes a program for performing processing such as memory diagnosis of the present embodiment. Accordingly, in the processor 1, the first core 11 and the second core 12 execute the control program, thereby realizing processing such as memory diagnosis.

[Comparison with conventional example]
Here, in order to better understand the technology disclosed in the present case, a memory diagnosis in a conventional multi-core processor will be briefly described.
As shown in FIG. 2, in the memory diagnosis in the conventional multi-core processor, as an example, the diagnosis area of the memory 2a is equally divided into two, the first core 11 of the multi-core processor diagnoses the first ROM area 21a, and the multi-core processor The second core diagnoses the second ROM area 22a. As a diagnosis method, for example, a so-called checksum method is adopted. As an example, the checksum method compares a checksum (total value) calculated for each block of the first ROM area 21a and the second ROM area 22a with a checksum (expected value) calculated in advance. If the checksum (total value) matches the checksum (expected value), it is diagnosed as normal.

  Here, for example, if the first core 11 and the second core 12 have different clock frequencies (operating frequencies) that serve as a guide for the arithmetic processing capability, the processing time for memory diagnosis or the like tends to vary. As described above, the core that has completed the memory diagnosis first generates a wasteful waiting time until the memory diagnosis by other cores is completed.

  Therefore, in the embodiment described below, a technique capable of improving the efficiency of memory diagnosis will be described. In addition, for example, speeding up of memory diagnosis and processing at the time of abnormality will be described.

[First embodiment]
FIG. 3 schematically shows the area of the ROM 2 as an example of the memory diagnosis process in the first embodiment. In FIG. 3, the expected value area in the checksum for each block as shown in FIG. 2 is not shown (hereinafter the same). In FIG. 3, the blocks of the memory diagnosed by the second core 12 are illustrated by diagonal lines. Here, in the first embodiment, the first clock frequency (f ₁ ) of the first core 11 is 240 MHz as an example, and the second clock frequency (f ₂ ) of the second core 12 is 80 MHz as an example. To do.

In the first embodiment, the memory area of the ROM 2 is divided into 20 blocks for easy understanding (see FIG. 3). Note that the method of dividing the memory area into a plurality of areas is an example, and may be divided according to the physical space or may be divided according to the logical space. In other words, the method of dividing the memory area into a plurality of areas is not particularly limited as long as it contributes to efficient memory diagnosis.
Here, when divided into 20 blocks as an example, the ratio r ₁ of the area in which the first core 11 performs memory diagnosis is:
r ₁ = f ₁ / (f ₁ + f ₂ ) = 240 MHz / (240 + 80) MHz = 0.75
It becomes.

On the other hand, the ratio r ₂ of the area where the second core 12 performs memory diagnosis is
r ₂ = f ₂ / (f ₁ + f ₂ ) = 80 MHz / (240 + 80) MHz = 0.25
It becomes. As a result, the number of blocks B _{1 in the} area where the first core 11 performs memory diagnosis is B ₁ = 20 × 0.75 = 15 blocks. Further, the number of blocks B _{2 in the} area where the second core 12 performs memory diagnosis is B ₂ = 20 × 0.25 = 5 blocks.
In the case of the above ratio, the number of blocks in the first core area 21 shown in FIG. 1 is 15 blocks, and the number of blocks in the second core area 22 is 5 blocks.
Therefore, as shown in FIG. 3, the first core 11 whose clock frequency is three times higher than the second core 12 can diagnose more blocks per unit time. This point will be described in more detail with reference to FIG.

In the timing chart of the memory diagnosis shown in FIG. 4, the horizontal axis represents the time axis, and the vertical axis schematically represents the diagnosis time of the blocks executed by the first core 11 and the second core 12 shown in FIG. It is represented by a rectangle. Specifically, FIG. 1 indicates that the larger the rectangular area, the longer the diagnosis time is required. Here, the memory diagnosis at the time of starting of the electronic control apparatus 100 is illustrated.
FIG. 4A illustrates, as a comparative example, a case where the diagnostic region is equally divided (in 10 blocks) between the first core 11 and the second core 12. FIG. 4B illustrates a case where the first core 11 diagnoses 15 blocks and the second core 12 diagnoses 5 blocks, as shown in FIG.

  In the case of FIG. 4A, since the clock frequency of the first core 11 is three times higher than that of the second core 12, the diagnosis time of the memory is completed in about one-third of the time. In this case, if the first core 11 cannot execute the next job unless the memory diagnosis job of the second core 12 is completed, a wasteful waiting time occurs.

On the other hand, in the case of FIG. 4B, the first core 11 diagnoses 15 blocks and the second core 12 diagnoses 5 blocks. Thereby, the end of the memory diagnosis of the first core 11 and the end of the memory diagnosis of the second core 12 substantially coincide.
That is, the first core 11 and the second core 12 are allocated based on the clock frequency of each core when the ROM 2 area is divided and memory diagnosis is performed using a predetermined checksum or the like. Diagnose each block of memory individually. Therefore, in the first embodiment, the efficiency of the memory diagnosis in the multi-core processor can be realized by changing the ratio of the memory diagnosis area according to the clock frequency. As a result, in the first embodiment, the memory diagnosis can be speeded up. Note that the ratio calculation and the memory block allocation may be performed by, for example, one of the first core 11 and the second core 12.

[Second Embodiment]
In the second embodiment, the ratio of the areas to be diagnosed is determined based on the processing load (hereinafter referred to as “processing load”) of each core. During the operation of the electronic control unit 100, the first core 11 and the second core 12 each manage the load factor for the arithmetic processing.

As an example of the memory diagnosis process shown in FIG. 5, specifically, the load factor of the first core 11 is set to 60%, and the load factor of the second core 12 is set to 20%. In other words, the margin ratio indicating the usable ratio of each core is 40% in the case of the first core 11 and 80% in the case of the second core 12. In the second embodiment, the case where the memory area of the ROM 2 is divided into 20 blocks will be described. Here, in the second embodiment, the margin ratio (s ₁ ) of the first core 11 is 40% as an example, and the margin ratio (s ₂ ) of the second core 12 is 80% as an example. In this case, the ratio r ₁ of the area where the first core 11 performs memory diagnosis is
r ₁ = s ₁ / (s ₁ + s ₂ ) = 40 / (40 + 80) = 0.333≈33%
It becomes.

On the other hand, the ratio r ₂ of the area where the second core 12 performs memory diagnosis is
r ₂ = s ₂ / (s ₁ + s ₂ ) = 80 / (40 + 80) = 0.666≈67%
It becomes. As a result, the number of blocks B _{1 in the} area where the first core 11 performs memory diagnosis is B ₁ = 20 × 0.33 = 6.6≈7 blocks. Further, the number of blocks B _{2 in the} area where the second core 12 performs memory diagnosis is B ₂ = 20 × 0.67 = 13.4≈13 blocks.
In this case, as shown in FIG. 5, the first core 11 having a high load (load factor 60%) performs a memory diagnosis of 7 blocks, and the second core 12 having a low load (load factor 40%) is 13 blocks. Perform memory diagnostics. Thereby, also in the second embodiment, the efficiency of the memory diagnosis can be realized by changing the ratio of the memory diagnosis area according to the processing load of each core.

[Third embodiment]
In the third embodiment, memory diagnosis is performed in consideration of the clock frequency and processing load of each core.

In the example of the memory diagnosis process in the third embodiment shown in FIG. 6, the first clock frequency (f ₁ ) of the first core 11 is 240 MHz and the second clock of the second core 12 is the same as in the first embodiment. The frequency (f ₂ ) is 80 MHz. The margin ratio of the first core 11 is 40%, and the margin ratio of the second core 12 is 80%.
Here, in order to consider the clock frequency and processing load of each core, in the case of the first core 11, first, 75% calculated in the first embodiment is multiplied by 33% calculated in the second embodiment. A value (r ₃ ) of 24.75% is obtained. Further, in the case of the second core 12, first, the value (r ₄ ) of 16.75% is obtained by multiplying 25% calculated in the first embodiment by 67% calculated in the second embodiment. .

Subsequently, the ratio r ₁ of the area in which the first core 11 performs memory diagnosis is:
r ₁ = r ₃ / (r ₃ + r ₄ ) = 24.75 / (24.75 + 16.75)
= 0.5963≈60%.
On the other hand, the ratio r ₂ of the area where the second core 12 performs memory diagnosis is
r ₂ = r ₄ / (r ₃ + r ₄ ) = 16.75 / (24.75 + 16.75)
= 0.4036≈40%.

Therefore, as shown in FIG. 6, the number of blocks B _{1 in the} area in which the first core 11 performs memory diagnosis is B ₁ = 20 × 0.60 = 12 blocks, and the number of blocks in the area in which the second core 12 performs memory diagnosis B ₂ is B ₂ = 20 × 0.40 = 8 blocks.
FIG. 7 shows an example of a timing chart of memory diagnosis in the third embodiment. However, for convenience of explanation, FIG. 7 illustrates the diagnosis time of the memory in units of 20 blocks in which the waiting time is omitted and divided by a thick chain line. Specifically, FIG. 7A illustrates, as a comparative example, a case where the memory diagnosis area is divided equally (10 blocks) in the first core 11 and the second core 12. FIG. 7B illustrates a case where the first core 11 performs memory diagnosis on 12 blocks and the second core 12 performs memory diagnosis on 8 blocks, as illustrated in FIG. 6.
As a result, in the third embodiment, by changing the ratio of the memory diagnosis area in consideration of the clock frequency and processing load of each core, the memory diagnosis is more efficient than the first and second embodiments, and the speed is increased. Can also be realized.

[Fourth embodiment]
In the fourth embodiment, memory diagnosis is executed during the execution of a job with a fixed period.
FIG. 8 shows an example of a timing chart of memory diagnosis in the fourth embodiment. As an example, the processor 1 (the first core 11, the second core 12, etc.) Jobs such as job B every 5 msec and job C every 10 msec are executed. Note that the job priorities are job A, job B, and job C in descending order. Further, in FIG. 8, the waiting time is indicated by hatched blocks. However, in FIG. 8, for convenience of explanation, the waiting time of job C and a part of waiting time of job B are represented by hatched blocks. Further, as shown in FIG. 8, job A every 2 msec is activated five times during 10 msec, such as A1, A2, A3, A4, A5,. Further, the job B every 5 msec is activated twice during 10 msec, such as B1, B2,. Further, job C every 10 msec is activated once every 10 msec, such as C1,.

For example, when performing memory diagnosis during execution of a job C having a fixed period such as 10 msec, the processor 1 performs memory diagnosis processing in parallel in the job C.
In FIG. 8A, the processor 1 starts job A1 at time 0, and then executes jobs A2 to A5 that are started every 2 msec within 10 msec. In addition, the processor 1 starts the job B1 at the timing of time 0, but executes the job B1 after the end of the job A1 due to the waiting time. Further, the processor 1 starts the job B2 at a timing of 5 msec on the time axis, but since the waiting time is generated due to the start of the job A4, the processor 1 executes it in two steps.
Further, the processor 1 starts the job C1 at the timing of time 0, but executes the job C1 in four times during 10 msec depending on the waiting time.

  FIG. 8B shows the total execution time of jobs A, B, and C. As described above, when the memory diagnosis is performed during execution of a job with a fixed period, the memory diagnosis is performed in parallel in the job, so that the efficiency of the memory diagnosis can be realized.

  In FIG. 8, when the unit time (T1), the execution time (T2), and the idle time (T3) are assumed, the load factor (%) = (T2) / (T1) and the margin rate (%) = (T1) ) / (T2). In this case, the processor 1 may determine the ratio in the memory diagnosis in the next cycle based on the load factor (or margin rate) within the period of execution time (T2) + free time (T3). This further increases the efficiency of memory diagnosis.

[Fifth Embodiment]
In the fifth embodiment, the ratio of areas for memory diagnosis is determined in consideration of the clock frequency and processing load of each core.

In the example of the memory diagnosis process shown in FIG. 9, when the processor 1 determines the block ratio of the area to be subjected to memory diagnosis once (see FIG. 9A), the memory diagnosis is performed until the memory diagnosis for all areas is completed. Memory diagnosis may be performed without changing the ratio (see FIGS. 9B and 9C).
Specifically, in the process shown in FIG. 9, when performing memory diagnosis with a job with a fixed period of 10 msec, the processor 1 (the first core 11, the second core 12, etc.) performs the process of the flowchart shown in FIG. "Flow process").

Step S101: The processor 1 executes a predetermined calculation process. Specifically, in the processor 1, for example, each core calculates a processing load.
Step S102: The processor 1 executes a subroutine of memory diagnosis processing.
Then, the processor 1 once ends the processing of the flow shown in FIG. Then, the processor 1 again starts the processing of the flow shown in FIG. 10 in order to perform memory diagnosis with a job having a fixed period of 10 msec.

Next, a subroutine of the memory diagnosis process shown in FIG. 11 will be described.
Step S103: The processor 1 determines whether or not diagnosis has been completed for all areas of the memory to be diagnosed in the ROM 2. When the diagnosis is not completed (step S103: No), the process proceeds to step S107 described later. On the other hand, when the diagnosis is completed (step S103: Yes), the process proceeds to step S104.
Step S104: The processor 1 determines the sharing of the diagnosis area based on the clock frequency and the processing load of each core.
Step S105: The processor 1 deletes the diagnosed information in each area.
Step S106: The processor 1 initializes the counter X. The counter X is, for example, a counter value of the memory block (hereinafter the same).
Step S107: The processor 1 determines whether or not the diagnosis of the shared area of the Nth core has been completed. Here, as shown in FIG. 1, the processor 1 is a dual-core processor, and therefore, here, the first core 11 and the second core 12 are targeted. When the diagnosis ends (step S107: Yes), the memory diagnosis process subroutine ends, the process returns to step S102, and the process of the flow shown in FIG. On the other hand, when the diagnosis is not completed (step S107: No), the process proceeds to step S108.
Step S108: The processor 1 diagnoses the memory area X of the divided block based on the counter X. Here, the counter X and the memory area X are associated by an address number or the like.
Step S109: The processor 1 performs update processing of the counter X. Then, the subroutine of the memory diagnosis process is terminated, the process returns to step S102, and the process of the flow shown in FIG. 10 is temporarily terminated.

  As described above, when the ratio of the block of the area to be subjected to the memory diagnosis is determined once, the processor 1 can perform the memory diagnosis without changing the ratio until the memory diagnosis of all the areas is completed. However, if the processing load fluctuates during the memory diagnosis, the memory diagnosis time may vary.

  Therefore, in FIG. 12, the processor 1 may review the ratio of the blocks in the memory diagnosis area for each memory diagnosis cycle. Specifically, at the start of the memory diagnosis, as shown in FIG. 12A, in the memory of the ROM 2, the area where the first core 11 performs the memory diagnosis (first core area 21) is 60%, The area where the two cores 12 perform memory diagnosis (second core area 22) is 40%. After that, as shown in FIG. 12B, when the processing load of the first core 11 is reduced, the processor 1 changes the ratio of the allocation of the first core 11 from 60% to 70 with respect to the block ratio of the area to be subjected to memory diagnosis. The ratio of the second core 11 is reduced from 40% to 30%. Then, the processor 1 executes the memory diagnosis to the end (see FIG. 12C).

  Specifically, when performing memory diagnosis with a job with a fixed period of 10 msec, the processor 1 performs the processing of the flow shown in FIG. 10 described above. However, the subroutine processing in the memory diagnosis processing in step S102 is partially different from the subroutine shown in FIG. 11 described above, and will be described below based on the subroutine flowchart shown in FIG.

Step S201: The processor 1 determines whether or not diagnosis has been completed for all areas of the target memory in the ROM 2. When the diagnosis is not completed (step S201: No), the process proceeds to step S204 described later. On the other hand, when the diagnosis is completed (step S201: Yes), the process proceeds to step S202.
Step S202: The processor 1 deletes the diagnosed information in each area.
Step S203: The processor 1 executes an initialization process for the counter X.
Step S204: The processor 1 determines the sharing of the diagnosis area based on the clock frequency and the processing load of each core.
Step S205: The processor 1 determines whether or not the diagnosis of the shared area of the Nth core (the first core 11 and the second core 12) has been completed. When the diagnosis is finished (step S205: Yes), the memory diagnosis process subroutine is finished, the process returns to step S101, and the process of the flow shown in FIG. 10 is once finished. On the other hand, when the diagnosis is not completed (step S205: No), the process proceeds to step S206.
Step S206: The processor 1 diagnoses the memory area X of the divided block based on the counter X.
Step S207: The processor 1 performs update processing of the counter X. Then, the subroutine of the memory diagnosis process is terminated, the process returns to step S102, and the process of the flow shown in FIG. 10 is temporarily terminated.

When reviewing the ratio for each memory diagnosis cycle, for example, it may be every 10 msec or every 100 msec, and may be arbitrarily set as long as it is suitable for memory diagnosis.
As described above, in the fifth embodiment, the ratio of the blocks in the memory diagnosis area is determined in consideration of the clock frequency and the processing load of each core, so that the memory diagnosis can be made more efficient and faster.

[Sixth Embodiment]
In the sixth embodiment, the memory diagnosis is performed by the background processing of each core without predetermining the block ratio of the area for memory diagnosis. That is, the first core 11 and the second core 12 diagnose the next undiagnosed block when the diagnosis of the block is completed.

In the example of the memory diagnosis process in the sixth embodiment shown in FIG. 14, the first core 11 starts diagnosis of the first block (n = 1) of the ROM 2 as shown in FIG. The core 12 starts diagnosis of the second block (n = 2) of the ROM 2. In order to make the explanation easy to understand, serial numbers are given to the respective blocks in FIGS.
Here, in FIG. 14B, when the first core 11 completes the diagnosis of the first block, if the second core 12 is diagnosing the second block, the first core 11 An undiagnosed third block (n = 3) is diagnosed. In FIG. 14C, when the second core 12 finishes the diagnosis of the second block, if the first core 11 is diagnosing the sixth block (n = 6), for example, the second core 11 diagnoses the next undiagnosed seventh block (n = 7). Thereafter, the same processing is performed.

  Note that the diagnosed block determination method can be realized, for example, by having a paired flag for each memory block. The diagnosis start flag is set at the start of diagnosis, and the diagnosis end flag is set at the end of diagnosis. Thereby, the 1st core 11 and the 2nd core 12 can judge that the block in which the diagnosis start flag is not set is an undiagnosed block.

In the example of the timing chart of the memory diagnosis in the sixth embodiment shown in FIG. 15, the first core 11 and the second core 12 perform the memory diagnosis process in the free time (T3).
Specifically, the processor 1 performs the processing of the background processing flow shown in FIG. FIG. 15 is a timing chart similar to that of FIG. 8, but background processing is added.

Step S301: The processor 1 diagnoses the memory area X of the block into which the ROM 2 is divided.
Step S302: The processor 1 determines whether or not diagnosis has been completed for all areas of the target memory in the ROM 2. When the diagnosis is not completed (step S302: No), the process proceeds to step S305 described later. On the other hand, when the diagnosis is completed (step S302: Yes), the process proceeds to step S303.
Step S303: The processor 1 deletes the diagnosed information in each area.
Step S304: The processor 1 initializes the counter X. Then, the process of the flow shown in FIG. 16 ends. Then, the processor 1 starts the processing of the flow shown in FIG. 16 again when the background processing is executed. That is, the process of the flow in FIG. 16 is always repeated and executed unless an end instruction is given.
Step S305: The processor 1 performs update processing of the counter X.
Step S306: The processor 1 determines whether or not the region X is a final diagnosis. When the region X has been diagnosed (step S306: No), the process returns to step S302. On the other hand, when the region X is a final diagnosis (step S306: Yes), the processing of the flow shown in FIG. Then, the processor 1 starts the processing of the flow shown in FIG. 16 again when the background processing is executed.
As described above, in the sixth embodiment, the efficiency of memory diagnosis can be realized by performing memory diagnosis by background processing in the idle time.

[Seventh embodiment]
In the seventh embodiment, memory diagnosis is performed mutually by a plurality of cores. For example, if the result of the memory diagnosis by the first core 11 is abnormal, the second core 12 different from the first core 11 that has diagnosed the abnormality is stored in the memory area diagnosed as abnormal. Perform the diagnosis again.

  Further, in FIG. 1, the first core 11 may perform memory diagnosis of the second core area 22, and the second core 12 may perform memory diagnosis of the first core area 21. In the seventh embodiment, for the ROM2 area used by each core, other cores that do not use the ROM2 area may perform memory diagnosis.

  As described above, according to the seventh embodiment, for example, when an abnormality occurs in the first core 11, the second core 12 performs the memory diagnosis of the first core area 21. It can be seen that an abnormality occurred in one core 11. Therefore, it is possible to prevent the first core 11 in which an abnormality has occurred from erroneously diagnosing the area as normal, so that it is possible to improve the efficiency of memory diagnosis. In FIG. 1, the first core 11 and the second core 12 may perform a cross check on the first core region 21 and the second core region 22, respectively. Thereby, the accuracy of memory diagnosis can be improved.

[Eighth embodiment]
In the eighth embodiment, the memory diagnosis is performed by the RAM 3. In an example of the memory diagnosis process in the eighth embodiment, the first core 11 and the second core 12 shown in FIG. 17 divide the memory diagnosis area of the RAM 3 into two equally, for example. I do. Specifically, the first core 11 performs memory diagnosis on the first RAM area 31, and the second core 12 performs memory diagnosis on the second RAM area 32. At this time, the first core 11 and the second core 12 can appropriately apply the memory diagnostic method of any of the above embodiments.

In addition, the 1st core 11 and the 2nd core 12 are performed by the verification system which reads and compares a test value as an example of RAM diagnosis. As can be seen from FIG. 17, if the diagnosis is shared by each core, the time until the diagnosis of the entire region can be shortened. Furthermore, in the eighth embodiment, similar to the memory diagnosis of the ROM 2 described above, the diagnosis can be performed efficiently by changing the share ratio of the area to be subjected to the memory diagnosis. In the eighth embodiment, a dual core is exemplified, but the present invention is not limited to this, and other multi-core configurations may be used.
As described above, according to the eighth embodiment, the same effect as the memory diagnosis of the ROM 2 described above can be obtained in the memory diagnosis of the RAM 3.

DESCRIPTION OF SYMBOLS 1 ... Processor 11 ... 1st core 12 ... 2nd core 2 ... ROM
21 ... First core area 22 ... Second core area 3 ... RAM
4 ... Bus 100 ... Electronic control device

Claims (3)

An electronic control unit including a plurality of arithmetic units and a memory for storing data,
When each of the arithmetic devices divides the memory into a plurality of areas and performs a predetermined memory diagnosis, the processing capability of each of the arithmetic devices in any job during the execution of a plurality of fixed-cycle jobs the region of the memory allocated on the basis of, diagnose individually,
When the result of the memory diagnosis is abnormal, another arithmetic device different from the arithmetic device that diagnosed the abnormality performs the memory diagnosis again on the memory area diagnosed as abnormal. Electronic control device characterized.   The electronic control device according to claim 1, wherein the processing capability of the arithmetic device is at least one of an operating frequency and a processing load of the arithmetic device. When a plurality of arithmetic units of the electronic control unit divide the memory into a plurality of areas and perform a predetermined memory diagnosis, during execution of a plurality of jobs with a fixed period, each of the arithmetic units Individually diagnosing the areas of the memory allocated based on processing power,
When the result of the memory diagnosis is abnormal, another arithmetic device different from the arithmetic device that diagnosed the abnormality performs the memory diagnosis again on the memory area diagnosed as abnormal. A memory diagnostic method.