JP2021039666A - Core allocation device and core allocation method - Google Patents

Abstract

To provide a core allocation device and a core allocation method that enable easy appropriate allocation of tasks.SOLUTION: A feature acquisition unit 201 acquires feature information indicating features of a task from design information 211 that defines the task. An allocation unit 210 allocates the task to the core, based on the feature information and a configuration of a core in a processor.SELECTED DRAWING: Figure 3

Description

The present disclosure relates to a core allocation device and a core allocation method.

In recent years, embedded systems equipped with electronic control units (ECUs) have been required to improve control performance, respond to stricter environmental regulations, and add new arithmetic processing due to device autonomy. Along with this, the load is increasing. For this reason, even in electronic control devices, a processor having a heterogeneous multi-core (a processor having a plurality of types of cores) is used for the purpose of improving performance and the like.

Further, in an embedded system, real-time performance is required in which the calculation result by the electronic control device is transmitted to the actuator at a predetermined timing. To accommodate this, electronic controllers with heterogeneous multi-cores need to properly assign each core the task it performs so that the entire task can be completed in a shorter amount of time. There is.

Patent Document 1 discloses a task group assigning device that assigns a task group included in an application to a core in a processor having a plurality of cores having variations in performance. This task group allocation device extracts the core arrangement and core performance, generates a constraint condition that associates the extracted core arrangement and performance with whether or not the application can be executed, and refers to the constraint condition. Then, the task group previously assigned to the plurality of cores is assigned to the cores again.

Japanese Patent No. 5158447

In the technique described in Patent Document 1, the task group is appropriately assigned by repeating the assignment of the task group to the core. In addition, when assigning a task group to a core, whether or not the application can be executed is acquired from the execution log in which the task is actually executed. Therefore, in order to properly allocate the task group to the core, it is necessary to repeatedly execute the application and measure whether or not the application can be executed, and it is necessary to determine the appropriate allocation. There is a problem that it takes a lot of time.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a core allocation device and a core allocation method capable of easily assigning appropriate tasks.

The core allocating device according to one aspect of the present disclosure is a core allocating device that assigns a task to be executed by the core to a plurality of types of cores provided in the processor, and is characterized by the task from the design information that defines the task. It has a feature acquisition unit for acquiring the feature information indicating the above, and an allocation unit for allocating the task to the core based on the feature information and the configuration of the core in the processor.

According to the present invention, it becomes possible to easily assign an appropriate task.

It is a figure which shows the computer system which concerns on Example 1 of this disclosure. It is a figure which shows the hardware configuration of the core allocation device. It is a figure which shows an example of the functional configuration of a core allocation device. It is a flowchart for demonstrating an example of operation of a task classification part. It is a figure which shows an example of the classification contents of a task. It is a figure which shows the functional structure of the core type determination part. It is a figure which shows an example of a task classification result. It is a figure which shows an example of the core allocation policy. It is a figure which shows an example of the allocation information. It is a figure which shows another example of the functional configuration of a core allocation device.

Hereinafter, examples of the present disclosure will be described with reference to the drawings.

FIG. 1 is a diagram showing a computer system according to a first embodiment of the present disclosure. The computer system 100 shown in FIG. 1 includes a core allocation device 101 and an electronic control device (ECU) 102. The core allocation device 101 assigns a task to be executed by a plurality of cores (processor cores) included in the processor to the cores. The electronic control device 102 is a device having a processor in which tasks are assigned from the core allocation device 101. In this embodiment, the electronic control device 102 is mounted on the vehicle as a part of a vehicle system (not shown) that controls the vehicle, but may be mounted on another device or as a single unit. It may be used. Examples of vehicle control by the vehicle system include control of automatic driving of the vehicle.

The electronic control device 102 includes a processor 103, a memory 104, a scheduling unit 105, and a peripheral device 106.

The processor 103 has a plurality of cores 107. The core 107 executes a task in response to a task execution instruction, and outputs the execution result. In the example shown in the figure, there are N cores 107. When it is necessary to distinguish N cores 107, each core 107 is referred to as cores 107_1 to 107_N. Further, the core 107 has a plurality of types having different performances. Examples of the core type include a core type 1 which is a first type having a high processing speed and a core type 2 which is a second type having a slower processing speed than the core type 1.

The memory 104 stores various information such as an execution instruction for the core 107 and an execution result output from the core 107. The scheduling unit 105 causes each core 107 to execute a necessary task while switching the task to be executed in each core 107 based on the allocation information indicating the correspondence between each core 107 and the task to be executed in each core 107. The peripheral device 106 communicates with an external device and the like.

FIG. 2 is a diagram showing a hardware configuration of the core allocation device 101. As shown in FIG. 2, the core allocation device 101 includes a CPU (Central Processing Unit) 111, a memory 112, an auxiliary storage unit 113, an input unit 114, and a communication unit 115.

The CPU 111 realizes various functions by reading a program recorded in the memory 112 and executing the read program. The memory 112 records a program that defines the operation of the CPU 11 and various data used by the CPU 111. The auxiliary storage unit 113 stores programs and data. The programs and data stored in the auxiliary storage unit 113 are loaded into the memory 12 as needed. The input unit 114 receives various information from the user of the core allocation device 101. The communication unit 115 is communicably connected to the electronic control device 102.

FIG. 3 is a diagram showing a functional configuration of the core allocation device 101. As shown in FIG. 3, the core allocation device 101 includes a feature acquisition unit 201, a task classification unit 202, a core type determination unit 203, and a core allocation determination unit 204.

The feature acquisition unit 201 acquires feature information indicating the feature (property) of the task for each task from the design information 211 that defines each task included in the task group of the application program to be executed by each core 107 of the electronic control device 102. To do. The design information 211 is, for example, the source code of a task or an application program. The feature information may indicate a plurality of features.

The task classification unit 202, the core type determination unit 203, and the core allocation determination unit 204 are included in the task group based on the feature information acquired by the feature acquisition unit 201 and the configuration of the core 107 in the processor 103 of the electronic control device 102. The allocation unit 210 that allocates each task to the core 107 is configured. The configuration of the core 107 is, for example, the number of cores for each type of core.

The task classification unit 202 classifies each task into one of a plurality of categories based on the feature information acquired by the feature acquisition unit 201 and the task list 212 indicating each task included in the task group. Generate the classification result as the task classification result. For example, when there are a plurality of task features, the task classification unit 202 classifies the task into one of a plurality of sub-divisions for each feature, and classifies the task into one of the plurality of sub-divisions according to the combination of each sub-division. Classify into.

Based on the task classification result generated by the task classification unit 202, the core type determination unit 203 executes the core type, which is the type of the core that executes the task, and the task for each task shown in the task list 212. The number of cores, which is the upper limit of the number of cores to be executed, is determined, and type allocation information indicating the correspondence between each task and the core type and the number of cores of each task is generated.

Based on the type allocation information generated by the core type determination unit 203, the core allocation determination unit 204 performs a task to be executed by the core 107 for each of the plurality of cores 107 provided in the electronic control device 102. Allocation, and as the allocation result, allocation information indicating the correspondence between each task and the core 107 to which they are allocated is generated.

The core allocation determination unit 204 outputs the generated allocation information to the electronic control device 102 and sets it in the scheduling unit 105 of the electronic control device 102, so that the task is assigned to each core 107 of the electronic control device 102 according to the allocation information. May be executed.

The functional configuration of the core allocation device 101 shown in FIG. 3 can be realized by the hardware configuration of the core allocation device 101 shown in FIG. Further, the design information 211 and the task list 212 may be stored in the memory 112 of the core allocation device 101, the auxiliary storage unit 113, or the like.

Next, the feature information acquired by the feature acquisition unit 201 will be described. In this embodiment, the feature information shows the time constraint condition, the safety level, the drive mode, the execution interval, the processing load, and the parallelism as the features of the task in this embodiment. It should be noted that these features are merely examples, and other features may be added or some features may be excluded. For example, the feature information may include at least one of a time constraint condition, a safety level, a drive mode, an execution interval, a processing load, and parallelism as a task feature.

The time constraint condition indicates whether or not the task has a time constraint (time limit from the start to the end of the task). A task without time constraints is a best effort type task that has no explicit time constraints but is completed as soon as possible.

The safety level indicates the degree of safety assigned to the task. In this embodiment, ASIL (Automotive Safety Integrity Level) is used as the safety level. In ASIL, safety is evaluated on a five-point scale, and is called ASIL-D, ASIL-C, ASIL-B, ASIL-A, and QM (Quality Management) in order from the highest degree of safety.

The drive mode indicates the type of mode in which the task is driven. In the present embodiment, the drive mode indicates whether the task is a periodic drive that is driven periodically or an interrupt drive that is driven in response to the occurrence of a predetermined event.

The execution interval indicates the time interval in which the task is executed. The execution interval is a cycle in which the task is driven when the task is time-driven, and is a statistical value of the time interval in which the event occurs (time interval in which the task is executed) when the task is interrupt-driven. The statistical values are, for example, an average value, a maximum value, a minimum value, and the like. When the task is interrupt-driven, the execution interval at which the task is executed may be acquired by the profiler 205 described later.

The processing load indicates the degree of load on the core 107 due to the task. In this embodiment, the processing load indicates the worst execution time, which is the maximum value of the execution time from the execution of the task to the end in the core of a predetermined type.

The parallelism indicates the degree of reduction of the processing load by parallelizing the tasks (execution of the tasks in parallel by a plurality of cores 107).

FIG. 4 is a flowchart for explaining an example of the operation of the task classification unit 202. The task classification unit 202 performs the processes of steps S301 to S306 shown in FIG. 4 for each of the plurality of tasks shown in the task list 212.

First, the task classification unit 202 classifies the tasks with respect to the time constraint condition based on the feature information (step S301). In this embodiment, the task classification unit 202 classifies the task into either a "time-constrained type" having a time constraint and a "best effort type" having no time constraint.

Subsequently, the task classification unit 202 classifies the tasks regarding ASIL based on the feature information (step S302). In this embodiment, the task classification unit 202 assigns the task to "ASIL" whose assigned safety level is any of ASIL-D to ASIL-A and "QM" whose assigned safety level is QM. It is classified into one of the above. In the classification related to ASIL, the task classification unit 202 may classify the tasks into any of ASIL-D, ASIL-C, ASIL-B, ASIL-A, and QM according to the assigned safety level. Good. In addition, by classifying ASIL, it is possible to reduce the overhead of tasks required to ensure safety.

Further, the task classification unit 202 classifies the tasks with respect to the driving mode based on the feature information (step S303). In this embodiment, the task classification unit 202 classifies the task into either "periodic drive" that drives the task periodically and "interrupt drive" that drives the task in response to the occurrence of a predetermined event.

Further, the task classification unit 202 classifies the tasks regarding the execution interval based on the feature information (step S304). In this embodiment, the task classification unit 202 classifies the task into either a "long cycle" executed at a long time interval and a "short cycle" executed at a short time interval. For example, when there is a task with an execution interval of 100 ms and a task with an execution interval of 10 ms, the task classification unit 202 classifies the task with the longer execution interval (the task with the execution interval of 100 ms) into a "long cycle". , The task with the shorter execution interval (task with the execution interval of 10 ms) is classified into "short cycle". Further, when there are three or more types of task execution intervals, the task classification unit 202 may classify the tasks into any of these types. Further, the task classification unit 202 may set a task execution interval of more than or equal to a threshold value as a "long cycle" and a task execution interval of less than a threshold value as a "short cycle".

Further, the task classification unit 202 classifies the tasks regarding the processing load based on the feature information (step S305). In this embodiment, the task classification unit 202 classifies the task into either a "high load" in which the worst execution time is equal to or greater than the threshold value and a "low load" in which the worst execution time is less than the threshold value. To do. In this embodiment, the threshold value is 50% of the execution interval, but other values may be used. By classifying the processing load, it is possible to improve the cache utilization efficiency.

Then, the task classification unit 202 classifies the tasks in terms of parallelism based on the feature information (step S306). In this embodiment, the task classification unit 202 uses "parallel" in which the degree of reduction of the processing load is reduced by parallelization to a threshold value or more, and "single" in which the degree of reduction of the processing load is less than the threshold value even if the tasks are parallelized. Classify into one of. The task classification unit 202 may classify the tasks into three or more according to the degree of reduction of the processing load. For example, the task classification unit 202 may classify into one of three sub-divisions having a degree of mitigation of less than 30%, 30% or more and less than 50%, and 50% or more.

FIG. 5 is a diagram showing the classification contents of tasks according to the above operation. As shown in FIG. 5, in the above example of operation, the task is classified into "time constraint type" or "best efford type" according to the time constraint condition, and is classified into "QM" or "ASIL" according to the safety level. It is classified into "periodic drive" or "interrupt drive" according to the drive mode, "long cycle" or "short cycle" according to the execution interval, and "high load" or "low load" depending on the processing load. It is classified as "parallel" or "single" depending on the parallelism. Therefore, the tasks are classified into 64 ways.

FIG. 6 is a diagram showing a functional configuration of the core type determination unit 203. The core type determination unit 203 shown in FIG. 6 holds a task classification result 601 that is a task classification result generated by the task classification unit 202 and a core allocation policy 602 that indicates a policy for allocating a task to the core 107. .. Further, the core type determination unit 203 has a core type management unit 603.

FIG. 7 is a diagram showing an example of the task classification result 601. The task classification result 502 shown in FIG. 7 includes a field 701 that stores a task ID that identifies a task, and a field 702 that stores a task classification that is classification information indicating the task classification. The task classification shows, for example, each of the above 64 classifications.

The core allocation policy 602 is prepared in advance according to the configuration of the core 107 in the processor 103 of the electronic control device 102. Specifically, the core allocation policy 602 indicates the core type, which is the type of core to which the task of the task classification is assigned, and the number of cores, which is the upper limit of the number of cores, for each task classification. The core type assigned to the task is not limited to one type, and may be two or more types.

FIG. 8 is a diagram showing an example of the core allocation policy 602. The core allocation policy 602 shown in FIG. 8 includes a field 801 for storing a task classification, a field 802 for storing a core type, and a field 803 for storing the number of cores.

The core type management unit 603 determines the core type and the number of cores to be assigned to each task using the task classification result 601 and the core allocation policy 602, and generates type allocation information indicating the determined core type and the number of cores. When the task classification result 601 and the core allocation policy 602 are shown in FIGS. 7 and 8, taking the task whose task ID is "task 2" as an example, the task classification result 601 in FIG. 7 gives the task ID "task 2". "Category 2" is associated with the task classification, and "Category 2" is associated with "core type 1" as the core type and "4" as the number of cores according to the core allocation policy 602. Therefore, the core type management unit 603 determines that the core type assigned to the task whose task ID is "task 2" is "core type 1" and the number of cores is "4". The core type management unit 603 determines the core type and the number of cores to be assigned to each task by performing such processing for each task ID.

The core allocation determination unit 204 allocates the task to the core 107 based on the type allocation information, and outputs the allocation information which is the allocation result.

FIG. 9 is a diagram showing an example of allocation information generated by the core allocation determination unit 204. In the example of FIG. 9, there are eight cores 107 from cores 107_1 to 107_8. Cores 107_1 to 107_4 are cores of core type 1 having a high processing speed, and cores 107_1 to 107_8 are cores of core type 2 having a slow processing speed.

As for the "best effort type task", if it is executed in an appropriate time division manner, there is no problem even if it is executed in any core 107 regardless of the core type. Therefore, the "best effort type task" is assigned to the cores 107_1 to 107_8 regardless of other features.

Further, regarding the "time-constrained task", in the example of the figure, when the safety level is "QM", it is executed in large quantities, that is, the execution interval is "short cycle". Therefore, the task having the safety level "QM" is assigned to the cores 107_1 to 107_4 of the core type 1 having a high processing speed. At this time, the "QM parallel execution task", which is a task whose concurrency is "parallel", is assigned to a plurality of (4 in the example of the figure) cores 107_1 to 107_4, and is a task whose concurrency is "single". One "QM task" is assigned to each of the cores 107_1 to 107_3.

Further, the "ASIL task", which is a task having a safety level of "ASIL", is assigned to one of the cores 107_1 to 107_4 of the high-speed core type 1 when the processing load is "high load", and the processing load is "". In the case of "low load", it is assigned to any of the cores 107_5 to 107_8 of the low-speed core type 2.

In addition to the tasks of the application program, the core allocation device 101 may allocate processing related to the OS (Operating System), processing related to BSW, and the like to the core 107. In the example of FIG. 9, the core allocation determination unit 204 classifies "ASIL OS", which is a process of the OS to which ASIL is assigned, and "ASIL BSW", which is a process of BSW to which ASIL is assigned, into core types. It is assigned to 2 cores.

According to the present embodiment described above, the task is assigned to the core 107 based on the feature information of the task acquired from the design information 211 of the task. Therefore, it is possible to appropriately assign a task without repeating the execution of the task, and it is possible to easily assign an appropriate task.

Further, in this embodiment, the task is classified into one of a plurality of categories based on the feature information of the task, and the type and the number of cores 107 to which the task is assigned are determined based on the category. Therefore, it becomes possible to reduce the number of combinations of correspondences between the task and the core 107 that executes the task, and it becomes possible to more easily assign an appropriate task. Therefore, it is possible to determine the task assignment in a short time.

Further, in the present embodiment, since the feature information indicates a plurality of features, the task can be assigned by appropriately considering the task features. In addition, the features are at least the time constraint condition of the task, the safety required for the task, the driving mode in which the task is executed, the execution interval in which the task is executed, the processing load due to the execution of the task, and the concurrency of the task. Including one. Therefore, tasks can be assigned appropriately.

This embodiment is different from the first embodiment in that the feature acquisition unit 201 receives designated information that specifies the features of the task used for core allocation.

When the feature acquisition unit 201 receives the designated information, the feature acquisition unit 201 acquires the feature information from the design information 211 based on the designated information. Specifically, the feature acquisition unit 201 acquires the feature information indicating the feature specified in the designated information from the design information 211.

The designated information can be received from the user using the input unit 114. For example, when there is only one core 107 mounted on the electronic control device 102 for each core type, the user can use the features (time constraint condition, safety level, drive mode, execution interval, etc.) described in the first embodiment. Processing load and parallelism) may be specified by excluding parallelism. Also, when the electronic control device 102 is used for important purposes such as controlling the automatic driving of a vehicle, the time constraint is important, but the deadline at which the task ends is not important. Time constraints may not be important when used for non-existent applications. In this case, the user can specify a feature described in the first embodiment excluding the time constraint condition.

According to the present embodiment described above, since the features to be used can be selected according to the type and application of the electronic control device 102, unnecessary classification can be reduced and processing capacity due to unnecessary allocation constraints can be selected. It becomes possible to suppress the decrease of.

In this embodiment, the first specific example of the method in which the feature acquisition unit 201 acquires the feature information related to the processing load will be described.

In the method of this embodiment, by executing each task using the electronic control device 102, the worst execution time is measured as the processing load of each task, and the measured worst execution time is incorporated in the design information 211 in advance. .. In this case, the feature acquisition unit 201 acquires the feature information related to the "processing load" by extracting the worst execution time from the design information 211. In addition, it is also possible to acquire the feature information related to the execution interval when the task is interrupt-driven by the same method.

According to the present embodiment described above, even when it is difficult to predict the processing load of a task from information such as source code, it is possible to acquire feature information related to the processing load.

In this embodiment, a second specific example of the method in which the feature acquisition unit 201 acquires the feature information related to the processing load will be described.

In the method of this embodiment, the feature acquisition unit 201 refers to the source code of the task included in the design information 211, and predicts the processing load based on the source code amount which is the scale of the source code. Specifically, the feature acquisition unit 201 predicts the worst execution time, which is a processing load, based on the function execution time required to execute a predetermined function included in the source code and the amount of the source code. For example, the feature acquisition unit 201 predicts the worst execution time by obtaining the number of lines of the source code as the amount of source code and multiplying the number of lines by the time corresponding to the function execution time. The function execution time may be held by the feature acquisition unit 201, for example, or may be incorporated in the design information 211 in advance.

When the task design information 211 includes control statements such as repetitive statements and branch statements, the feature acquisition unit 201 may predict the processing load in consideration of the control statements. For example, when the design information 211 includes a repetitive statement, the feature acquisition unit 201 corrects the source code amount by multiplying the number of lines of the repetitive statement by the number of times the process corresponding to the repetitive statement is repeated, and corrects the amount. Predict the processing load based on the amount of source code. When the design information 211 includes a branch statement, the feature acquisition unit 201 corrects the source code amount by dividing the number of lines of the branch statement by the number of processes branched by the branch statement. Predict the processing load based on the corrected amount of source code.

According to the present embodiment described above, feature information related to the processing load can be acquired even when there is no environment for measuring the processing load of the task.

In this embodiment, a third specific example of the method in which the feature acquisition unit 201 acquires the feature information related to the processing load will be described.

In the method of this embodiment, the feature acquisition unit 201 refers to the assembler code of the task included in the design information 211, and predicts the processing load based on the number of instructions requested to be executed by the task. Specifically, the feature acquisition unit 201 calculates the instruction execution time, which is the execution time per instruction, from the clock frequency of the core 107, the number of pipeline stages, the number of cycles required for memory access, and the like, and the instruction execution time and the instruction execution time are calculated. The worst execution time, which is the "processing load", is predicted based on the number of instructions. For example, the feature acquisition unit 201 predicts the worst execution time by multiplying the time corresponding to the instruction execution time by the number of instructions.

When the task design information 211 includes control statements such as repetitive statements and branch statements, the feature acquisition unit 201 may predict the processing load in consideration of the control statements. For example, when the design information 211 includes a repetitive statement, the feature acquisition unit 201 corrects the number of instructions by multiplying the number of instructions included in the repetitive statement by the number of times the process corresponding to the repetitive statement is repeated. Predict the processing load based on the corrected number of instructions. When the design information 211 includes a branch statement, the feature acquisition unit 201 corrects the number of instructions by dividing the number of instructions included in the branch statement by the number of processes branched by the branch statement. The processing load is predicted based on the corrected number of instructions.

According to the present embodiment described above, feature information related to the processing load can be acquired even when there is no environment for measuring the processing load of the task.

In this embodiment, a fourth specific example of the method in which the feature acquisition unit 201 acquires the feature information related to the processing load will be described.

In the method of this embodiment, the feature acquisition unit 201 refers to the source code of the task included in the design information 211, and predicts the processing load based on the number of predetermined functions included in the source code. The predetermined function is, for example, a function having a large load.

Specifically, the feature acquisition unit 201 predicts the worst execution time, which is a processing load, based on the function execution time required to execute a predetermined function included in the source code and the number of predetermined functions. For example, the feature acquisition unit 201 predicts the worst execution time by multiplying the number of predetermined functions by the time corresponding to the function execution time. The function execution time may be held by the feature acquisition unit 201, for example, or may be incorporated in the design information in advance.

When the task design information 211 includes control statements such as repetitive statements and branch statements, the feature acquisition unit 201 may predict the processing load in consideration of the control statements. For example, when the design information 211 includes a repetitive statement, the feature acquisition unit 201 multiplies the number of predetermined functions included in the repetitive statement by the number of times the process corresponding to the repetitive statement is repeated to obtain the predetermined function. The number is corrected, and the processing load is predicted based on the corrected number of predetermined functions. When the design information 211 includes a branch statement, the feature acquisition unit 201 divides the number of predetermined functions included in the branch statement by the number of processes branched by the branch statement to obtain a predetermined function. The quantity of is corrected, and the processing load is predicted based on the corrected number of predetermined functions.

According to the present embodiment described above, feature information related to the processing load can be acquired even when there is no environment for measuring the processing load of the task.

In this embodiment, a specific example of a method in which the feature acquisition unit 201 acquires feature information related to parallelism will be described.

In the method of this embodiment, the feature acquisition unit 201 analyzes the source code of the task included in the design information and identifies a parallel portion that can be executed in parallel by a plurality of cores in the source code. Then, based on the parallel part, the feature information about the concurrency is acquired. For example, the feature acquisition unit 201 determines that the degree of reduction of the processing load is equal to or more than the threshold value when the number of lines in the parallel portion in the source code is equal to or more than a predetermined value, and processes when the number of rows in the parallel portion is less than the predetermined value. It is judged that the load reduction degree is less than the threshold value. The predetermined value is, for example, 20% of the total number of lines in the source code.

As described above, according to the present embodiment, it is possible to acquire the feature information related to the parallelism of the tasks even when the parallelism of the tasks is not defined in the design information 211.

This embodiment is different from the first embodiment in that the assignment of the task to the core 107 is determined once and then changed.

FIG. 10 is a diagram showing a functional configuration of the core allocation device 101 according to the present embodiment. The core allocating device 101 shown in FIG. 10 further includes a profiler 205 in addition to the configuration of the core allocating device 101 according to the first embodiment shown in FIG.

The profiler 205 executes and actually measures the execution time required for executing each task from the execution log 213, which is the history of the electronic control device 102 executing the task according to the allocation information generated by the core allocation determination unit 204. It is an analysis unit that extracts as a value. When the task is executed a plurality of times, the profiler 205 may extract the statistical value (for example, the average value or the maximum value) of the measured value of each execution time as the executed measured value.

When the execution log 213 has not been generated yet, that is, when the allocation information has not been generated yet, the allocation unit 210 generates the allocation information and outputs it to the electronic control device 102 in the same manner as in the first embodiment.

After that, when the electronic control device 102 executes the task and generates the execution log 213, the allocation unit 210 uses the feature information acquired by the feature acquisition unit 201 and the actual execution value of each task acquired by the profiler 205 from the execution log 213. Based on, each task is assigned to the core 107, and the allocation information which is the allocation result is output.

Specifically, the task classification unit 202 classifies each task again based on the feature information acquired by the feature acquisition unit 201 and the actual execution measurement value of each task acquired by the profiler 205. For example, the task classification unit 202 classifies the execution actual measurement value in addition to the classification according to each feature indicated by the feature information. In the classification related to the actual execution measurement value, for example, the task classification unit 202 compares the actual execution measurement value with the worst execution time, which is the processing load, and determines that the actual execution measurement value is "more than expected", which is equal to or longer than the worst execution time. Classify as one of "less than expected", which is less than the worst execution time.

The core type determination unit 203 regenerates the type allocation information by further using the classification related to the actual measurement value. For example, the core type determination unit 203 holds, as the core allocation policy 602, a first core allocation policy that does not include the classification related to the actual measurement value and a second core allocation policy that includes the classification related to the actual measurement value. The core type determination unit 203 generates type allocation information using the first core allocation policy when the execution measurement value is not classified, and when the execution measurement value is classified, the second core allocation is performed. Generate type assignment information using the policy.

The task classification unit 202 updates the worst execution time, which is the processing load included in the feature information acquired by the feature acquisition unit 201, to the actual execution time value, and executes the task classification unit 202 based on the updated feature information indicating the worst execution time. Similar to Example 1, classification may be performed according to each feature indicated by the feature information. In this case, the operations of the core type determination unit 203 and the core allocation determination unit 204 are the same as those in the first embodiment.

According to the present embodiment described above, the task can be assigned to the core 107 based on the measured value of the processing load of the task. As a result, the task can be assigned in consideration of the compatibility between the core 107 and the task.

The present embodiment differs from the eighth embodiment in that the execution log 213 is updated in real time. The execution log 213 is updated every time a task is executed by the scheduling unit 105 of the electronic control device 102, for example. In the case of this embodiment, the core allocation device 101 may be arranged in the vehicle system together with the electronic control device 102.

The profiler 205 extracts the actual execution value from the execution log 213 every time the execution log 213 is updated or at regular intervals.

When the profiler 205 extracts the execution measurement value, the allocation unit 210 allocates each task to the core 107 based on the execution measurement value and the feature information acquired by the feature acquisition unit 201, and regenerates the allocation information. The allocation unit 210 updates the execution log 213 by outputting the generated allocation information to the electronic control device 102 and causing each core 107 of the electronic control device 102 to execute a task according to the allocation information.

It is desirable that the scheduling unit 105 of the electronic control device 102 updates the allocation information used for task scheduling to the allocation information from the allocation unit 210 during driving. In this case, the scheduling unit 105 performs scheduling based on the updated allocation information in order from the task for which the processing is completed. Further, the core 107 executing the task executes the task based on the updated allocation information after the task is completed.

According to the present embodiment described above, the task can be assigned to the core 107 based on the measured value of the processing load of the task. Further, since the assignment of the task to the core 107 can be dynamically updated, the task can be assigned in response to changes in the environment or the like.

The embodiments of the present disclosure described above are examples for the purpose of explaining the present disclosure, and the scope of the present disclosure is not intended to be limited only to those embodiments. One of ordinary skill in the art can practice the present invention in various other aspects without departing from the scope of the present invention.

100: Computer system, 101: Core allocation device, 102: Electronic control device, 103: Processor, 104: Memory, 105: Scheduling unit, 106: Peripheral device, 107: Core, 201: Feature acquisition unit, 202: Task classification unit , 203: Core type determination unit, 204: Core allocation determination unit, 205: Profiler, 210: Assignment unit

Claims (8)

A core allocation device that assigns tasks to be executed by multiple types of cores provided by a processor.
A feature acquisition unit that acquires feature information indicating the features of the task from the design information that defines the task, and
A core allocation device having an allocation unit that allocates the task to the core based on the feature information and the configuration of the core in the processor. The allocation unit
A classification unit that classifies the task into any of a plurality of categories based on the feature information,
A type determination unit that determines the type and number of cores that execute the task based on the task classification and the core configuration.
The core allocation device according to claim 1, further comprising an allocation determination unit that allocates the task to the core based on the determination result of the type determination unit. The core allocation device according to claim 1, wherein the feature information indicates a plurality of the features. The core allocation device according to claim 1, wherein the feature acquisition unit receives designated information for designating the feature and acquires the feature information based on the designated information. The features are the time constraint condition of the task, the safety required for the task, the driving mode in which the task is executed, the execution interval in which the task is executed, the processing load due to the execution of the task, and the task. The core allocation device according to claim 1, which comprises at least one of the parallelisms of the above. The processor further has an analysis unit that extracts the execution time required for the execution of the task from the execution log of executing the task according to the allocation result of the task by the allocation unit.
The core allocation device according to claim 1, wherein the allocation unit allocates the task to the core based on the feature information and the execution time. The allocation unit updates the execution log by causing the processor to execute the task according to the allocation result.
The core allocation device according to claim 6, wherein the analysis unit extracts the execution time based on the execution log updated by the allocation unit. This is a core allocation method using a core allocation device that allocates tasks to be executed by the cores of multiple types provided by the processor.
From the design information that defines the task, the feature information indicating the feature of the task is acquired, and the feature information is obtained.
A core allocation method for allocating the task to the core based on the feature information and the configuration of the core in the processor.

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