JP2007323142A - Information processing apparatus and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing apparatus which has a plurality of virtual machines and which, even for a serious error regarding the operation of the particular virtual machine, is capable of continuing the operation of the other virtual machines unaffected by the error. <P>SOLUTION: The information processing apparatus having a plurality of virtual machines has: an associating means for associating the particular virtual machine with hardware used by the particular virtual machine; an error detecting means for detecting errors with the hardware used by the particular virtual machine; and an operation stopping means for stopping, upon detection of an error, the operation of the virtual machine associated with the hardware. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an information processing apparatus and a control method thereof, and more particularly, to an information processing apparatus including a virtual machine environment and a control method thereof.

  An information processing apparatus such as a personal computer or a server is usually configured to include a CPU, a main memory, and various peripheral devices connected to these via an appropriate bus. If an error occurs for some reason in the main memory or peripheral device, or if a communication error such as a parity error occurs with the peripheral device, the occurrence of these errors is detected and the detected error In the case of a serious error, defensive measures such as shutting down the system are often taken to prevent further damage.

  It is difficult to make the error occurrence itself completely zero. Therefore, it is a very important technical problem for the information processing apparatus to minimize the influence of an error when it occurs, and to easily identify the location where the error occurs.

  For example, Patent Document 1 discloses a technique relating to error processing when a communication error is detected on a PCI bus frequently used in recent information processing apparatuses.

  In the technique disclosed in Patent Document 1, when a parity error or the like is detected on the PCI bus, not only the error is detected and the system is stopped, but also the PCI device causing the parity error is specified and the record is left. Thus, maintenance work such as repair and replacement of the PCI device can be facilitated.

  On the other hand, recent information processing apparatuses, particularly servers, are adopting the concept of information processing called virtual machines.

  In a virtual machine, hardware such as a main memory and peripheral devices connected to the virtual machine is virtualized as software, and the virtualized hardware (actually software) is controlled on an OS called a guest OS. I'm taking it. The virtualized hardware and the actual hardware are associated by software called a virtual machine monitor (hereinafter referred to as VMM (Virtual Machine Monitor)).

  A virtual machine that operates on the guest OS can also operate under the management of the host OS. In this case, the VMM operates under the management of the host OS.

  Normally, one information processing apparatus has one host OS, but this host OS can handle a plurality of virtual machines (that is, a plurality of guest OSs).

  For example, Windows XP (Windows (registered trademark)) of Microsoft Corporation is used as a host OS, and a plurality of different types of guest OSs such as Windows 98 (Windows (registered trademark)) and UNIX (registered trademark) are operated under the management. It is possible. With such a configuration, a new OS can be used as the host OS, while an old OS that is no longer supported is continuously used as the guest OS.

  In addition, while using an old OS with a relatively low security function as a guest OS, using a new OS with a high security function as a host OS enables high security for the entire information processing apparatus. Become.

Thus, there are many advantages of virtual machines, and some of them are already provided as products such as “VMware” of VMware and “Virtual Server” of Microsoft. If the overhead processing time unique to the virtual machine is shortened along with the improvement of the CPU capability, it is expected that it will become more popular in the future.
Japanese Patent Laid-Open No. 2003-22222

  By the way, when a serious error such as an uncorrectable memory error is detected, the process of stopping the entire system is the same in the form of an information processing apparatus having a plurality of virtual machines. Normally, for multiple virtual machines, the actual physical memory area is divided into multiple parts, and the divided areas are assigned to each virtual machine, but if an error occurs in the memory, that area and the virtual machine In the past, no measures were taken so that the entire system including all virtual machines could only be stopped.

  The present invention has been made in view of the above circumstances, and in an information processing apparatus having a plurality of virtual machines, even when a serious error relating to the operation of a specific virtual machine occurs, the influence of the error is reduced. An object of the present invention is to provide an information processing apparatus and a control method thereof that can continue the operation of another virtual machine that is not received.

  In order to solve the above problems, an information processing apparatus according to the present invention is used by a specific virtual machine and the specific virtual machine in an information processing apparatus having a plurality of virtual machines as described in claim 1. Associating means for associating with hardware, error detecting means for detecting an error in hardware used by the specific virtual machine, and operation of the virtual machine associated with the hardware when the error is detected And an operation stop means for stopping.

  In order to solve the above problems, an information processing apparatus control method according to the present invention includes a specific virtual machine and a control method for an information processing apparatus including a plurality of virtual machines. An associating step of associating with hardware used by the specific virtual machine, an error detecting step of detecting an error in hardware used by the specific virtual machine, and associating with the hardware when the error is detected And an operation stop step for stopping the operation of the virtual machine.

  According to the information processing apparatus and the control method thereof according to the present invention, even if a serious error related to the operation of a specific virtual machine occurs in the information processing apparatus including a plurality of virtual machines, The operation of other virtual machines that are not affected can be continued.

  An information processing apparatus 1 and a control method thereof according to an embodiment of the present invention will be described with reference to the accompanying drawings.

(1) Configuration FIG. 1 is a diagram illustrating an example of a system configuration of the information processing apparatus 1, and is a diagram specifically illustrating the configuration of software.

  The information processing apparatus 1 according to the present embodiment includes a plurality of virtual machines (including n + 1 virtual machines from the virtual machine 0VM0 to the virtual machine nVMn in the example of FIG. 1).

  The information processing apparatus 1 includes hardware 3 (see FIG. 2 for a detailed example) and software 2. The software 2 includes a plurality of virtual machines (VM0 to VMn) and a virtual machine monitor VMM that associates these virtual machines with actual hardware.

  Each virtual machine (hereinafter simply referred to as a virtual machine VM when collectively referring to virtual machines (VM0 to VMn)) includes an OS called a guest OS (guest OS (0) GOS0 to guest OSGOSn). Each virtual machine VM operates under this guest OS.

  The guest OS of each virtual machine VM is, for example, Windows (registered trademark), Linux (registered trademark), UNIX, or the like. The guest OS used in each virtual machine VM may be a different type of OS or the same. It may be a type of OS.

  Under the virtual machine environment, the guest OS does not directly access the actual hardware 3, but accesses the virtualized (softwareized) hardware. Hardware virtualization is performed by the virtual machine monitor VMM. The virtual machine monitor VMM also associates virtualized hardware with actual hardware 3.

  In each virtual machine VM, various application software (App0 to Appm) operates under the management of the guest OS. Different types of application software (App0 to Appm) may be used for each virtual machine VM, or overlapping types of application software may be used.

  In the example of FIG. 1, a host OS 4 is further provided. The host OS 4 is an OS used in a normal environment (that is, an environment that is not a virtual machine environment), and is called a host OS to distinguish it from a guest OS. Similarly to the guest OS, the host OS is, for example, Windows, Linux, UNIX, or the like. Normal application software (App0 to Appm) also operates under the management of the host OS. The virtual machine monitor VMM also operates under the management of the host OS 4.

  Note that the host OS may not be provided, that is, the virtual machine VM, the virtual machine monitor VMM, and the hardware 3 may be included.

  FIG. 2 is a diagram showing an emphasis on the configuration example of the hardware 3 in the configuration of the information processing apparatus 1.

  The hardware 3 includes, for example, a CPU 31, a chip set (MCH) 32 (MCH: Memory Control Hub), and a chip set (ICH) 33 (ICH: I / O Control Hub). In addition to the main memory 34, a video controller 35 is connected to the chip set (MCH) 32 via the BUS 1. A display 39 is further connected to the video controller 35.

  The main memory 34 is configured by, for example, a DIMM (Dual In-line Memory Module) with ECC (Error Correction Code).

  On the other hand, to the chip set (ICH) 33, for example, a LAN card 36 is connected via BUS2, an IDE controller 37 via BUS3, and a SCSI controller 38 via BUS4. The IDE controller 37 is connected to IDE devices such as a hard disk drive (HDD) 41 and an optical disk (not shown), and various SCSI devices 42 are connected to the SCSI controller 38.

  BUS1 to BUS4 are PCI buses such as a PCI bus, a PCI-X bus, a PCI Express bus, and the like.

  FIG. 3 is a block diagram illustrating a configuration example of the function realizing unit of the information processing apparatus 1 according to the present embodiment, and is a block diagram relating to the function realizing unit that is particularly characteristic of the present invention.

  The information processing apparatus 1 includes an error detection unit 51, an association unit 52, an association table 53, and an operation stop unit 54.

  The error detection means 51 is a means for detecting hardware errors such as memory errors and bus communication errors. Specifically, in the case of a memory error, the chip set (MCH) 32 to which the main memory 34 is connected becomes the error detection means 51. Further, in the case of a bus communication error, for example, a parity error of a PCI bus called SERR or PERR, the chip set (ICH) 33 or chip set (MCH) 32 connected to the PCI bus system (BUS1 to BUS4) has an error. It becomes a detection means.

  By the way, when a serious error such as a memory error or a parity error is detected by the chip sets 32 and 33, the chip set is normally set to generate an SMI (System Management Interrupt) interrupt. When an SMI interrupt occurs, this SMI interrupt is notified directly to the BIOS without going through the OS, and the BIOS is configured to activate the SMI handler in the BIOS and stop the entire system of the information processing apparatus 1. .

  On the other hand, by changing the settings for the chip sets 32 and 33, an interrupt called an SCI (System Control Interrupt) interrupt can be generated instead of the SMI interrupt. This SCI interrupt can be notified to the OS or the virtual machine monitor VMM instead of the BIOS.

  In the information processing apparatus 1 according to the present embodiment, the chip sets 32 and 33 are set so as to generate an SCI interrupt when a memory error, a parity error, or the like is detected. The generated SCI interrupt is notified to the virtual machine monitor VMM. That is, in the present embodiment, even when a memory error, a parity error, or the like occurs, the entire system of the information processing apparatus 1 is not stopped (by a normal SMI interrupt setting).

  The SCI interrupt is notified to the association unit 52 of the virtual machine monitor VMM. When recognizing the SCI interrupt, the associating unit 52 reads the registers of the chip sets 32 and 33 and specifies the location where the error has occurred. For example, in the case of a memory error, the memory address where the error has occurred is specified. In the case of a parity error, the bus in which the parity error has occurred is specified.

  On the other hand, the virtual machine monitor VMM recognizes hardware used by each virtual machine VM. The virtual machine monitor VMM has a function of associating the virtual machine VM with actual hardware. For example, with respect to the main memory 34, as illustrated in FIG. 4, the area of the main memory 34 is divided in advance for the virtual machine monitor VMM and each virtual machine VM (VM0 to VNn), and each virtual machine VM can be used. Is allocated to each virtual machine VM. An association table (memory allocation table) 53 that associates the address area in the main memory 34 with each virtual machine VM is held.

  FIG. 5 is a diagram illustrating an example of the memory allocation table 53. In this example, for example, an area from the start address 4000_0000h to the end address 7FFF_FFFFh is assigned to the virtual machine VM0, and an area from the start address 8000_0000h to the end address BFFF_FFFFh is assigned to the virtual machine VM1.

  When the address 52 in which the memory error has occurred is specified, the associating unit 52 of the virtual machine monitor VMM refers to the memory allocation table 53 and specifies the virtual machine VM using the corresponding address.

  For example, when the address where the memory error occurs is 8000_0FFFh, the virtual machine VM using the address is specified as the virtual machine VM1.

  The operation stop unit 54 is a unit that issues an instruction to stop the specified virtual machine VM, for example, the virtual machine VM1.

  Specifically, the operation stop unit 54 of the virtual machine monitor VMM generates an NMI (Non-Maskable Interrupt) interrupt only for the guest OS of the virtual machine VM1, and stops the operation of the virtual machine VM1. An NMI interrupt is not generated for other virtual machines VM (virtual machine VM to which a normal memory area is allocated). As a result, only the virtual machine VM1 that uses the area where the memory error has occurred stops its operation, and the other virtual machines VM can continue its operation.

(2) Operation The operation (control method) of the information processing apparatus 1 configured as described above will be described using a flowchart.

  FIG. 6 is a flowchart for explaining the operation when a memory error occurs as a first operation example. FIG. 7 shows the location of the operation on the configuration diagram. The numbers in circles in FIG. 7 correspond to the step numbers in FIG.

  First, it is assumed that a memory error has occurred in the memory allocated to the virtual machine VM1 (step ST1).

  The chip set (MCH) 32 detects that a memory error has occurred (step ST2). Here, the memory error means an error that cannot be corrected when the main memory 34 is a memory with an error correction function.

  Next, the chip set (MCH) 32 generates an SCI interrupt and notifies the virtual machine monitor VMM (step ST3).

  The virtual machine monitor VMM that has received the notification reads the register of the chip set (MCH) 32 and acquires an error address (step ST4).

  Further, the virtual machine monitor VMM compares the acquired error address with the memory allocation table, and detects that an error has occurred in the memory allocated to the virtual machine VM1 (step ST5).

  Thereafter, the virtual machine monitor VMM generates an NMI interrupt for the guest OS of the virtual machine VM1 and stops the operation of the virtual machine VM1 (step ST6). Note that other virtual machines VM other than the virtual machine VM1 continue to operate.

  FIG. 8 is a flowchart for explaining the operation when a parity error occurs in the PCI bus as a second operation example. FIG. 9 shows the location of the operation on the configuration diagram. The numbers in the circles in FIG. 9 correspond to the first digit of the step number in FIG.

  First, it is assumed that the virtual machine VM1 accesses the HDD 41 of the IDE controller 37 (step ST11).

  In response to this, the virtual machine monitor VMM tries to access the IDE controller 37 (step ST12).

  At this time, it is assumed that a SERR indicating a parity error has occurred on the PCI bus (BUS3) to which the IDE controller 37 is connected (step ST13).

  When SERR is generated in the PCI bus, the chip set (ICH) 33 detects SERR (step ST14).

  Thereafter, the chip set (ICH) 33 generates an SCI interrupt to the virtual machine monitor VMM (step ST15).

  When receiving the SCI interrupt, the virtual machine monitor VMM reads the register of the chip set (ICH) 33 and detects that the SERR has occurred in BUS3 (step ST16).

  The virtual machine monitor VMM stops the operation of the virtual machine VM1 that has accessed BUS3 (actually, the HDD 41 connected to BUS3) (step ST17).

Note that other virtual machines VMs other than the virtual machine VM1 that has not accessed the BUS3 in which the SERR has occurred continue to operate.

  In addition to SERR, there is PERR as a parity error defined on the PCI bus. In this case as well, the operation of the virtual machine VM1 may be stopped by the same processing as the above SERR.

  By the way, in the second operation example described above, when a parity error occurs in BUS3 accessed by the virtual machine VM1, the operation of the virtual machine VM1 is stopped.

  On the other hand, if another virtual machine VM, for example, virtual machine VM2 tries to access BUS3 after a parity error has occurred in BUS3, a serious failure may occur in virtual machine VM2. In such a case, it is possible to avoid a failure by stopping the operation of the virtual machine VM2.

  In order to realize this operation, the virtual machine monitor VMM may have a bus management table as illustrated in FIG.

  FIG. 10A shows an initial state of the bus management table, and all buses (for example, BUS1 to BUS4) are set to “normal”.

  During the operation, for example, when an abnormality of BUS3 is detected by access from the virtual machine VM1, the operation of the virtual machine VM1 is stopped and, as shown in FIG. 10B, the bus “ Change the column “3” to “abnormal”.

  When there is an access to BUS3 from another virtual machine VM, for example, virtual machine VM2, the virtual machine monitor VMM refers to this bus management table and confirms that BUS3 is abnormal, and then BUS3 The operation of the virtual machine VM2 that accessed is stopped. Thereby, it is possible to prevent a serious failure from occurring in the virtual machine VM2 in advance.

  As described above, according to the information processing apparatus 1 and the control method thereof according to the present embodiment, when a serious error related to the operation of a specific virtual machine occurs in the information processing apparatus including a plurality of virtual machines. Even so, the operation of another virtual machine that is not affected by the error can be continued.

  Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, the constituent elements over different embodiments may be appropriately combined.

1 is a diagram illustrating an example of a system configuration of an information processing apparatus according to an embodiment of the present invention, and particularly illustrates a software configuration with emphasis. 1 is a diagram illustrating a system configuration example of an information processing apparatus according to an embodiment of the present invention, and particularly illustrates a hardware configuration. The block diagram which shows the structural example of the function implementation | achievement means in the information processing apparatus which concerns on one Embodiment of this invention. 1 is a diagram illustrating an example of a system configuration of an information processing apparatus according to an embodiment of the present invention, and more particularly, a diagram that focuses on area allocation of a main memory. The figure which shows an example of the memory allocation table with which a virtual machine monitor is provided. The flowchart which shows the process example (1st operation example) when a memory error generate | occur | produces in the main memory. The figure explaining the process example (1st operation example) when a memory error generate | occur | produces in the main memory using a system block diagram. The flowchart which shows the process example (2nd operation example) when a parity error generate | occur | produces in the PCI bus. The figure explaining the process example (2nd operation example) when a parity error generate | occur | produces in a PCI bus using a system block diagram. The figure which shows an example of the bus management table with which a virtual machine monitor is provided.

Explanation of symbols

1 Information processing device 31 CPU
32 Chipset (MCH)
33 Chipset (ICH)
34 Main memory 37 IDE controller 41 HDD
51 Error Detection Unit 52 Association Unit 52 Operation Stop Unit 53 Association Table (Memory Allocation Table)
VM0 to VMn Virtual machine (0) to Virtual machine (n)
VMM virtual machine monitor GOS0 to GOSm Guest OS (0) to Guest OS (n)

Claims (14)

In an information processing apparatus including a plurality of virtual machines,
An association means for associating a specific virtual machine with hardware used by the specific virtual machine;
Error detection means for detecting an error in hardware used by the specific virtual machine;
An operation stopping means for stopping the operation of the virtual machine associated with the hardware when the error is detected;
An information processing apparatus comprising: The hardware is main memory;
The associating means is means for dividing the area of the main memory, assigning the divided areas to the respective virtual machines, and associating them.
The operation stop means stops the operation of the virtual machine assigned to the area where the error is detected.
The information processing apparatus according to claim 1. The main memory is a memory with an error correction function,
The operation stop means stops the operation of the virtual machine when the detected error is uncorrectable.
The information processing apparatus according to claim 2. The hardware error is a bus communication error of a PCI device used by the specific virtual machine.
The information processing apparatus according to claim 1. The PCI device communication error is SERR or PERR.
The information processing apparatus according to claim 4. The hardware error is a PCI device bus communication error used by the specific virtual machine,
Means for stopping the operation of the other virtual machine to be accessed when another virtual machine tries to access the bus of the PCI device in which the error is detected;
The information processing apparatus according to claim 1, further comprising: The error detection means is an error detection means by a chip set, and the chip set notifies the operation stop means by an SCI interrupt when an error is detected, not by an SMI interrupt.
The information processing apparatus according to claim 1. In a control method for an information processing apparatus including a plurality of virtual machines,
Associating a specific virtual machine with the hardware used by the specific virtual machine;
An error detection step of detecting a hardware error used by the specific virtual machine;
An operation stop step for stopping the operation of the virtual machine associated with the hardware when the error is detected;
An information processing apparatus control method comprising: The hardware is main memory;
The associating step is a step of dividing the area of the main memory, assigning the divided area to the respective virtual machines, and associating them.
The operation stop step stops the operation of the virtual machine assigned to the area where the error is detected.
The information processing apparatus control method according to claim 8. The main memory is a memory with an error correction function,
The operation stop step stops the operation of the virtual machine when the detected error is uncorrectable.
The information processing apparatus control method according to claim 9. The hardware error is a bus communication error of a PCI device used by the specific virtual machine.
The information processing apparatus control method according to claim 8. The PCI device communication error is SERR or PERR.
The method of controlling an information processing apparatus according to claim 11. The hardware error is a PCI device bus communication error used by the specific virtual machine,
A step of stopping the operation of the other virtual machine to be accessed when another virtual machine tries to access the bus of the PCI device in which the error is detected;
The information processing apparatus control method according to claim 8, further comprising: The operation stop step is an error detection step by a chipset. When the chipset detects an error, the chipset notifies the operation stop step by an SCI interrupt instead of an SMI interrupt.
The information processing apparatus control method according to claim 8.

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