JP4656080B2 - System parts for information processing equipment - Google Patents

Description

The present invention relates to a virtual computer system that operates a plurality of OSes on a single computer,
Prevention of malfunction due to unauthorized access between OSs, processing method when an error occurs, and
It relates to the computer system using them.

US Patent Publication US2002 / 0010811A1
Logical partitioning is a technique for operating multiple operating systems (hereinafter referred to as OS) simultaneously on a single server. In logical partitioning, a management program called a hypervisor divides server computer resources (including memory areas and IO devices) into multiple logical partitions (LPARs) according to instructions from the server administrator. Run one OS at a time.

In logical partitioning, the OS on another LPAR must not stop or malfunction due to the operation of one OS. For that purpose, it is necessary to guarantee that an OS cannot access other LPAR resources (hereinafter referred to as isolation).

By the way, PCI buses are widely used as IO buses in PC servers represented by Intel's IA-32 and IA-64 ^TM architectures. Since the PCI bus is not designed with logical partitioning in mind, there is a risk that isolation may not be maintained by access from the IO device (hereinafter referred to as isolation failure). Specifically, isolation cannot be guaranteed if the OS is defective or if an error cannot be detected by the hardware when the IO card fails. Therefore, in order to realize logical partitioning with a PC server, it has been a challenge to ensure isolation for access from IO devices.
Conventionally, a known example US2002 / 0010811A1 (hereinafter, known example 1) has been proposed for the above problem. In known example 1, a PCI to PCI bridge called Terminal Bridge is
Stores the address range that can be accessed by transactions originating from IO devices. In the known example 1, when the destination address of the transaction is outside the accessible area, the isolation is realized by aborting the received transaction.
US Patent Publication US2002 / 0010811A1

  However, in the known example 1, the following problems are not solved.

The first issue is to successfully terminate the received transaction originating from the IO device on the IO bus and to notify the hypervisor. Simply suspending the reception of a transaction will cause the issuing IO device to time out or prevent other IO devices from transferring data correctly. Moreover, if the hypervisor is not notified, appropriate error handling such as rebooting the corresponding OS cannot be realized.

The second problem is that the known example 1 does not consider transfer between IO devices. In general, since a server holds a large number of IO slots, the method of storing the access availability within an address range has many combinations of IO slots and requires a large amount of storage area.

The third problem is that known example 1 assigns IO devices to each LPAR in slot units,
It is not considering the initialization. Therefore, when resetting a certain IO slot, there is a problem that IO cards assigned to other LPARs are also reset.

  An object of the present invention is to solve the above problems.

In a server using a general-purpose IO bus typified by a PCI bus, the following advantages can be obtained by applying the present invention to a part of a chip set.
Appropriate for the failed LPAR while maintaining the operation of IO devices belonging to other LPARs when an isolation failure occurs while preventing an isolation failure due to access from an IO device during logical partitioning operation Realize error handling.
Provide efficient isolation failure detection means for access between IO devices during logical partitioning operation.
When an isolation failure occurs, a means for resetting only the IO device belonging to the failed LPAR in slot units is provided, and the IO device can be reassigned to another LPAR.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an outline of a server assumed by the present invention. In this embodiment, an example is shown in which four CPUs (100 to 103) are connected to a 110 CPU bus to which a plurality of CPUs can be connected. In this embodiment, the number of CPUs is four, but it may be other than four.

There are 120 chip sets that control the CPU bus, and the chip set controls the 130 IO bus # 0, 131 IO bus # 1, 160 memory interface, and 140 crossbar interface in addition to the CPU bus. This IO bus is a commonly used PC
I-bus is assumed.

In the present embodiment, a configuration example is shown in which two IO buses are connected like 130 and 131, but configurations other than two may be used.

The 120 chipset has a 121 CPU Bus Ctrl Unit that controls the CPU bus, a 122 Memory Ctrl Unit that controls the memory interface, and a 123 IO Ctr that controls the IO bus.
l Unit and 124 CrossBar Ctrl Unit that controls the crossbar interface.

In the present invention, the CPU, chipset, 150 memory, and IO devices (not shown in the drawing) connected to the IO bus are collectively treated as nodes, and a server capable of connecting a plurality of nodes using a 180 crossbar is provided. Assumed. In FIG. 1, 190 nodes # 0 and
Although an example of a two-node configuration of 191 node # 1 is shown, it need not be two nodes.

The virtual machine system provided by this server is realized by software called a hypervisor.
Fig. 2 shows a correlation diagram of the address map used in the virtual machine system.
The address map provided by the server of FIG. 1 is called an absolute address space. The real address space in FIG. 2 indicates an address used by the OS, and the virtual address space in FIG. 2 indicates an address used by the application program.
FIG. 2 shows an example in which two OSs are operating on each LPAR, and it is assumed that OS A and OS B respectively. It is assumed that virtual addresses VA and VB used by different application programs running on OS A and OS B are converted into addresses indicated by RA and RB, respectively, during non-logical partitioning operation. When there is no address conversion by the hypervisor during logical partitioning operation, if RA and RB have the same value, OS A and OS B will access the same absolute address, and normal operation will not be possible. In order to prevent this, the hypervisor makes access to PA and PB (≠ PA) corresponding to RA and RB.

The access from the CPU and IO device in the virtual machine system will be described below.

In the case of access from the CPU, the hypervisor detects that OS A tries to register a TLB entry that converts VA to RA in the CPU, and the hypervisor PAs the VA on behalf of the OS.
Register the TLB entry to be converted to. The hypervisor can calculate the PA from the memory allocation status and RA for each LPAR. When the application program actually accesses VA, the TLB entry that converts VA to PA is registered by the hypervisor. Therefore, the access is to access PA instead of RA, and for each LPAR shown in FIG. Address translation is realized.

On the other hand, in the case of access from an IO device, unlike the access from the CPU, there is no address conversion function corresponding to TLB. Therefore, in the present invention, by configuring the 123 I / O Ctrl Unit in FIG. 1 as shown in FIG. 3, the LPAR that generated the access is identified according to the access from the IO, and a different address is assigned to each LPAR. Perform address translation to access. The mechanism of this address conversion will be described below with reference to the drawings.

FIG. 3 shows a configuration example of the 123 I / O Ctrl Unit. 123 I / O Ctrl Unit is 130 and 13
1 The IO bus is controlled. In this embodiment, a configuration is shown in which each IO bus has Slot # 0 to Slot # 3. The IO bus has signal lines 206a and 206b that arbitrate access requests from IO devices on these slots.
The access request by 6b is arbitrated by the bus arbs (bus arbitration circuit) 204a and 204b, and an Ack response is sent to the slot that can issue the access request.

In addition, a normal IO bus has only one reset signal for initializing the IO devices on the bus, and is used in common for all slots. However, in the present invention, 205a and 205b reset signal lines are prepared independently for each slot,
Assertion / deassertion of the reset signal is controlled by 204a, 204b Bus Arb. As a result, initialization can be performed in slot units, and rebooting and reinitialization can be performed for each LPAR. The procedure for reinitializing the IO slot using the 205a and 206a reset signals will be described later with reference to FIG.

As a result of arbitration by the above bus arbitration circuit from one of the 130 and 131 IO buses, when an access to another IO bus, CPU, or memory is issued, the access request is sent to the 123 I via the IO bus. / O Transmitted to Ctrl Unit. I / O Ctrl
In Unit, the destination address of the access request is modified by the address modification unit 203a or 203b based on the value of the address. The contents of this modification point to address conversion so that a different address is accessed for each LPAR described above.
FIG. 4 shows a configuration example of the address modification unit 203a. Since the same circuit is used for 203b, only 203a will be described in this embodiment. In the circuit example shown in FIG. 4, information related to address conversion stored in 201a ADR conversion information is used. This information includes: (1) Interleave and address area information, (2) Member LPAR information in slot units, and (3) Address addition value for each LPAR according to the real address range. FIG. 6 shows the format of a register for storing such information.
(1) For interleaving and address area information, the address type, interleaving presence / absence / range designation, and destination bus / slot number information for the range specified by the absolute address in the address map described in FIG. included. For the address type, the address range is a memory device, or Memory Mapped IO (MMIO)
Stores the distinction of whether or not it is assigned to an IO device. When the address range is allocated to the memory device, information indicating whether the address range is allocated to the memory device of a specific node or interleaved between the memory devices of a plurality of nodes is displayed in the interleave presence / absence / range specification field. Stored. The address range is assigned to the IO device (hereinafter referred to as MMIO area)
In this case, the bus number and slot number of the IO device to be accessed are stored in the destination bus slot number field. (1) Interleaving and address area information are set by the BIOS (Basic IO System) or firmware during the server initialization sequence, and even servers that do not support logical partitioning possess similar information.
(2) LPAR information belonging to each slot can be accessed for each issuing PCI slot
(= Belongs to the same LPAR) Information for identifying PCI slots. Access is permitted only to slots for which the permission bit in this information is set to 1. This information is set by the hypervisor when each LPAR is created. Further, as a variation of this register format, access may be permitted only to a slot whose permission bit is 0.
Since this information only requires 1-bit storage capacity for each combination of the issuer IO slot and issuer IO slot, in contrast to the known example 1 method in which the address range needs to be stored for each combination, The same effect can be achieved with a much smaller memory capacity, and the second problem mentioned above is solved.
(3) The address addition value for each LPAR according to the real address range is unique to each LPAR.
This is information for address conversion from a real address to an absolute address. This information is set by the hypervisor when each LPAR is created.
The procedure for setting each piece of information in FIG. 6 will be described with reference to FIG.
601 When power is turned on, POST is used to check for hardware failure
(Power On Self Test) is executed.
602 Next, BIOS and Firmware initialization code are executed. Here, the memory installation status and IO device connection status are investigated, and (1) interleaving and address area information setting in FIG. 6 are performed.
603 Next, the hypervisor is loaded. The boot device is generally a flexible disk or hard disk, as with other OSs, but may be other devices. Thereafter, the hypervisor initializes the hypervisor itself.
604 The hypervisor waits for a new LPAR creation request from the server administrator. As an interface for receiving an instruction from the server administrator, a console screen through a CRT or a serial line, a liquid crystal (LCD) panel, an e-mail, and the like can be considered. The server administrator specifies the absolute memory address range, IO device (or slot) number, and OS boot device to be assigned to the newly started LPAR through the hypervisor interface described above, but gives other information as options. It doesn't matter. Options include CPU allocation method for each LPAR and specification of CPU time ratio.
605 The hypervisor creates a new memory area specified by the server administrator.
Assign to LPAR.
Next, the hypervisor assigns the IO device specified by the server administrator to the newly created LPAR.
607 Based on the memory area specified by the server administrator and the IO device allocation status, the hypervisor selects (2) the assigned LPAR information in SLOT units and (3) each LPAR according to the real address range in Figure 6. Set the address addition value. By setting these registers, the functions of the 202a, 202b Adr Dec, and 203a, 203b Adr modifiers described later become effective.
608 The hypervisor is stored in the boot device specified by the server administrator.
Call the OS boot loader and start the OS operation on the new LPAR.

The 203a Adr modifier shown in FIG. 4 receives (3) 304a, 304b address addition value, (1) address area information, 210a issuer slot number input from 204a Bus Arb, and IO bus transaction as input. . In this embodiment, the address addition value is 2
10a In the example, there are two for each issuer slot number, but there may be other than two.
The IO bus transaction is separated into Tx information indicating the type of transaction such as read / write and 307 real address indicating the access destination by the 301 Tx decoding circuit. The Tx information is output as it is without any operation.
304a, 304b Address addition value is selected by 210a issuer slot number,
It is separated into 305a BASE and SIZE parts and 306a and 306b OFFSET parts.
The 307 real address is input to the 303a and 303b adders and added to 306a and 306b OFFSET.
The 302 ADR conversion determination circuit selects one of the 309a and 309b addition results and the 307 real address and outputs it as a 312 absolute address. The determination procedure in this circuit is as follows.
The 307 real address is compared with the absolute address range of the address area information to determine whether the 307 real address is an MMIO area. In this embodiment, it is assumed that the MMIO area does not perform address translation. If it is in the MMIO area, the 307 real address is output to the 312 absolute address. At the same time, the 311 address conversion presence / absence signal is deasserted to notify that address conversion has not been performed.
If 307 real address is not MMIO area, 307 real address is 305a, 305b BASE, SIZ
Judge whether it matches the real address range specified by E. If it matches, the corresponding 3
09a or 309b Add result is selected and output as 312 absolute address. At the same time, 311 address conversion presence / absence signal is asserted to notify that address conversion has been performed.
If the 307 real address does not match the real address range specified by 305a, 305b BASE, and SIZE, the 307 real address is output as a 312 absolute address. At the same time, the 311 address conversion presence / absence signal is deasserted to notify that address conversion has not been performed.

FIG. 5 shows a configuration example of 202a Adr Dec. In this embodiment, since 202a and 202b use the same circuit, only 202a is shown. 202a Adr Dec is 203a Ad in Figure 4
r 308 Tx information output from the modifier, 312 absolute address, 311 address conversion presence / absence received, interleaving and address area information from 201a ADR conversion information, belonging LPAR information in SLOT units, 204a Bus Arb 210a Receives the issuer slot number and issues an intra-chipset transaction (hereinafter referred to as Inbound Tx) to the 200 other Ctrl Unit IF control units in FIG.
The 401 access destination determination circuit receives the 312 absolute address, 308Tx information, interleave and address area information, determines the access destination of the transaction,
3 Output Inbound Tx. At the same time, the 411 address type notifies the access destination type (memory, IO device, CPU, etc.), the 412 destination slot number, the destination IO bus number, and the IO slot number to the 402 access availability determination.
402 Access enable / disable judgment: Selects Tx to be issued to Inbound Tx IF after receiving the belonging LPAR information in SLOT units selected by 311 address conversion presence / absence, 411 address type, 412 destination slot number, and 210 source slot number To do. The issue determination procedure in this circuit is as follows.
411 When the address type is an IO device (MMIO), the access permission bit indicated by the 412 destination slot number is 1 in the bitmap of the belonging LPAR information in SLOT units (
Or if it is 0), allow access.
411 When the address type is CPU (interrupt transaction from IO device), access is permitted. In this embodiment, it is assumed that the CPU is shared by all LPARs in a time-sharing manner, and the interrupt vector of each LPAR is managed by the hypervisor, so that the operation of other OSs is not hindered.
If the address type is 411 and the presence / absence of 311 address conversion is asserted, access is permitted.
If access is permitted by (1) to (3) above, change 413 Inbound Tx to Inbound T
x Output to IF.
If the above (1) to (3) do not apply, the 402 access determination determines that access is denied, the access target address of 413 Inbound Tx IF is exchanged with the address registered in the 403 destination Reg, and the Inbound Tx IF And generate 404INT to generate an interrupt transaction for the CPU and issue it as Inbound Tx. At the same time, the issuing slot number and 312 absolute address are stored in the 405 isolation failure register. It is assumed that the 405 isolation fault register can be read from the CPU.

The CPU that has received the interrupt transaction performs error processing. The procedure will be described with reference to FIG.

In 701, the CPU that has received the interrupt transaction activates the hypervisor error processing routine registered in the interrupt vector.

In 702, the hypervisor specifies that the error that has occurred is an isolation failure between LPARs from the value of the error register in the chipset and the information of the error record reported from the firmware.

At 703, the hypervisor identifies the area affected by the isolation fault. In the configuration example of FIG. 3, the configuration guarantees that there is no influence other than the LPAR to which the issuing IO slot belongs. Therefore, the IO slot number causing the isolation failure is acquired from the issuer slot number recorded in the 405 isolation failure register, and the LPAR to which the IO slot belongs is specified. In this patent, each IO slot is assigned exclusively when an LPAR is created and is not shared with other LPARs. Therefore, the LPAR to which the IO slot belongs can be uniquely identified from the IO slot number.

In 704, the hypervisor instructs to stop the OS (hereinafter referred to as guest OS) operating in the LPAR. To stop the guest OS from the hypervisor: (1) Guest
Notifying the OS that a fatal error such as an address parity error has occurred, allowing the guest OS to perform reboot processing, or (2) the CPU in the hypervisor
A possible method is to remove the corresponding LPAR from the allocation queue. Further, the hypervisor or the guest OS acquires failure log information such as a guest OS memory image as needed for OS debugging or the like.

In 705, the hypervisor resets all IO slots belonging to the corresponding LPAR using the 205a RST # signal provided for each slot, and then releases the IO slot to a state that does not belong to any LPAR. With this processing, the IO slot can be reassigned to another LPAR, and the third problem mentioned above is solved.

In 706, the hypervisor releases the memory area allocated to the corresponding LPAR to a state not belonging to any LPAR. This processing makes it possible to reallocate the memory area to another LPAR.

In 707, the hypervisor notifies the server administrator that the corresponding LPAR has caused an isolation failure. Examples of failure notification means include an LCD panel and buzzer for displaying the server status, a console screen for management, and e-mail. The failure notification means may be prepared exclusively for notification of an isolation failure, or may be shared with other failure notification means.
In FIG. 5, only the hypervisor is used for the 403 destination Reg, and a memory address not assigned to each LPAR is set in the initialization of the hypervisor itself during the 603 hypervisor load in FIG. As a result, when an isolation failure occurs,
The LPAR data is prevented from being destroyed, and the IO bus transaction can be completed for the IO bus in the same route as the normal access processing from the IO device. To prevent.
The transaction for which the above processing has been completed is input to the 220 Ctrl Unit IF control unit in FIG. 2, and the 121 CPU Ctrl Unit or 124 C based on the Tx information and the absolute address.
For the rossBar Ctrl Unit or 122 Memory Ctrl Unit or other IO bus, issue an Inbound Tx via the signal line 132 or 133, wait for a response from each destination unit, and make the access request Response transactions to IO devices on the bus
Issue to the IO bus and complete the access request on the IO bus.
As a result, when an isolation failure occurs due to access from an IO device, it is possible to report the occurrence of an isolation failure and perform error handling while continuing the operation of the IO device belonging to another LPAR. To solve the first problem mentioned above.

The present embodiment is a modification of the first embodiment, and the 123 I / O Ctrl Unit in FIG.
An example in which O to I / O Bridge is added is shown.

In Example 2, the IO bus connected to the 123 I / O Ctrl Unit for reasons of space is 134 I
This is a configuration example with one O bus. 137 I / O to I / O Bridge is an LSI that has the function of distributing one IO bus to multiple IO buses. In this embodiment, 134, 135, 136
Are simply described as IO buses, but they may be different types of IO buses or the same type of IO buses.

Example 2 includes 201a, 201b ADR conversion information in Example 1, 202a, 202b Adr Dec
, 203a, 203dAdr modifiers on the 138 access monitoring card # 0 and 139 access monitoring card # 1 as shown in FIG. 7, 201c, 201d ADR conversion information (2), and 202c, 202d
This is an example of mounting as a Dec (2), 203c, 203d Adr modifier (2). Since 138 and 139 use exactly the same circuit, only 138 access monitoring card # 0 will be described.
In the second embodiment, unlike the first embodiment, IO devices are allocated to each LPAR in IO bus units, not in IO slot units. Therefore, 201c ADR conversion information (2) holds only a part of the information of 201a. Specifically, (1) information other than the destination slot number in the interleave information and address area information in FIG. 6, (2) the permission bit of the belonging LPAR information holds only one bit per bus, (3 ) The address addition value for each LPAR corresponding to the real address range is held as information in IO bus units, not in IO slot units.
The 203c Adr modification unit (2) monitors an IO bus transaction issued from another IO slot on the same bus, and performs the above-described address modification by using the IO bus transaction as an input. As described above, in Example 2, the IO device allocation unit is the IO bus unit, so unlike the 203a Adr modifier in Example 1, the 304a, 304b address addition value receives only one piece of information and 210a The issuer slot number is not received.
202c Adr Dec (2) checks the destination address of the received IO bus transaction. Unlike 202a Adr Dec of the first embodiment, 202c Adr Dec (2) does not include the 210a issuer slot number, the route for issuing 413 Inbound Tx to the Inbound Tx IF, and the 403 destination Reg. 402 Inbound Tx when access is possible
No transactions are issued for IF (in this case IO bus). If it is not accessible, create an interrupt transaction to the CPU and report that an isolation failure has occurred.
As a result, if the 135 IO bus and 136 IO bus belong to different LPARs,
Transaction issued from IO device on IO bus is 137 I / O to I / O Bridg
Access to an IO device on the 136 IO bus via e can be detected as an isolation failure. Conversely, from 136 IO bus to 135 I
The same can be detected when accessing the O bus.
Although it is not possible to completely prevent the occurrence of an isolation failure, it is possible to notify that an isolation failure has occurred. Therefore, it is possible to perform the processing when an error occurs as shown in FIG. At that time, regarding the identification of the affected area, in addition to the source LPAR of the transaction that caused the transaction, the destination LPAR is specified, and the corresponding guest OS
Reboot. The destination LPAR can be identified from the 312 absolute address stored in the 405 isolation failure register.

This example is a modification of Example 1, in which 123 I / O Ctrl Unit in FIG. 3 is replaced with 126 I / O in FIG.
Configure like Ctrl Unit.

The 202a Adr Dec of the first embodiment is changed and configured as 202e Adr Dec (3) shown in FIG. Since 202f Adr Dec (3) has exactly the same circuit, only 202e Adr Dec (3) will be described below. 421 Access determination availability (2) is a transaction issuance determination and interrupt transaction issuance similar to the 402 access determination availability in the first embodiment, but when it is determined that access is impossible, the Inbound Tx is changed to Inbound Tx IF. Without issuing, using the 209a response issue request, 207a is requested to issue a response transaction for the Inbound Tx. The 420 access destination determination circuit (2) uses the 211a Tx response information to transmit information necessary for issuing a response transaction such as the type of the transaction.
207a Response issue controls the IO bus transaction issued from 126 I / O Ctrl Unit to 130 IO bus # 0. Since the 207b response issuance has exactly the same circuit as 207a, only 207a will be described below with reference to FIG.
The 502 response selection unit issues a bus right request to 204a Bus Arb using the 208a Bus right request / grant signal, and issues an IO bus transaction to 130 IO bus # 0 only when the Bus right is acquired. When a response issuance request is not made by the 209a signal, the 502 response selection unit outputs a transaction input from the other Ctrl Unit I / F control unit to the 130 IO bus # 0. 211a when a response issuance request is made by the 209a signal
A positive response transaction is transmitted to the IO bus using the transaction information received from the Tx response information and the data of the 501 response data generation unit. Specifically, if the transaction requires response data such as memory read, 50
1 The data generated by the response data generation unit is transmitted as response data. When response data such as memory write is not required, only the Ack response is transmitted. This completes the IO bus transaction that caused the isolation failure.
Enables operations on the IO bus and prevents system stoppage due to IO device timeout.
Furthermore, as a variation of Example 3, I which caused isolation failure
A configuration is possible in which a negative response transaction such as a retry is always transmitted in response to an O-bus transaction. This configuration cannot be used when the IO device is performing its own timeout detection in order to prevent the system from being stopped due to a long retry, but generally negative response transactions are not possible. Since no response data is required, there is an advantage that the 501 response data generation unit can be omitted.

The present embodiment is a modification of the first embodiment, and the 203a Adr modifying unit in FIG. 4 is configured like the 203g Adr modifying unit in FIG. The 203 g Adr modifier in Example 4 is 203a Adr of Example 1.
Unlike the modifier, it does not receive the 304a address addition value, but holds the 323a-323d index table instead. 307 real address is 321 index bits and 32
Separated into 2 offset bits. FIG. 13 shows an example in which the upper 3 bits are extracted as 321 index bits and the value is “010”.
Other than this, the length of the index bit and which bit is used as the 321 index bit may be used. The 203g Adr modification unit reads the value of the entry indicated by the value of the 321 index bit in the index tables of 323a to 323d, selects it with the 210a issuer slot number, and obtains the index bit after 324 replacement. If address conversion is necessary in the above 302 address conversion determination circuit, 324
After replacement, the index bit is selected. When conversion is not required, the 321 index bit is selected, and then combined with the 322 offset bit and output as a 312 absolute address.
In the case of the fourth embodiment, instead of recording an addition value for each LPAR corresponding to (3) real address range in FIG. 6, a storage capacity for recording the index tables of 323a to 323d is necessary. Compared with the first embodiment, when the fragmentation (fragmentation) of the memory is repetitively generated and repeated, the information necessary for address translation can be reduced. The information in the index tables 323a to 323d needs to be set in the 607 register update in FIG. 11, and by setting this information, the 203g Adr modifying unit operates.

The block diagram of the structural example of the server which this invention assumes. The address map figure which this invention assumes. 1 is a block diagram of a configuration example 1 of an I / O Ctrl Unit in the present invention. The block diagram of the configuration of the Adr modifier in the present invention. The Adr Dec composition block diagram in the present invention. The format figure of the ADR conversion information in this invention. The block diagram of the example 2 of a structure of I / O Ctrl Unit in this invention. The block diagram of the structural example 3 of I / O Ctrl Unit in this invention. The block diagram of the example 2 of Adr Dec structure in this invention. The block diagram of the structural example of the response issuance in this invention. The processing flowchart at the time of boot in this invention. 6 is a processing flowchart when an error occurs in the present invention. The block diagram of the structural example 2 of the Adr modification part in this invention.

Explanation of symbols

100 ... 103 CPU # 0 ... CPU # 3
110 CPU bus
120 chipsets
121 CPU Bus Ctrl Unit
122 Memory Ctrl Unit
123 I / O Ctrl Unit
124 CrossBar Ctrl Unit
130, 131 IO bus # 0, IO bus # 1
140 Crossbar interface
150 memory
160 Memory interface
180 Crossbar
190, 191 Node # 0, Node # 1
200 Other Ctrl Unit I / F control part
201a, 201b ADR conversion information
202a, 202b Adr Dec
203a, 203b Adr modifier
204a, 204b Bus Arb
205a, 205b RST #
206a, 206b req #, ack #
210a, 210b Issuer slot number
301 Tx decoding circuit
302 ADR conversion judgment circuit
303a, 303b Adder
304a, 304b Address addition value
305a, 305b BASE, SIZE
306a, 306b OFFSET
307 Real address
308 Tx information
309a, 309b addition result
311 Address conversion presence / absence
312 Absolute address
401 Access destination judgment circuit
402 Accessibility judgment
403 Destination Reg
404 INT generation
405 Isolation fault register
411 Address type
412 Destination slot number
413 Inbound Tx
137 I / O to I / O Bridge
138, 139 Access monitoring card # 0, Access monitoring card # 1
201c, 201d ADR conversion information (2)
202c, 202d Adr Dec (2)
203c, 203d Adr modifier (2)
207a, 207b issue response
208a, 208b Bus request / permission
202e, 202f Adr Dec (3)
209a, 209b Response issue request
211a, 211b Tx response information
420 Access destination judgment circuit (2)
421 Accessibility judgment (2)
501 Response data generator
502 Response selection part
601 POST execution
602 BIOS / Firmware execution
603 Load the hypervisor
604 New LPAR generation request reception
605 Secure memory area
606 I / O device reservation
607 Register update
608 Call OS boot loader
701 Error notification by interrupt transaction
702 Interrupt source identification
703 Impact range identification
704 Instruction to stop the guest OS
705 Reset / release I / O slot belonging to the relevant LPAR
706 Free memory area belonging to LPAR
707 Error occurrence / factor notification to the administrator
321 index bits
322 Offset bit
323a, ..., 323d Index table # 1, ..., index table # 4
324 Index bit after replacement.

Claims (1)

Multiple logical partitions are set, and memory resources and CPU resources are allocated to each of the logical partitions.
A system component for controlling an information processing apparatus in which an operating system is individually operated in each of the logical partitions,
An IO interface that connects multiple IO devices connected to multiple IO slots, and
Means for allocating one of the logical partitions to each of the IO devices connected to the IO slot;
An address offset value determined according to the logical partition to which the memory access transaction issued by the IO device belongs is added to the destination address of the memory access transaction in the chip set obtained from the IO device via the IO interface. An address modifier to
Whether the addition result to the destination address indicates a memory address in a memory address area allocated to the logical partition to which the memory access transaction issued by the IO device belongs, is confirmed, and the confirmation result Is accepted, an access destination determination circuit that permits issuance of a memory access transaction in the chipset that includes the addition result as a destination address;
Address replacement means for replacing a destination address of a memory access transaction in the chipset with a memory address in a specific memory area not assigned to any logical partition when the addition result is rejected. System parts of information processing equipment.

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