JP2009230425A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor capable of protecting periodic processing by using a free time of application processing to perform data writing. <P>SOLUTION: The information has: a CPU 10 for executing application processing at a predetermined period; a nonvolatile memory 20 for occupying a resource of the CPU to stop the application processing when data write processing is performed; a write determining means 30 for determining whether or not the data write processing is possible within the remaining time in the predetermined period after executing application processing; and a data writing means 40 for executing the data write processing when the write determining means determines that the data write processing is possible. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, and more particularly, to an information processing apparatus having a nonvolatile memory in which application processing of a CPU stops when data writing processing is performed.

Conventionally, in a computer that executes a computer program, a device that changes information in an instruction including a part of the computer program without interrupting execution of the computer program, the memory storing the information at its own internal address Means and means coupled to the memory means for periodically accessing information for use by the computer; and means coupled to the memory means and stored in the memory means without interrupting execution of the computer program An apparatus having means for changing information between periodic access to memory means by an access means so as to change information is known (for example, see Patent Document 1).
JP-T 9-512119

  However, in the configuration described in Patent Document 1 described above, when the execution of the computer program occupies most of the periodic processing or when the amount of information stored in the memory means is large, the periodic access Even if the information is changed between intervals, the information changing process does not end within the cycle, and the process goes over to the next cycle, which makes it impossible to keep the cycle.

  Therefore, an object of the present invention is to provide an information processing apparatus capable of writing data by using the idle time of application processing and protecting the periodic processing.

In order to achieve the above object, an information processing apparatus according to a first invention includes a CPU that executes application processing at a predetermined cycle;
When performing the data write process, a nonvolatile memory that occupies the CPU resources and stops the application process;
Write determination means for determining whether or not the data write processing is possible in the remaining time within the predetermined period after executing the application processing;
And a data writing unit that executes the data writing process when the writing determination unit determines that the data writing process is possible.

  As a result, the data writing process can be performed using the free time of the cycle, and the data writing process is not performed when the data writing is not in time, thus preventing the data writing process from extending over the next cycle. In addition, application processing can be performed while keeping a predetermined cycle.

A second invention is an information processing apparatus according to the first invention, wherein
A periodic processing timer for performing interrupt processing to interrupt the data writing processing;
And periodic time control means for controlling the periodic processing timer so that the timing at which the periodic processing timer performs the interrupt processing is within the predetermined period.

  Thereby, the data writing process can be interrupted within a predetermined processing cycle, and a normal application process can be executed in the next cycle.

A third invention is an information processing apparatus according to the first or second invention,
The cycle time control means controls the timing of performing the interrupt processing by setting the count value of the cycle processing timer to a count value that is smaller than the total count value of the predetermined cycle. To do.

  Thereby, even if the data writing process is not completed within the remaining time in the cycle by setting the count value of the cycle processing timer, the data writing process can be surely interrupted within the predetermined cycle, and the cycle can be controlled.

A fourth invention is an information processing apparatus according to any one of the first to third inventions,
A main cycle timer for measuring the predetermined cycle is provided.

  As a result, the normal predetermined cycle can be time-measured by providing another dedicated timer, and the measurement of the predetermined cycle can always be constant regardless of the presence or absence of the data writing process.

A fifth invention is an information processing apparatus according to any one of the first to fourth inventions,
The CPU includes the data writing means.

  As a result, the nonvolatile memory can be written in the CPU.

  According to the present invention, it is possible to perform data writing processing of the nonvolatile memory while reliably keeping the cycle by using the idle time of the cycle processing of the application processing.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram illustrating an example of the overall configuration of an information processing apparatus 100 according to a first embodiment to which the present invention is applied. In FIG. 1, an information processing apparatus 100 according to the first embodiment includes a central processing unit (CPU) 10, a nonvolatile memory 20, a writing determination unit 30, a writing unit 40, and a periodic processing timer 50. And a cycle time control means 60. The information processing apparatus 100 according to the present embodiment may include a main cycle timer 70, a RAM (Random Access Memory) 80, and an input / output port 90. Further, although not shown in FIG. 1, the information processing apparatus 100 according to the present embodiment may include a ROM (Read Only Memory) other than the nonvolatile memory 20 as necessary.

  The information processing apparatus 100 according to the present embodiment may be configured as a microcomputer or a microcontroller, for example, and may be used by being incorporated into various electronic devices. For example, it may be used as a part of an electronic computer or may be used for an embedded application having a specific purpose. For example, the specific device may be used in a vehicle ECU (Electronic Control Unit).

  The CPU 10 is a means for performing various arithmetic processes and control processes, and is a part that can also be called the brain of the information processing apparatus 100. In the information processing apparatus 100 according to the present embodiment, the CPU 10 performs application processing for performing a predetermined function for a specific purpose.

  When performing application processing, the CPU 10 executes application processing within a predetermined period. Various application processes are executed in units of a predetermined cycle, and the CPU 10 operates by executing each application process with good separation within a predetermined cycle.

  The nonvolatile memory 20 is a storage means that can be electrically rewritten and can retain stored contents even when the power is turned off. The non-volatile memory 20 according to the present embodiment is intended for the non-volatile memory 20 having a property that, when data write processing is performed, resources of the CPU 10 are occupied and normal application processing by the CPU 10 is stopped. For example, a semiconductor memory such as a flash memory or an EEPROM (Electrically Erasable and Programmable Read Only Memory) may be applied to the nonvolatile memory 20. In the present embodiment, an example in which a flash memory is applied to the nonvolatile memory 20 will be described below. However, including the above-described EEPROM and the like, data can be rewritten and a CPU resource can be used during data write processing. As long as the non-volatile memory 20 is occupied, the various types of non-volatile memories 20 can be applied.

  The nonvolatile memory 20 stores a program for application processing executed by the CPU 10. Thereby, the CPU 10 can read a program stored in the nonvolatile memory 20 and execute a predetermined application process. Further, as described above, the application processing program stored in the nonvolatile memory 20 can be rewritten as necessary.

  The non-volatile memory 20 may also store basic software of an OS (Operating System) as necessary. If it is preferable to store the OS in a ROM that is not rewritten, a ROM may be provided for the OS.

  The write determination means 30 is a means for determining whether or not there remains a time during which data can be written to the nonvolatile memory 20 within the remaining time of one cycle when the CPU 10 finishes the application process within a predetermined period. is there. When performing a data write process to the nonvolatile memory 20, there is a minimum time required for the data write process. Therefore, the write determination unit 30 performs the minimum process required for the data write process when the application process is completed. It is determined whether or not a limited time is left.

  Specifically, for example, the write determination unit 30 acquires information on the end of the application process within the cycle from the CPU 10 and monitors the cycle processing timer 50 to calculate the remaining time of the cycle, which is the data write It is determined whether or not the predetermined time required for the processing is longer than the predetermined time. If the remaining time is equal to or longer than the predetermined time, it is determined that the data writing process is possible. Good. The minimum predetermined time required for the data writing process depends on the mode of the nonvolatile memory 20 and the like, but may be about 10 [M bytes / second], for example.

  Since the write determination unit 30 performs the determination calculation process as described above, the write determination unit 30 may be configured by a unit having a calculation processing function, for example, may be configured by an ASIC (Application Specific Integrated Circuit), or as a part of the CPU 10 It may be built in and configured.

  The write determination unit 30 may send the determination result of the write determination to the CPU 10 and provide information for causing the CPU 10 to appropriately execute the next operation. Thereby, the CPU 10 can appropriately select whether to execute the data writing process to the nonvolatile memory 20 in the remaining time of the period, or to enter the next period and execute the application process without executing it.

  The writing means 40 is means for writing data into the nonvolatile memory 20. The writing unit 40 may be configured as a unit having a writing function such as a writer by an ASIC or the like, for example. Further, it may be incorporated in the CPU 10 and configured as a part of the CPU 10, but this point will be described in the second embodiment.

  The periodic processing timer 50 is a means for measuring the time of the periodic processing, interrupting the data writing processing by the writing means 40 by interruption, and terminating the processing within the period. The cycle processing timer 50 starts counting from the start of the cycle, and measures the interruption timing of the data write processing when the data write processing to the nonvolatile memory 20 is to be executed. For example, the periodic processing timer 50 counts and adds clocks supplied at time intervals shorter than the operation period of the CPU 10, and when the clock reaches a predetermined number of times, issues an interrupt request to the CPU 10 to end the processing. May be provided with a function of notifying. The CPU 10 can end the data writing process by this interrupt request.

  The cycle time control means 60 is means for controlling the timing for executing the interrupt processing by the cycle processing timer 50. The cycle time control means 60 controls the time so that the interrupt timing of the cycle processing timer 50 falls within a predetermined cycle and does not straddle the next cycle when data write processing to the nonvolatile memory 20 is performed. I do. Specifically, the cycle time control means 60 sets the count value of the cycle processing timer 50 and sets the timing at which the interrupt processing by the cycle processing timer 50 is performed. The count value of the cycle processing timer 50 is set to a smaller count value than the entire count value in a predetermined cycle.

  The main cycle timer 70 is a means for measuring the time of a predetermined cycle in which the CPU 10 performs application processing. The main cycle timer 70 may be configured such that, for example, a clock count value is set so as to be a constant interval, and the number of clocks is counted to make an interrupt request to the CPU 10 when the set count value is reached. At this time, the CPU 10 may end the cycle accordingly and perform an operation to start the next cycle. Thereby, processing such as application processing is executed in the CPU 10 at a constant predetermined cycle.

  The RAM 80 is temporary storage means that can electrically read and write data and can store data only when the power is on. The RAM 60 may be used for data processing by the CPU 10.

  The input / output port 90 is an interface unit used for input / output of information with a device connected to the outside of the information processing apparatus 100. For example, when the information processing apparatus 100 is applied to a vehicle ECU, signals are input / output from other vehicle ECUs and sensors.

  Next, the processing flow of the information processing apparatus 100 according to the present embodiment will be described with reference to FIG. FIG. 2 is a diagram illustrating an example of a processing flow for one cycle of the information processing apparatus 100 according to the present embodiment.

  In step 100, the periodic processing timer 50 starts counting simultaneously with the start of the predetermined period of the CPU 10. At this time, the main cycle timer 70 may also start counting at the same time.

  In step 110, the CPU 10 reads an application program stored in the nonvolatile memory 20 and executes application processing.

  In step 120, the write determination unit 30 performs a determination process as to whether or not the data write process to the nonvolatile memory 20 can be performed in the remaining time within the predetermined period after the application process is performed within the predetermined period. Executed. In step 120, the timing for starting the determination as to whether or not the data writing process can be performed may be the timing at which the application processing in the CPU 10 ends, or which application is to be executed and the time required for the application. If it is determined, it may be determined whether or not the data writing process can be performed in parallel during the execution of the application process.

  In step 130, the write determination unit 30 outputs a determination result as to whether or not the data write process to the nonvolatile memory 20 can be executed in the remaining time within a predetermined period. The determination may be made based on the relationship between the remaining time within the predetermined period indicated by the periodic processing timer 50 or the main periodic timer 70 and the time required for data writing processing to the nonvolatile memory 20.

  For example, let us consider a case where the predetermined period set for executing normal application processing (main processing) is 5 [ms], and at least 1 [ms] is required to perform data writing processing. Here, if it takes 2 [ms] to finish the application processing within the cycle, the remaining 3 [ms] is free, so it is determined that the data write processing is possible during that time. On the other hand, if 4.5 [ms] is required to complete the application process, the remaining is only 0.5 [ms], so it is determined that the data writing process is impossible.

  If it is determined in step 130 that the data writing process is impossible, the process in the cycle is terminated. Further, the processing flow similar to that shown in FIG. 2 is repeated for the next cycle. On the other hand, if it is determined that the data writing process is possible, the cycle time control means 60 performs control such that the count value of the cycle processing timer 50 is smaller than the count value of the main cycle timer 70 being executed. Then, the interruption timing of the data writing process (the end timing within the predetermined period) is controlled so as not to exceed the predetermined period, and the process proceeds to Step 140.

  Note that the determination result of step 130 is output to the CPU 10.

  In step 140, data writing processing to the nonvolatile memory 20 is executed by the data writing means 40 in accordance with an instruction from the CPU 10. During the data writing process, CPU resources are occupied. The interrupt process is ready to be accepted. The data writing process can write a plurality of bytes of data.

  In step 150, the periodic processing timer 50 makes an interrupt request to the CPU 10 to execute interrupt processing. Thereby, the CPU 10 starts a process of interrupting the data writing process.

  In step 160, the data writing means 40 interrupts the data writing process in accordance with an instruction from the CPU 10. The processing within the predetermined period is finished here. Then, in the next cycle, the processing flow shown in FIG. 2 is executed, and the processing flow in FIG. 2 is repeatedly executed for each cycle.

  Next, the contents of processing in the CPU 10 will be described in more detail with reference to FIGS. 3 and 4. FIG. 3 is an example of a timing chart of the time division writing process executed in the information processing apparatus 100 according to the present embodiment. FIG. 4 is an example of a more detailed processing flow diagram of the information processing apparatus 100 according to the present embodiment corresponding to the timing chart of FIG.

  FIG. 3 shows various examples of the relationship between application processing and data writing processing when the CPU 10 executes main application processing at a predetermined cycle.

  FIG. 3A is a diagram illustrating an example of a case where data write processing is possible after main application processing. In FIG. 3A, simultaneously with the start of the predetermined cycle, application process A having function 1 is executed, and then application process B having function 2 is executed. After the application processes A and B are executed, the remaining time is still sufficient within a predetermined period of the main period, and the data writing process D is subsequently executed. Then, the data writing process D is temporarily interrupted before reaching the end of the main period, and the process is completed within the predetermined period of FIG. Note that the end of the data writing process in this case may be executed by an interrupt process by the periodic process timer 50. The timing for executing this interrupt processing is such that the cycle time control means 60 makes the count value of the cycle processing timer 50 smaller than the count value of the entire predetermined cycle of the main cycle timer 70 that counts the time of the predetermined cycle. May be set and controlled.

  FIG. 3B is a timing chart of the next predetermined cycle of FIG. 3A, and shows an example in which execution of data writing processing is impossible. In FIG. 3B, an application process A having function 1, an application process B having function 2, and an application process C having function 3 are sequentially executed, and all of these application processes A, B, and C are completed. Thus, sufficient time for performing the data writing process D does not remain within a predetermined period of the main period. Therefore, in this case, application processes A, B, and C having a normal predetermined cycle are executed, and the predetermined cycle process is ended. In this case, the cycle processing timer 50 may count the same count value as the count value of the main cycle timer 70 and end the processing. The interrupt processing for ending the predetermined cycle may be performed by the main cycle timer 70 or the cycle processing timer 50. However, since it is a normal processing, it is preferable that the main cycle timer 70 performs it. .

  FIG. 3C is a timing chart of the next predetermined cycle of FIG. 3B, and is a diagram illustrating an example in which the data writing process can be performed. In FIG. 3C, the application process A having the function 1 is executed simultaneously with the start of the predetermined period, thereby completing the application process within the predetermined period. Then, at the end stage of the application process A, since sufficient time remains within a predetermined period of the main period, the data write process D is executed. The data writing process D executed at this time may be a continuation of the data writing process D interrupted in FIG. As a result, even if the amount of data to be written in the data writing process D is large, a plurality of bytes of data are continuous, and all the data writing processes are performed, even if the time of a predetermined period is exceeded, By performing the time-sharing process using the idle time of the period, the data write process can be executed without affecting the normal application processes A, B, and C.

  Note that the end of the data writing process in FIG. 3C may be controlled by setting the processing cycle timer 50 by the cycle time control means 60 so that it falls within a predetermined cycle of the main cycle. Thereby, the predetermined period of the main period is kept constant, and it is possible to write a plurality of bytes of data that require a data write processing time longer than the predetermined period while keeping the predetermined period.

  FIG. 4 shows an example of a more detailed processing flow diagram for one cycle of the information processing apparatus 100 according to the present embodiment corresponding to the timing chart of FIG. In addition, about the process similar to the process flowchart shown in FIG. 2, the same step number is attached | subjected and the description is abbreviate | omitted or simplified.

  In step 100, both the cycle processing timer 50 and the main cycle timer 70 start counting. This is the same step as in FIG.

  In step 111, application process A having function 1 is executed.

  In step 112, application process B having function 2 is executed. In the case of FIG. 3C, since the application process B does not exist within the cycle, the process passes through step 112 as it is.

  In step 113, application process C having function 3 is executed. In the case of FIGS. 3A and 3C, the application process C does not exist in the cycle, and thus the process passes through step 113 as it is.

  In step 120, the write determination unit 30 starts determining whether or not the data write process D is possible. Since this step is the same as that in FIG. 2, the description thereof is omitted.

  In step 130, the write determination unit 30 outputs a determination result as to whether or not the data write determination process D is possible to the CPU 10. Since this step is the same as that in FIG. 2, the description thereof is omitted. As shown in FIG. 3B, when it is determined that the data writing process D is not possible, the process within the cycle is terminated and the process flow is terminated. On the other hand, as shown in FIGS. 3A and 3C, when it is determined that the data writing process D is possible, the process proceeds to step 131.

  In step 131, the count value of the cycle processing timer 50 is set by the cycle time control means 60. At this time, the count value of the period processing timer 50 is set so as to be suitable for interrupting the data writing process and within a predetermined period of the main period. Specifically, the count value of the cycle processing timer 50 may be set so as to be smaller than the count value of the entire cycle of the main cycle timer 70 and at a good timing of the data write processing.

  In step 140, data writing processing to the nonvolatile memory 20 is executed by the data writing means 40 in accordance with an instruction from the CPU 10. Since this step is the same as that in FIG. 2, its description is omitted.

  In step 150, timer interrupt processing is executed on the CPU 10 by the periodic processing timer 50. Since this step is the same as that in FIG. 2, its description is omitted.

  In step 160, the data writing means 40 interrupts the data writing process in accordance with an instruction from the CPU 10. As a result, the data writing process in one cycle ends, and the process itself in the one cycle also ends.

  In the next cycle, the processing flow shown in FIG. 4 is repeatedly executed, but the corresponding processing is performed in all cases of FIGS. 3A, 3B, and 3C according to the processing flow of FIG. Also, corresponding processing can be executed for other processing patterns not shown in FIG. Thus, for example, when the predetermined cycle is 5 [ms], even if it is necessary to write a plurality of continuous bytes of data required for writing at least 5 [ms], the data is written by the write determination means 30. Data write processing can be executed by determining whether processing is possible, checking the free time within a predetermined period after execution of the main application processing, and performing time-sharing processing.

  FIG. 5 is a diagram illustrating an example of the overall configuration of the information processing apparatus 100a according to the second embodiment to which the present invention is applied. In FIG. 5, the information processing apparatus 100 a according to the second embodiment includes a CPU 10 a, a nonvolatile memory 20, a write determination unit 30, a cycle processing timer 50, a cycle time control unit 60, and a main cycle timer 70. 1 is the same as the information processing apparatus 100 according to FIG. 1 of the first embodiment in that the RAM 80 and the input / output port 90 are provided.

  In FIG. 5, the data writing means 40a is incorporated in the CPU 10a, and is different from the information processing apparatus 100 according to the first embodiment in that the CPU 10a is configured to directly perform the data writing process of the nonvolatile memory 20. .

  As described above, the data writing process to the nonvolatile memory 20 may be directly performed by the CPU 10a. Thereby, a required number of parts can be reduced. In FIG. 5, the write determination unit 30, the cycle processing timer 50, the cycle time control unit 60, and the main cycle timer 70 are shown as externally attached to the CPU 10a. Thus, the processing may be performed.

  As described above, the information processing apparatus 100a according to the second embodiment may be configured to be incorporated in the CPU 10a as long as various arithmetic processing functions have similar functions. Thereby, it can comprise as the information processing apparatus 100a of compact and space-saving.

  Since the other components are the same as those in the first embodiment, the same reference numerals are given and the description thereof is omitted. Also, the processing flow and timing chart described in FIGS. 2 to 3 can be applied to the second embodiment as they are.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

1 is a diagram illustrating an example of an overall configuration of an information processing apparatus 100 according to a first embodiment. It is an example of the process flow figure for 1 period of the information processing apparatus 100 which concerns on a present Example. It is an example of the timing chart of a time division writing process. FIG. 3A is a diagram illustrating an example in which data write processing is possible. FIG. 3B is a diagram illustrating an example of the case where the data writing process cannot be executed. FIG. 3C is a diagram illustrating an example in which the data writing process can be executed. It is an example of the more detailed process flow figure of the information processing apparatus 100 which concerns on a present Example. It is the figure which showed an example of the whole structure of the information processing apparatus 100a which concerns on Example 2. FIG.

Explanation of symbols

10, 10a CPU
20 Nonvolatile memory 30 Write determination means 40, 40a Data writing means 50 Period processing timer 60 Period time control means 70 Main period timer 80 RAM
90 Input / output port 100, 100a Information processing device

Claims (5)

A CPU that executes application processing in a predetermined cycle;
When performing the data write process, a nonvolatile memory that occupies the CPU resources and stops the application process;
Write determination means for determining whether or not the data write processing is possible in the remaining time within the predetermined period after execution of the application processing;
An information processing apparatus comprising: a data writing unit that executes the data writing process when the writing determination unit determines that the data writing process is possible. A periodic processing timer for performing interrupt processing to interrupt the data writing processing;
2. The information according to claim 1, further comprising: a cycle time control unit that controls the cycle processing timer so that a timing at which the cycle processing timer performs the interrupt processing is within the predetermined cycle. Processing equipment.   The cycle time control means controls the timing of performing the interrupt processing by setting the count value of the cycle processing timer to a count value that is smaller than the total count value of the predetermined cycle. The information processing apparatus according to claim 1 or 2.   The information processing apparatus according to claim 1, further comprising a main period timer that measures the predetermined period.   The information processing apparatus according to claim 1, wherein the CPU includes the data writing unit.

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