JP6130735B2 - Microcontroller and error detection method - Google Patents

Description

  The present invention relates to a microcontroller and an error detection method.

  A microcontroller (sometimes called a microcomputer) has a storage element in which set values such as various peripheral circuits (a timer, a communication circuit, etc.) are stored. Some of these set values may include data that directly affects the control of devices (automobiles, home appliances, mobile phones, etc.) by a microcontroller. May change and reliability may deteriorate.

  As a technique for improving the reliability of RAM (Random Access Memory), there is a technique of adding a parity such as ECC (Error Correcting Code) to the RAM and detecting and correcting an error when reading data. There is also a mirroring method in which RAMs are multiplexed, a plurality of areas are formed in the RAM, the same data is stored in a plurality of RAMs or a plurality of areas in the same RAM, and values are compared at the time of reading. .

JP 2001-356998 A JP 2007-148777 A

  However, unlike the instruction code read from the processor side, the set values of the peripheral circuits are not read from the normal processor side after being written once, and there is no opportunity for error detection and correction. For this reason, it is difficult to ensure the reliability of the set value with a method that simply uses a RAM with ECC. Therefore, the processor periodically updates the set value stored in the storage element. In addition, with respect to the mirroring method, it is conceivable that the setting values for which the reliability is to be ensured are periodically updated by the processor.

  When the set value is regularly updated by the processor in this way, the processing performed by the processor is interrupted due to the set value update process, which adversely affects device control, such as a reduction in processing speed. There is concern to give.

  According to one aspect of the invention, a first storage unit that holds a setting value of a peripheral circuit, and a second storage unit that holds a replication value of the setting value and detects and corrects the error of the replication value at the time of reading. And, based on the writing times of the plurality of setting values to the first storage unit, the setting values with the old writing time are preferentially read from the first storage unit and correspond to the read setting values. There is provided a microcontroller including a comparison verification unit that reads the duplicate value from the second storage unit and performs comparison verification.

  According to another aspect of the invention, the setting value of the peripheral circuit is written in the first storage unit, and the duplicate value of the setting value is stored in the second storage unit that performs error detection and correction of the duplicate value at the time of reading. The writing / comparison / verification unit preferentially reads out and reads out the setting value with an earlier writing time from the first storage unit based on the writing time of the plurality of setting values into the first storage unit. An error detection method is provided in which the duplicate value corresponding to a set value is read from the second storage unit and compared and verified.

  According to the disclosed microcontroller and error detection method, it is possible to easily detect an error in setting values of peripheral circuits without interrupting the processing of the processor.

It is a figure which shows an example of the microcontroller of 1st Embodiment. It is a flowchart which shows an example of the error detection method. It is a figure which shows an example of the microcontroller of 2nd Embodiment. It is a figure which shows an example of a comparison verification part. It is a flowchart which shows an example of the process at the time of the operation | movement start of a microcontroller. It is a figure which shows an example of the data stored in RAM with ECC. It is a flowchart which shows an example of the process at the time of the comparison verification of a setting value and a replication value. It is a figure which shows the example of a storing of a priority. It is a figure which shows the example of an update of log | history information. It is a figure which shows the example of an update of a priority.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating an example of a microcontroller according to the first embodiment.

The microcontroller 1 of the first embodiment includes a processor 2, peripheral circuits 3a, 3b, 3c, storage units 4, 5, and a comparison verification unit 6.
The processor 2 controls each part of the microcontroller 1. The processor 2 is, for example, a central processing unit (CPU), a micro processing unit (MPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), or a programmable logic device (PLD). The processor 2 may be a combination of two or more elements of CPU, MPU, DSP, ASIC, and PLD.

  The peripheral circuits 3a, 3b, 3c are an interface for connection to an external device controlled by the microcontroller 1, a timer, and the like. Note that the peripheral circuits 3 a to 3 c may be provided outside the microcontroller 1.

  The storage unit 4 includes, for example, registers (such as flip-flops) 4a, 4b, and 4c. The storage unit 4 holds set values a, b, and c for controlling the peripheral circuits 3a, 3b, and 3c.

  The storage unit 5 holds duplicate values aa, bb, cc of the set values a to c. The storage unit 5 also stores information (history information) related to the setting value write time (update time). The writing time is stored as a counter value (not shown), for example. The storage unit 5 includes parity for error detection and correction, and performs error detection and correction of duplicate values at the time of reading. The storage unit 5 is, for example, a RAM with ECC. The history information may be stored in another storage unit.

  The comparison verification unit 6 refers to the history information, reads the setting values with the oldest writing time from the storage unit 4 based on the writing times of the plurality of setting values a to c to the storage unit 4, and responds to it. Duplicate values to be read are read from the storage unit 5 and their comparison is verified. The comparison verification unit 6 includes, for example, a priority order determination unit 6a and a comparison unit 6b as shown in FIG.

  Based on the history information, for example, the priority order determination unit 6a determines which setting value among the setting values a to c has the oldest writing time, and sets the setting value having the oldest writing time to the highest priority. To do. The comparison unit 6b performs comparison with the corresponding replication value at predetermined intervals in order from the setting value with the highest priority. When the set values a to c read from the storage unit 4 are different from the duplicate values aa to cc read from the storage unit 5, the comparison unit 6b notifies the processor 2 to that effect, for example.

Hereinafter, an example of an error detection method performed by the microcontroller 1 according to the first embodiment will be described with reference to a flowchart.
FIG. 2 is a flowchart illustrating an example of an error detection method.

  For example, when the user requests to write the set value a, the set value a is written into the register 4a of the storage unit 4 and the duplicate value aa is written into the storage unit 5 under the control of the processor 2 (step S1). The writing time is also stored in the storage unit 5 (step S2). When there is a write request for the other setting values b and c, the setting values b and c are similarly written to the registers 4b and 4c of the storage unit 4 under the control of the processor 2 and the duplicate values thereof. bb and cc are written in the storage unit 5. Further, the writing time is stored in the storage unit 5.

  Thereafter, the process of step S3 is performed. In the process of step S3, the priority order determination unit 6a determines the priority order based on the writing times of the plurality of setting values a to c. The priority order determination unit 6a increases the priority order of the setting values whose writing time is old. For example, when writing is performed in the order of the setting values a to c, the setting value a has the highest priority, the setting value b has the next highest priority, and the setting value c has the highest priority. Lower.

  Thereafter, the process of step S4 is performed. In the process of step S4, the comparison unit 6b first reads, for example, the setting value with the highest priority, that is, the setting value with the oldest writing time from the storage unit 4 after a predetermined period of time, and obtains the corresponding replication value. It reads from the memory | storage part 5, and those comparison verification is performed.

  For example, when the priority order of the set value a is the highest, comparison verification is performed between the set value a and the duplicate value aa corresponding to the set value a. The duplicate value aa is likely to be a correct value at the time of writing because error detection and correction are performed when it is read from the storage unit 5. On the other hand, the setting value a read from the storage unit 4 may be different from the value at the time of writing due to, for example, the storage unit 4 being affected by neutron rays or the like, causing a soft error. For this reason, it is possible to detect an error in the set value a by comparing the set value a with the duplicate value aa.

Thereafter, the update process of step S5 is performed.
If the set value a is different from the duplicate value aa, the comparison unit 6b notifies the processor 2 to that effect, and the processor 2 updates the set value a. Then, history information and priority order are also updated. When the set value a is updated, since the set value a is the newest, the priority is the lowest. Further, when the set value a and the duplicate value aa are the same (when there is no error), the comparison / verification unit 6 stores the information of the compared time in the history information, and lowers the priority of the one with the new compared time. You may do it.

In the update process in step S5, the comparison / verification unit 6 may update the corresponding setting value with the duplicate value read from the storage unit 5.
When the comparison verification and update processing as described above is performed on the setting value with the highest priority, the comparison unit 6b performs the same processing as described above with respect to the setting value with the next highest priority after a predetermined period. Perform comparative verification.

  As described above, according to the microcontroller 1 and the error detection method of the present embodiment, the comparison / verification unit 6 preferentially sets a setting value that has an old writing time and is likely to have an error. Error detection. Thereby, an error in the set value can be easily detected without interrupting the processing of the processor 2.

  If there is an error, for example, the processor 2 performs a setting value update process. As a result, the reliability of the setting value can be easily ensured without interrupting the processing of the processor 2 periodically for updating the setting value.

  If there is an error, the comparison verification unit 6 may update the corresponding setting value with the duplicate value read from the storage unit 5. As a result, the processing of the processor 2 does not have to be interrupted during the setting value update processing.

  In the above description, the case where there is one set value a to c for each of the three peripheral circuits 3a to 3c has been described. However, a plurality of set values are set for each of the peripheral circuits 3a to 3c. There may be. Further, the number of peripheral circuits is not limited to three, and may be two or four or more.

(Second Embodiment)
FIG. 3 is a diagram illustrating an example of the microcontroller according to the second embodiment.
The microcontroller 10 includes a CPU 11, a bus bridge 12, peripheral circuits 13-1, 13-2, ..., 13-n, registers 14-1, 14-2, ..., 14-n, a RAM with ECC 15, and a comparison verification unit 16. And a clock generation unit 17 and buses B1, B2, B3, B4.

The CPU 11 is connected to the bus B1 and controls each part of the microcontroller 10. The bus bridge 12 connects the buses B1 to B3 to each other.
The peripheral circuits 13-1 to 13-n are an interface for connection to an external device controlled by the microcontroller 10, a timer, and the like. Note that the peripheral circuits 13-1 to 13-n may be provided outside the microcontroller 1.

  In the registers 14-1 to 14-n, setting values for controlling the peripheral circuits 13-1 to 13-n are written. The registers 14-1 to 14-n are connected between the buses B2 and B4.

  The ECC-added RAM 15 is a RAM capable of error detection and 1-bit error correction, and holds a copy value of a set value written in the registers 14-1 to 14-n. The RAM with ECC 15 has the same address area as the registers 14-1 to 14-n. Further, the ECC-added RAM 15 stores history information related to setting value update history and comparison verification history. The ECC-added RAM 15 is connected to the bus B 3 and the comparison verification unit 16.

  The comparison verification unit 16 refers to the history information, and based on the writing time of the plurality of setting values and the time when the comparison verification is performed, the comparison verification unit 16 stores the setting value and the corresponding replication value in the registers 14-1 to 14-n, ECC. The data is read from the attached RAM 15 and the comparison is verified. The comparison verification unit 16 is connected to the bus B 4, the ECC-added RAM 15, and the clock generation unit 17.

  The clock generation unit 17 generates a clock for operating a counter (to be described later) in the comparison verification unit 16. This clock may be slower than the clock used by the CPU 11 or the like.

FIG. 4 is a diagram illustrating an example of the comparison verification unit.
The comparison verification unit 16 includes a counter 20, a priority order determination unit 21, a RAM access unit 22, a register access unit 23, and a comparison unit 24.

  The counter 20 counts clocks supplied from the clock generation unit 17. For example, when the counter 20 detects that the initial values of the registers 14-1 to 14-n are written in the ECC-added RAM 15, the counter 20 starts counting the clock.

  The priority determination unit 21 refers to the history information, and in each setting value, the difference between the counter value when the last writing is performed or when the comparison verification with the duplicate value is performed and the current counter value is performed. And priorities of setting values to be compared and verified are determined. The priority order determination unit 21 increases the priority order as the setting value increases. Then, when the difference in the setting value with the highest priority is equal to or greater than a predetermined value, the priority determination unit 21 sends the setting value with the highest priority and its duplication to the register access unit 23 and the RAM access unit 22. Instructs reading of value.

  The RAM access unit 22 supplies the address of the duplicate value instructed to be read by the priority order determination unit 21 to the ECC-added RAM 15 and sends the duplicate value read from the ECC-added RAM 15 to the comparison unit 24.

  The register access unit 23 supplies the address of the setting value instructed to be read by the priority order determination unit 21 to any of the registers 14-1 to 14-n, and reads from any of the registers 14-1 to 14-n. The obtained set value is sent to the comparison unit 24.

  The comparison unit 24 compares the read duplicate value with the set value, and determines whether or not they match. When the duplicate value matches the set value, the comparison unit 24 updates the history information stored in the ECC-added RAM 15 with the counter value at the time of comparison. If the duplicate value and the set value do not match, the comparison unit 24 notifies the CPU 11 of this by an interrupt or the like. Further, the comparison unit 24 notifies the CPU 11 of the address where the set value where the mismatch has occurred is stored. Note that the comparison unit 24 may notify the CPU 11 of the comparison result even when the duplicate value matches the set value.

Next, an exemplary flow of an error detection method performed by the microcontroller 10 will be described.
FIG. 5 is a flowchart showing an example of processing at the start of operation of the microcontroller.

  In the process of step S10, under the control of the CPU 11, the initial values written in the registers 14-1 to 14-n are transferred to the ECC-added RAM 15 and written therein. In the process of step S <b> 11, the counter 20 starts counting the clock supplied from the clock generation unit 17.

  In the process of step S12, the priority determination unit 21 determines whether or not the setting value has been written to any one of the registers 14-1 to 14-n from the CPU 11. If writing has not occurred, the process of step S12 is repeated until writing occurs. If writing has occurred, the process of step S13 is performed.

  In the process of step S13, the CPU 11 stores a duplicate value of the set value at the same address as the register in which the set value is stored in the ECC-added RAM 15. In addition, the counter value when writing is performed by the priority determination unit 21 is stored in the RAM with ECC 15 as history information. Thereafter, the processing from step S12 is repeated.

For example, when the power source of the microcontroller 10 is turned off, the above process ends.
FIG. 6 is a diagram illustrating an example of data stored in the ECC-added RAM.
The addresses of the registers 14-1 to 14-n viewed from the CPU 11 are assigned to the RAM 15 with ECC. Then, for each address, the numbers of the registers 14-1 to 14-n (No. 1, No. 2,..., No. n) and the copy of the set values stored in the registers 14-1 to 14-n Stores the value (initial value of the set value). Further, ECC (ECC No. 1, ECC No. 2,..., ECC No. n), which is an error code generated when the duplicate value is written, and registers 14-1 to 14-n are finally written. The counter values (C1 to Cn) when stored are stored.

FIG. 7 is a flowchart illustrating an example of processing at the time of comparison verification between the set value and the duplicate value.
In the process of step S20, the priority determination unit 21 accesses the registers 14-1 to 14-n via the register access unit 23 to enable or disable the peripheral circuits 13-1 to 13-n. It is determined whether or not the valid bit to indicate indicates validity.

  For example, when the valid bits of all the peripheral circuits 13-1 to 13-n indicate invalidity, until one of the valid bits of the peripheral circuits 13-1 to 13-n becomes valid, The process of step S20 is repeated.

  If at least one of the valid bits of the peripheral circuits 13-1 to 13-n is a value indicating validity, the process of step S21 is performed. In the process of step S21, the priority order determination unit 21 refers to history information (a counter value as shown in FIG. 6). Then, the priority order determination unit 21 obtains the difference between the current counter value and the counter value at the time of the last writing in each setting value, or the last comparison verification with the replicated value, The priority order of the setting values to be compared and verified is determined.

  For example, in the history information (counter value) as shown in FIG. 6, if C1 <C2 <... <Cn, the priority order is the set value of the register 14-1, the set value of the register 14-2,. , The order of priority decreases in the order of the set values in the register 14-n. The priority order determination unit 21 includes, for example, a storage unit, and holds the determined priority order.

FIG. 8 is a diagram illustrating an example of storing the priority order.
The storage unit 21a of the priority order determination unit 21 uses, for example, the priority order determined by FIFO (First In First Out) as the register number No. 1-No. n. In the example of FIG. 1 has the highest priority, and the register number No. No. 2 register 14-2,... The order of priority decreases in the order of the set values of the n registers 14-n. The storage unit 21a of the priority order determination unit may hold history information (counter value) of the setting value with the highest priority. For example, when the set value of the register 14-1 has the highest priority, the counter value C1 shown in FIG. 6 is held in the storage unit 21a.

  After the priority order is determined, the process of step S22 is performed. In the process of step S22, when the difference between the counter value of the setting value with the highest priority and the current counter value is greater than or equal to a predetermined value, the priority determination unit 21 determines whether the register access unit 23 and the RAM access unit 22 To read the set value and its duplicate value. The predetermined value is set based on, for example, the cycle of the clock generated by the clock generator 17 and the cycle (time) for error detection. When the counter 20 counts up in synchronization with the rising edge of the clock, assuming that the error detection cycle is Td and the clock cycle is Tc, for example, Td / Tc becomes the above predetermined value.

  Next, the process of step S23 is performed. In the process of step S23, the comparison unit 24 masks bits that do not need to be compared among the read set value and its duplicate value. For example, bits that are rewritten by the operations of the peripheral circuits 13-1 to 13-n are masked (not subject to comparison) because errors cannot be detected even if they are compared.

  Thereafter, the process of step S24 is performed. In the process of step S24, the comparison unit 24 compares the read copy value with the set value (the unmasked portion) and determines whether or not they match.

  If the duplicate value matches the set value, the process of step S25 is performed. In the processing of step S25, the comparison unit 24 updates the history information stored in the ECC-added RAM 15 with the counter value at the time of comparison.

FIG. 9 is a diagram illustrating an update example of history information.
If the counter value at the time when the set value of the register 14-1 having the highest priority is compared with the duplicate value is Cx, the history information is stored in the data stored in the ECC-added RAM. The counter value shown is updated as shown in FIG. Moreover, after the process of step S25, it returns to the process of step S21, and the priority stored in the memory | storage part 21a of the priority determination part 21 shown in FIG. 8 is updated.

FIG. 10 is a diagram illustrating an example of updating the priority order.
In the example of FIG. The set value of the register 14-1 of No. 1 has the highest priority. However, as a result of comparison and verification, it is determined that the value matches the duplicate value (no error). Therefore, in the example of FIG. It is low. Instead, in the example of FIG. The setting value of the register 14-2 of No. 2 has the highest priority in the example of FIG. In addition, with the update of the priority order, the storage unit 21a may hold history information (the counter value C2 in the example of FIG. 6) regarding the setting value of the register 14-2 having the highest priority order.

  On the other hand, if the duplicate value does not match the set value, the process of step S26 is performed. In the process of step S26, the mismatch information is stored in a storage unit (for example, the storage unit 21a described above) in the comparison verification unit 16. The mismatch information includes the address of the register where the mismatch between the set value and the replicated value occurred, the value of the set value, the update history of the set value, the comparison history, the current counter value, the counter value indicating the history and the current counter value And the difference.

  The setting value update history is, for example, the counter value when the setting value is written (updated) last time, and the comparison history is, for example, the counter value when the previous comparison verification is performed.

  Thereafter, in the process of step S27, the comparison unit 24 notifies the CPU 11 that a mismatch has occurred and the above-described mismatch information by interruption or the like. Thereby, for example, the CPU 11 may update the set value that did not match the duplicate value. For example, when the set value stored in the register 14-1 and the copy value stored in the ECC-added RAM 15 of the set value do not match, the CPU 11 updates the set value and the copy value. .

Note that the setting value may be updated by the comparison / verification unit 16 overwriting the copy value read from the ECC-added RAM into the register in which the setting value corresponding to the copy value is stored.
After step S27, the process returns to step S21, and for example, as shown in FIG. 10, the priority order stored in the storage unit 21a is updated.

For example, when the power source of the microcontroller 10 is turned off, the above process ends.
As described above, according to the microcontroller 10 and the error detection method of the present embodiment, the comparison verification unit 16 sets the setting value that has a high possibility that an error has occurred at an old writing time or comparative verification time. On the other hand, error detection is preferentially performed. Thereby, an error in the set value can be easily detected without interrupting the processing of the CPU 11.

  If there is an error, for example, the CPU 11 performs a setting value update process. Thus, the reliability of the setting value can be easily ensured without interrupting the processing of the CPU 11 periodically for updating the setting value.

  If there is an error, the comparison verification unit 16 may update the corresponding setting value with the duplicate value read from the RAM 15 with ECC. As a result, the processing of the CPU 11 does not have to be interrupted during the setting value update processing.

  When there is an error in a certain setting value, the comparison verification unit 16 notifies the CPU 11 of mismatch information including an update history and a comparison history, so that the current counter value (at the time of error detection) is From the comparison, it can be inferred at which counter value range an error has occurred. That is, the error occurrence time can be estimated.

  As described above, one aspect of the microcontroller and the error detection method of the present invention has been described based on the embodiment, but these are only examples and are not limited to the above description.

DESCRIPTION OF SYMBOLS 1 Microcontroller 2 Processor 3a, 3b, 3c Peripheral circuit 4,5 Memory | storage part 4a, 4b, 4c Register 6 Comparison verification part 6a Priority determination part 6b Comparison part

Claims (5)

A first storage unit for holding set values of peripheral circuits;
A second storage unit that holds a duplicate value of the set value and performs error detection and correction of the duplicate value at the time of reading;
Based on the writing times of the plurality of setting values to the first storage unit, the setting values with the old writing time are preferentially read from the first storage unit, and the duplication corresponding to the read setting values A comparison verification unit that reads a value from the second storage unit and performs comparison verification;
A microcontroller comprising: Have a processor,
When the set value and the duplicate value corresponding to the set value are different, the comparison verification unit notifies the result of the comparison verification to the processor,
The microcontroller according to claim 1, wherein the processor updates the setting value different from the corresponding replication value.   The comparison verification unit notifies the processor of the update history of the set value or the history of the comparison verification when the set value is different from the duplicate value corresponding to the set value. The microcontroller according to claim 2.   The comparison verification unit updates the set value using the duplicate value when the set value is different from the duplicate value corresponding to the set value. Microcontroller. Write the set value of the peripheral circuit to the first storage unit,
Writing the duplicate value of the set value to a second storage unit that performs error detection and correction of the duplicate value at the time of reading,
The comparison verification unit preferentially reads out the setting value with the old writing time from the first storage unit based on the writing time of the plurality of setting values to the first storage unit, and reads out the setting value. Reading the duplicate value corresponding to the second storage unit, and performing comparison verification,
An error detection method characterized by the above.

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