JP2010181990A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To use a common memory patrol circuit for a plurality of memories in a data processor. <P>SOLUTION: The data processor includes a memory patrol circuit (4) for periodically performing read-access to a memory (2) which performs error correction to read data, and outputs the data according to control of a CPU (1), and for supporting maintenance to the data that the memory holds. The memory patrol circuit is connected to the memory through a bus (SBUS) to which the CPU is connected, and the memory patrol circuit is not closely coupled to the memory by one to one correspondence. The range of a patrol operation by the memory patrol circuit is determined on the basis of setting of the CPU, and when the notification of an error is received from the memory, the address of the data related to the error is stored in the storage circuit (41) of the memory patrol circuit, and an error flag is set to an error flag storage region (44), for example, or interruption is requested to the CPU. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a data processor having a data recovery function for a memory with an error detection and correction function for read data, and relates to a technique effective when applied to, for example, an automobile control system.

  A data processor (hereinafter also simply referred to as “microcomputer” or “microcomputer”) is incorporated in devices such as home appliances, AV devices, mobile phones, automobiles, and industrial machines, and performs processing according to programs stored in a memory. Thus, the semiconductor integrated circuit controls each device.

  The microcomputer is required to have a performance necessary for controlling the device and to be inexpensive because of its nature of being incorporated in the device and used. Furthermore, there is a strong demand for reliability to operate normally under operating conditions where operation is guaranteed.

  In recent years, with the complexity and sophistication of device control, the amount of data processed by the central processing unit (CPU) has increased, and the memory capacity built in the microcomputer has increased. On the other hand, with the miniaturization of the manufacturing process and the lower voltage of the power source of the microcomputer, a soft error in which the charge of the memory element is temporarily reversed due to the influence of neutron rays or the like has become a problem. In particular, since the memory is fine, it is more susceptible to soft errors than other elements. Among the data stored in the memory, there is important data that directly affects the control of the device, and it is desirable to make it less susceptible to soft errors.

  There is ECC (Error Correcting Code) as a highly reliable technology of a memory used conventionally. The ECC stores an error correction code added to the original data and stores it, so that even if a 1-bit error occurs, the original correct data can be restored and output. When a 2-bit error occurs Is a technology that cannot be restored but can detect errors.

  There is a memory patrol as a technique that makes it difficult to generate a two-bit error in an uncorrectable memory. Apart from memory access for device control, a memory having an ECC function (hereinafter also simply referred to as “ECC memory”) is read in the order of addresses, and when a 1-bit error is detected, the corrected data is written back. If the memory is left in a state where a 1-bit error exists, an error may occur in another bit at the same address, which may result in a 2-bit error. However, the 1-bit error is corrected by memory patrol. As a result, the probability of occurrence of a 2-bit error can be reduced. There are two types of memory patrols: a method in which the CPU executes with software and a method in which the CPU executes with dedicated hardware. The latter is desirable because it does not put a processing load on the CPU.

  Patent Document 1 describes a memory patrol control technique that can change the frequency of memory patrol for a first memory area that is mainly read and hardly rewritten and a second memory area that is always read and written. There is. According to this document, the memory patrol circuit is tightly coupled with the memory.

JP-A-6-324952

  When the memory patrol is tightly coupled with the ECC memory, it is necessary to provide a memory patrol circuit for each memory to be subjected to memory patrol. That is, each memory is connected to a common bus to which a CPU or the like is connected via a unique memory patrol circuit. Recent microcomputers tend to increase the number of built-in memories. For example, multi-cores have a memory for each CPU, and some peripheral modules have, for example, communication data in the memory. As the number and types of memories built into the microcomputer increase and the number of memories that you want to perform memory patrol increases, the memory scale and design man-hours increase if each memory has a memory patrol function. turn into.

  An object of the present invention is to provide a data processor that can use a common memory patrol circuit for a plurality of ECC memories.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the data processor has a memory patrol circuit that supports maintenance of data held in the memory by periodically performing read access to the memory that performs error correction on the read data and outputs the data under the control of the CPU. The memory patrol circuit is connected to the memory via a bus connected to the CPU, and is not tightly coupled to the memory in a one-to-one correspondence. The range of the patrol operation by the memory patrol circuit is determined by the setting of the CPU. When an error notification is received from the memory, the address of the data related to the error is held in the memory circuit of the memory patrol circuit, for example, an error flag storage area An error flag is set in the above or an interrupt is requested to the CPU. The CPU recognizes the occurrence of the error by an error flag or an interrupt, etc., performs a memory read using the address related to the error held by the storage circuit, and writes the read data to the address to store the data in the memory. Error data can be replaced with correct data. The memory patrol circuit is not tightly coupled to the memory, and the address range of the patrol is programmable by the CPU, so that a common memory patrol circuit can be used for a plurality of memories.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, control for recovering error data for a plurality of memories can be performed by a common memory patrol circuit.

FIG. 1 is a block diagram showing a first embodiment of a data processor according to the present invention. FIG. 2 is an explanatory diagram illustrating the register configuration of the memory patrol circuit. FIG. 3 is a flowchart illustrating a processing flow of the memory patrol operation by the memory patrol circuit. FIG. 4 is a block diagram showing a second embodiment of the data processor according to the present invention. FIG. 5 is a block diagram showing a third embodiment of the data processor according to the present invention. FIG. 6 is a block diagram showing a fourth embodiment of the data processor according to the present invention. FIG. 7 is a block diagram showing a fifth embodiment of the data processor according to the present invention. FIG. 8 is a block diagram of an automobile equipped with an automobile electronic control device to which the data processor according to the present invention is applied.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A data processor (DPU1 to DPU3) according to a typical embodiment of the present invention includes a CPU (1) that executes a program and a single that is arranged in the address space of the CPU and that reads and writes data. Or it has a plurality of memories (2) and a memory patrol circuit (4) controlled by the CPU. The memory has an error detection and correction function for generating an error correction code from write data in a write operation and storing it together with the data, and performing error correction on the read data using the data and error correction code read in a read operation and outputting the data. Is provided. The memory patrol circuit includes: a memory circuit (41 to 45) that is writable and readable by the CPU; and a patrol control circuit (47 to 50) that performs read control of the memory with reference to the memory circuit. Have. The memory circuit has an error flag storage area (45) that can be referred to by the CPU while the read range of the memory is programmable by the CPU. When the patrol control circuit is instructed to start a patrol operation by the CPU, the patrol control circuit instructs a read operation to the address of the memory specified in the storage circuit, thereby receiving the presence or absence of an error from the memory, When there is an error, the address of the data related to the error is held in the storage circuit, and an error flag (ERR) is set in the error flag storage area.

  The CPU recognizes the occurrence of the error by the error flag, performs a memory read using the address related to the error held by the storage circuit, and writes the read data to the address to thereby store the error data stored in the memory. Can be replaced with correct data. The memory patrol circuit is not tightly coupled to the memory, and the address range of the patrol is programmable by the CPU, so that a common memory patrol circuit can be used for a plurality of memories.

  [2] (Patrol enable) In the data processor of item 1, for example, the storage circuit has a patrol enable bit (PE), and the patrol operation can be started by the CPU setting the patrol enable bit. The patrol operation can be stopped by the patrol control circuit resetting the patrol enable bit.

  [3] (Error recognition by polling) In the data processor according to item 1, the CPU refers to the error flag storage area by polling, for example, and sets the error flag on the condition that the error flag is set. An address is read from the storage circuit, the memory is read using the address information, and read data is written back to the address.

  [4] (Error notification by interruption) In the data processor according to item 1, the patrol control circuit requests, for example, an error interrupt (54) to that effect from the CPU when there is an error, and performs the next patrol operation. Suppress the start of. It is also possible to notify the CPU of the occurrence of an error by an interrupt and shift to processing for data recovery.

  [5] (Interrupt response processing) In the data processor according to item 4, for example, the CPU reads an address of data related to the error from the storage circuit in response to the error interrupt, and uses the address information to read the memory And read back the read data to the address.

  [6] (Setting of Patrol Period) In the data processor according to item 1, for example, the storage circuit has a storage area (43) for period information. The control circuit controls the interval of the memory read operation by the patrol operation according to the period information set by the CPU.

  [7] The data processor (DPU2, DPU3) of item 1 includes a plurality of the memories, for example. The patrol control circuit receives the presence / absence of an error from the memory according to a logical sum signal of an error signal output from the memory in response to a read operation instruction.

  [8] In the data processor (DPU 3) described in [7], the plurality of memories are connected to different buses connected by a bus bridge circuit (1200), for example.

[9] (Interrupt notification to CPU)
The data processors (DPU1 to DPU3) according to another aspect of the present invention are a CPU that executes a program, one or a plurality of memories that are arranged in the address space of the CPU and read and write data, and are controlled by the CPU. A memory patrol circuit. The memory detects and corrects an error by generating an error correction code from write data in a write operation and storing it together with the data, and performing error correction on the read data using the data and error correction code read in a read operation Is provided. The memory patrol circuit includes a storage circuit that can be written and read by the CPU, and a patrol control circuit that performs read control of the memory with reference to the storage circuit. In the memory circuit, a read range of the memory is specified in a programmable manner by the CPU. When the patrol control circuit is instructed to start a patrol operation by the CPU, the patrol control circuit instructs a read operation to the address of the memory specified in the storage circuit, thereby receiving the presence or absence of an error from the memory, When there is an error, the address of the data related to the error is held in the storage circuit, and an interrupt related to the error is requested to the CPU.

  [10] (Memory with write-back function) A data processor (DPU4, DPU5) according to still another aspect of the present invention includes a CPU (1) for executing a program, and reading and writing of data arranged in the address space of the CPU. And a memory patrol circuit (4) controlled by the CPU. The memory (1600) generates an error correction code from the write data in the write operation and stores it together with the data, and performs error correction on the read data using the read data and the error correction code in the read operation and outputs the error detection code. And a memory unit (2) having a correction function and a write-back control unit (1601) for writing back the corrected data to the memory unit when error correction is performed on the read data. The memory patrol circuit includes a storage circuit that can be written and read by the CPU, and a patrol control circuit that performs read control of the memory with reference to the storage circuit. The memory circuit has an error flag storage area that can be referred to by the CPU while the read range of the memory is programmable by the CPU. When the patrol control circuit is instructed to start a patrol operation by the CPU, the patrol control circuit instructs a read operation to the address of the memory specified in the storage circuit, thereby receiving the presence or absence of an error from the memory, When there is an error, the address of data relating to the error is held in the storage circuit, and an error flag is set in the error flag storage area.

  [11] (Patrol enable) In the data processor according to item 10, for example, the storage circuit has a patrol enable bit, and the patrol operation can be started when the CPU sets the patrol enable bit, and the patrol control circuit The patrol operation can be stopped by resetting the patrol enable bit.

  [12] (Patrol cycle setting) In the data processor according to item 10, for example, the storage circuit has a storage region for cycle information. The control circuit controls the interval of the memory read operation by the patrol operation according to the period information set by the CPU.

  [13] The data processor according to item 10 includes, for example, a plurality of the memories. The patrol control circuit receives the presence / absence of an error from the memory according to a logical sum signal of an error signal output from the memory in response to a read operation instruction.

  [14] In the data processor of item 13, for example, the plurality of memories are connected to different buses connected by a bus bridge circuit.

2. Details of Embodiments Embodiments will be further described in detail.

  FIG. 1 illustrates a data processor according to the present invention. The data processor DPU1 shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by, for example, complementary MOS integrated circuit manufacturing technology.

  The data processor DPU1 is a central processing unit (CPU) 1 that fetches and executes a program, a memory (MRY) 2 that is used for holding the program and a work area of the CPU, a memory patrol circuit (MRYPTRL) 4, and a bus master selection The circuit (BMSLC) 5 and other circuit units such as a peripheral circuit (not shown) and an accelerator are included.

  SBUS is a system bus SBUS including a command and address bus (BCMD, ADR) 30, a read data bus (RDAT) 31, and a write data bus (WDAT) 32.

  The CPU 1 accesses the memory 2 etc. according to the program and performs data processing. The memory patrol circuit 4 reads the memory 2 according to the setting by the CPU 1 and performs error detection processing. The bus master selection circuit 5 selects the CPU 1 or the memory patrol circuit 4 as the bus master of the system bus SBUS.

  The memory 2 is operated by being supplied with a command and an address 20 from the command / address bus 30, and is supplied with write data 22 in a write operation and outputs read data 21 in a read operation. The memory 2 has an ECC function. In the write operation, an error check code is generated based on the write data, and the error check code is stored in the memory array together with the data. In the read operation, an error in the read data is detected using the error check code read from the memory array, and if there is an error, this is corrected and the read data 21 is output. Error correction is effective, for example, for 1-bit errors and does not have a correction function for errors of 2 bits or more. When there is an error in the read data during the read access from the CPU 1, the memory 2 returns an error signal 23 to the CPU 1. When there is an error in the read data during the read access from the memory patrol circuit 4, the memory 2 returns an error signal 24 to the memory patrol circuit 4. The memory 2 determines whether to output the error signal 23 or the error signal 24 according to whether the access is from the CPU 1 or the memory patrol circuit 4 according to the access request source ID included in the command.

  The CPU 1 outputs a command and an address 10 when performing access, reads read data 11 when performing read access, and outputs a write data signal 12 when performing write access. When the memory patrol circuit 4 performs read access, a command and an address 40 are output. The bus master selection circuit 5 selects either the command output from the CPU 2 and the address 10 or the command output from the memory patrol circuit 4 and the address 40 and outputs the selected command to the command and address 30 of the system bus SBUS.

  The CPU 1 can perform read / write access to the registers included in the memory patrol circuit 4 in the same manner as the memory 2. That is, the memory patrol circuit 4 inputs the command and address 10 output from the CPU 1 as the command and address 51, and in the case of read access, the memory patrol circuit 4 outputs read data 52, which is read by the CPU 1 as read data 11. In the case of read or write access, the CPU 1 outputs write data 12, which is written as write data 53 in the register of the memory patrol circuit 4.

  The memory patrol circuit 4 includes a transfer address register (MPATAR) 41, a transfer count register (MPATCR) 42, a transfer cycle register (MPATPR) 43, a control register (MPACR) 44, and a flag register (MPAFR) 45 as registers. These registers can be read and written by the CPU 1 as described above. A read / write control circuit (RDWRCNT) 46 controls reading and writing from the system bus SBUS to the registers 41 to 45. A transfer control circuit (TRCMDC) 47 controls an access command for memory patrol. The transfer control circuit 47 outputs a command 470 when the transfer is started, and the command 470 is input to the bus master selection circuit 5 together with the address signal 410 from the transfer address register 41. If the system bus SBUS is not in use by the CPU 1, the bus master selection circuit 5 selects the command 470 and the address signal 410 from the memory patrol circuit 4, thereby reading out the memory 2. When the reading is completed, the memory patrol circuit 4 completes one transfer. If there is an error in the data read from the memory 2, the memory 2 outputs an error signal 24 to the memory patrol circuit 4. When an error is detected by the error detection circuit (ERRTC) 48, the sequence control circuit (SQNSCNT) 50 interrupts the memory patrol operation, sets an error flag indicating the occurrence of an error in the flag register 45, and transfers the address register 41. The address where the error occurred is held, and the interrupt generation circuit 49 causes the CPU 1 to generate an error interrupt with the signal 54. For example, the CPU 1 in which the error interrupt is generated reads the transfer address register 41 of the memory patrol circuit 4, reads the memory 2 using the read memory address, and writes back the read data to the memory. That is, the CPU 1 reads from the memory 2 memory data in which a 1-bit error has occurred during memory patrol by the memory patrol circuit 4, and when the data is read, the data corrected by the error detection and correction function of the memory is written back to the address. . As a result, the 1-bit error is corrected on the memory 2. If an error occurs when the CPU 1 accesses the memory 2, an error signal 23 different from the error signal 24 is supplied to the CPU 1. When this error signal is received, the CPU 1 may perform a process of reading the memory address related to the error and writing back the read data by the same interrupt process in response to the activation of the signal 23, for example.

  FIG. 2 illustrates a register configuration of the memory patrol circuit 4.

  The transfer address register (MPATAR) 41 is a 32-bit register, for example, and holds address information in units of bytes. A transfer start address is set in the transfer address register 41 by the CPU 1, and each time the memory 2 is read by the memory patrol circuit 4, the value of the transfer address register 41 is incremented to the next address value by an arithmetic unit (not shown). Is done.

  The transfer count register (MPATCR) 42 is a 32-bit register and holds the transfer count. When the transfer count is set by the CPU 1 and the memory 2 is read by the memory patrol circuit 4, the value of the transfer count register 42 is decremented by 1 by an address calculator (not shown). For example, the sequence control circuit 50 repeats the memory patrol operation until the value of the transfer count register 42 becomes zero.

  The transfer cycle register (MPATPR) 43 is a 16-bit register, and the interval between read operations of the memory 2 by the memory patrol circuit 4 is set by the CPU 1 by the number of synchronous clock cycles of the system bus SBUS.

  A control register (MPACR) 44 is an 8-bit register, and a PE (Patrol Enable) bit 0 is a control bit indicating whether or not to permit a memory patrol operation. 0 indicates that the memory patrol operation is not performed, and 1 indicates that the memory patrol operation is performed. The IE (interrupt enable) of bit 3 is a control bit indicating whether or not to permit generation of a memory patrol error interrupt to the CPU 1 when an error detected by the signal 24 occurs. 0 indicates that no interrupt is generated, and 1 indicates that an interrupt is generated. A bit 2 EIE (end interrupt enable) is a control bit that indicates whether or not to permit generation of a memory patrol end interrupt to the CPU 1 when patrol is completed. 0 indicates that no interrupt is generated, and 1 indicates that an interrupt is generated. The TS (transfer size) [1: 0] of bits 5 and 4 sets the transfer size (read data size). 00 is a byte (8 bits), 01 is a word (16 bits), 10 is a long word (32 bits), and 11 is a reservation. Bits 7, 6, and 1 are reserved bits and cannot be written, and 0 is always read when read.

  A flag register (MPAFR) 45 is an 8-bit register, and TE (transfer end) of bit 0 is a transfer end flag. When the value of the transfer count register (MPATCR) 42 becomes 0, 1 is set to TE. ERR of bit 1 is an error flag. When the occurrence of an error due to the signal 24 is detected in the reading of the memory 2 by the memory patrol circuit 4, ERR is set to 1.

  The relationship between the operation of the memory patrol circuit 4 and the data processing operation of the CPU 1 when a read error is notified by the signal 24 is as follows. For example, when the memory patrol circuit 4 requests an interrupt from the CPU 1 when a read error is notified by the signal 24, the sequence control circuit 50 disables the patrol enable PE together with the interrupt request, and interrupts the memory patrol operation. During this time, the CPU 1 reads and writes back the memory data related to the error, and finally sets the patrol enable PE to be enabled so that the memory patrol operation of the memory patrol circuit 4 can be resumed.

  If the memory patrol circuit 4 does not request an interrupt from the CPU 1 when a read error is notified by the signal 24, the CPU 1 performs processing for monitoring the error flag ERR at an appropriate timing. Further, the memory patrol circuit 4 performs a process of sequentially accumulating addresses related to errors in a FIFO memory (not shown) or the like, and the memory patrol operation is not interrupted. When the CPU 1 detects the set state of the error flag ERR by polling or the like, the memory data is read and written back using the memory address related to the error held in the FIFO memory (not shown), and the data related to the error Perform recovery.

  FIG. 3 illustrates a processing flow of the memory patrol operation by the memory patrol circuit 4. The registers 41 to 45 are initialized by reset (1000). The control register 44 and flag register 45 are all set to 0. When the reset is released, the memory patrol condition is detected (1001). The patrol condition EXE is calculated according to the formula in the figure. The symbol “&” is a logical product. According to the conditions, PE = 1 of the control register, TE = 0 of the flag register, ERR = 0 of the flag register, and EXE = 1 because of the counter CNT ≧ MPATPR. The counter CNT is reset to 0 at the start of transfer in the reset and memory patrol, and in other cases, the value 1 is added every cycle of the system bus clock. Here, the counter CNT is provided in the sequence control circuit 50 for convenience.

  If the patrol condition EXE = 1 is not detected in step 1002, the process returns to the patrol condition detecting operation (1001). If the patrol condition EXE = 1 is detected, the process proceeds to the next step 1003. In step 1003, the counter CNT is cleared to 0, and the memory 2 is read. As a result of the memory read, an error determination is made based on the signal 24 (1004). If an error has occurred, the process proceeds to step 1005, and if not, the process proceeds to step 1008.

  In step 1005, ERR of the flag register MPAFR is set to 1. Next, when the IE of the control register is 1, an error interrupt is generated by the signal 54 to the CPU 1 (1007), and when it is 0, the process returns to step 1001 without being generated.

  In step 1008, a register update operation is performed. A value corresponding to the transfer size set in the TS of the control register (MPACR) is added to the transfer address register (MPATAR). 1 for bytes, 2 for words, 4 for longwords. The transfer count register (MPATCR) decrements by one. In the next determination process 1009, it is determined whether or not the value of the transfer count register (MPATCR) is 0. If not 0, the process returns to step 1001. In the case of 0, TE of the flag register (MPAFR) is set to 1 (1010). In the next determination processing 1011, if the EIE of the control register is 1, a memory patrol end interrupt is generated by the signal 55 (1012), and if it is 0, the process returns to step 1001 without generating it.

  FIG. 4 shows a second embodiment of the data processor according to the present invention. The data processor DPU2 of FIG. 4 is different from the data processor DPU1 of FIG. 1 in that a memory 9 is added and a logic circuit (ORLGC) 1100 is added, and the other points are the same as in FIG. Detailed description is omitted.

  Similarly to the memory 2, the memory 9 has an error detection function and a 1-bit error correction function. A command and address signal 90 is supplied from the command and address bus 30 to the memory 9, write data 92 is supplied from the write data bus 32, and read data 91 is output to the read bus 31. Similarly to the memory 2, the CPU 1 and the memory patrol circuit 4 can access the memory 9. When the memory 9 detects an error with respect to the read data in the read access from the CPU 1, an error signal 93 is output to the CPU 1. When the memory 9 detects an error with respect to the read data in the read access from the memory patrol circuit 4, the error signal 94 is output. Output. The error signal 93 corresponds to the error signal 23 from the memory 2, and the error signal 94 corresponds to the error signal 24 from the memory 2. The error signal 94 and the error signal 24 are logically summed by the logic circuit 1100, and the resulting logical sum signal 1101 is supplied to the error detection circuit 48, whereby the memory patrol circuit 4 accompanies read access to the memories 2 and 9. It is possible to detect that a data error has occurred.

  According to this example, the memory patrol circuit 4 can perform a memory patrol operation on the two memories 2 and 9 according to the setting from the CPU 1. The number of memories to be subject to memory patrol by one memory patrol circuit 4 is not limited to two, and the same is true even if there are three or more. The CPU 1 may input an error signal from each memory, and the logic circuit may input an error signal from each memory.

  FIG. 5 shows a third embodiment of the data processor according to the present invention. The data processor DPU3 of FIG. 5 has a local bus LBUS connected to the system bus SBUS via a bus bridge circuit (BRDG) 1200 with respect to the data processor DPU2 of FIG. The point that the memory 1300 is added is different, and the other points are the same as those in FIGS. 1 and 4, and the detailed description thereof is omitted.

  The local bus LBUS includes a command and address bus (BCMD / ADR) 1400, a read data bus (RDAT) 1401, and a write data bus (WDAT) 1402. The bridge circuit 1200 receives command and address signals supplied from the system bus SBUS. 1201 and write data 1203 are transmitted as command and address signals 1204 and write data 1206 to the local bus LBUS, and read data 1205 supplied from the local bus LBUS is supplied as read data 1202 to the system bus SBUS.

  Similar to the memory 2, the memory 1300 has an error detection function and a 1-bit error correction function. A command and address signal 1301 is supplied from the command and address bus 1400 to the memory 1300, write data 1303 is supplied from the write data bus 1402, and read data 1302 is output to the read bus 1401. Similarly to the memory 2, the CPU 1 and the memory patrol circuit 4 can access the memory 1300. When the memory 1300 detects an error for the read data in the read access from the CPU 1, the error signal 1303 is output to the CPU 1. When the memory 1300 detects the error for the read data in the read access from the memory patrol circuit 4, the error signal 1304 is output. Output. The error signal 1303 corresponds to the error signal 23 from the memory 2, and the error signal 1304 corresponds to the error signal 24 from the memory 2. The error signal 1304 and the error signal 1304 are logically summed by the logic circuit 1100, and the resulting logical sum signal 1101 is supplied to the error detection circuit 48, whereby the memory patrol circuit 4 accompanies read access to the memories 2 and 1300. It is possible to detect that a data error has occurred.

  According to this example, the memory patrol circuit 4 can perform a memory patrol operation on the two memories 2 and 1300 coupled to different buses sandwiching the bus bridge circuit 1200 according to the setting from the CPU 1. The number of memories that one memory patrol circuit 4 connects to each of the buses SBUS and LBUS targeted for memory patrol is not limited to one, and the same is true even if there are two or more memories in each bus. The CPU 1 may input an error signal from each memory, and the logic circuit may input an error signal from each memory.

  FIG. 6 shows a fourth embodiment of the data processor according to the present invention. The data processor DPU 4 in FIG. 6 is different from the data processor DPU 1 in FIG. 1 in that a memory (MRYCR) 1600 having a function of rewriting error data is employed. The differences will be described in detail below.

  The memory 1600 includes a memory (MRY) 200 as a memory unit and a write-back control unit (CRCT) 1601 that performs rewrite control of error data arranged between the bus SBUS and the memory 2. The error data write-back control unit 1601 includes an address buffer (ABUF) 1700, an address selection circuit (ADRSLC) 7, a data buffer (DBUF) 1800, and a write data selection circuit (WDSLC) 8.

  When read access to the memory 1600 is instructed by the command and address, the address buffer 1700 stores the command and address 20 supplied from the command and address bus 30, and the address selection circuit 7 uses the command and address 20 as a signal 71. The data is supplied to the memory 2, whereby the memory 2 reads out the data corresponding to the address and the error check code from the memory array, and performs error check using them. If there is no error, the read data is left as it is. If there is a 1-bit error, the error is corrected, and other data is output to the read data bus 31 as read data 21. Read data 2 is also supplied to and held in the data buffer 1800. When a 1-bit error is detected in the read data of the memory 2 in the read access from the CPU 1, an error signal 23 is output, and when a 1-bit error is detected in the read data of the memory 2 in the read access from the memory patrol circuit 4. An error signal 24 is output. When the error signal 23 or 24 is output, the signal 25 is output to cause the write data selection circuit 8 to select the data held in the data buffer 1800, and the command and address held in the address buffer 1700. Is selected by the address selection circuit 8. As a result, the error in the read data is corrected and the data held in the data buffer 1800 is written back to the corresponding address in the memory 2. In this manner, the error data rewriting function in the memory 1600 is realized.

  When write access to the memory 1600 is instructed by the command and address, the command and address 20 supplied from the command and address bus 30 are supplied to the memory 2 as the signal 71 by the address selection circuit 7 and supplied from the write data bus 32. When the write data selection circuit 8 rejects the write data 22 as write data 81 to the memory 2, writing to the memory is performed. The memory patrol circuit 4 is configured in the same manner as in FIG.

  As a result, when there is an error in the read data of the memory 2, it is not necessary to perform the process of writing the error correction data back to the corresponding address of the memory 2 by the interrupt process of the CPU1. The error data rewriting circuit (CRCT) 1601 is tightly coupled to the memory 2, but only one memory patrol circuit 4 may be arranged for memory patrol control for a plurality of memories (MRYCR) 1600 having an error data rewriting function.

  FIG. 7 shows a fifth embodiment of the data processor according to the present invention. The data processor DPU 5 of FIG. 7 is different in that the memory 2 in the data processor DPU 1 of FIG. 5 is replaced with a plurality of memories (MRYCR) 1600 having the error data rewriting function of FIG. Since other configurations are the same as those in FIGS. 5 and 6, detailed description thereof will be omitted. Also in this configuration, the CPU 1 and the memory patrol circuit 4 can access the memory 1600 and the memory 1300, and can supply error signals of a plurality of memories to the memory patrol circuit 4.

  FIG. 8 shows an automobile electronic control apparatus as an example to which the data processor according to the present invention is applied. In an automobile 1500, a data processor to which the present invention indicated by reference numeral 1503 is applied is mounted in a control device 1502 for electronically controlling an engine 1501. The data processor 1503 may be any of the data processors DPU1 to DPU5.

  As described above, according to the data processors DPU1 to DPU5 according to the present invention, the memory patrol circuit 4 detects a data error in the memory (ECC memory) 2 having an error detection and correction function built in the data processor separately from the CPU1. The CPU 1 can correct the error in the memory 2 by reading the address where the error has occurred from the memory patrol circuit 4.

  The memory patrol circuit 4 is not tightly coupled to the ECC memory 2 and is used by being connected to a bus that the CPU 1 performs memory access. Therefore, even when there are a plurality of memories to be patroled, one memory patrol circuit 4 can cope with it. be able to.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, when the CPU performs a data write-back operation for a memory error, the start of the process is not limited to interruption or polling, but may be performed periodically at a predetermined timing. Further, the start of the processing may be limited to only one of interruption and polling. The data processor may have a multi-CPU configuration. Data recovery may be performed by a specific one or a CPU with the smallest load at that time.

DPU1 Data processor 1 Central processing unit (CPU)
2 Memory (MRY)
4 Memory patrol circuit (MRYPTRL)
SBUS system bus 30 address bus (BCMD, ADR)
31 Read data bus (RDAT)
32 Write data bus (WDAT)
41 Transfer address register (MPATAR)
42 Transfer count register (MPATCR)
43 Transfer cycle register (MPATPR)
44 Control register (MPACR)
45 Flag register (MPAFR)
46 Read / Write Control Circuit (RDWRCNT)
47 Transfer control circuit (TRCMDC)
48 Error detection circuit (ERRTC)
50 Sequence control circuit (SQNSCNT)
PE Patrol Enable IE Interrupt Enable EIE End Interrupt Enable TS Transfer Size TE Transfer End ERR Error Flag DPU2 Data Processor 1100 Logic Circuit (ORLGC)
9 Memory 93 Error signal 94 Error signal DPU3 Data processor LBUS Local bus 1300 Memory 1200 Bridge circuit 1303 Error signal 1304 Error signal DPU4 Data processor 1600 Memory 1601 Write-back controller (CRCT)
1700 Address buffer (ABUF)
7 Address selection circuit (ADRSLC)
1800 Data buffer (DBUF)
8 Write data selection circuit (WDSLC)
DPU5 data processor 1500 automobile 1502 electronic control unit 1503 data processor

Claims (14)

A CPU that executes a program, a memory or a plurality of memories that are arranged in an address space of the CPU and that reads and writes data, and a memory patrol circuit that is controlled by the CPU;
The memory detects and corrects an error by generating an error correction code from write data in a write operation and storing it together with the data, and performing error correction on the read data using the data and error correction code read in a read operation With
The memory patrol circuit includes a memory circuit that is writable and readable by the CPU, and a patrol control circuit that performs read control of the memory with reference to the memory circuit,
The memory circuit has an error flag storage area that can be referred to by the CPU while the read range of the memory is programmable by the CPU.
When the patrol control circuit is instructed to start a patrol operation by the CPU, the patrol control circuit instructs a read operation to the address of the memory specified in the storage circuit, thereby receiving the presence or absence of an error from the memory, A data processor that holds an address of data relating to an error in the storage circuit and sets an error flag in the error flag storage area when an error occurs.   The memory circuit has a patrol enable bit, and the patrol operation can be started by the CPU setting the patrol enable bit, and the patrol operation is stopped by the patrol control circuit resetting the patrol enable bit. The data processor of claim 1, enabled.   The CPU refers to the error flag storage area by polling, reads the address of the data related to the error from the storage circuit on condition that the error flag is set, and uses the address information to store the memory. The data processor according to claim 1, wherein a process of reading and reading back the read data to the address is performed.   The data processor according to claim 1, wherein when there is an error, the patrol control circuit requests an error interrupt to that effect from the CPU and suppresses the start of the next patrol operation.   In response to the error interrupt, the CPU reads the address of the data related to the error from the storage circuit, reads the memory using the address information, and writes the read data back to the address. The data processor according to claim 4. The storage circuit has a storage area for periodic information;
The data processor according to claim 1, wherein the control circuit controls an interval of a memory read operation by the patrol operation according to period information set by a CPU.   2. The data according to claim 1, further comprising: a plurality of the memories, wherein the patrol control circuit receives the presence / absence of an error from the memory according to a logical sum signal of an error signal output from the memory in response to a read operation instruction. Processor.   8. The data processor according to claim 7, wherein the plurality of memories are connected to different buses connected by a bus bridge circuit. A CPU that executes a program; a memory or a plurality of memories that are arranged in the address space of the CPU and that reads and writes data; and a memory patrol circuit that is controlled by the CPU;
The memory detects and corrects an error by generating an error correction code from write data in a write operation and storing it together with the data, and performing error correction on the read data using the data and error correction code read in a read operation With
The memory patrol circuit includes a storage circuit that is writable and readable by the CPU, and a patrol control circuit that performs read control of the memory with reference to the storage circuit,
In the memory circuit, a read range of the memory is specified by the CPU in a programmable manner,
When the patrol control circuit is instructed to start a patrol operation by the CPU, the patrol control circuit instructs a read operation to the address of the memory specified in the storage circuit, thereby receiving the presence or absence of an error from the memory, A data processor that holds an address of data related to the error in the storage circuit and requests an interrupt related to the error to the CPU when there is an error. A CPU that executes a program, a memory or a plurality of memories that are arranged in an address space of the CPU and that reads and writes data, and a memory patrol circuit that is controlled by the CPU;
The memory detects and corrects an error by generating an error correction code from write data in a write operation and storing it together with the data, and performing error correction on the read data using the data and error correction code read in a read operation And a write-back control unit that writes the corrected data back to the memory unit when error correction is performed on the read data,
The memory patrol circuit includes a memory circuit that is writable and readable by the CPU, and a patrol control circuit that performs read control of the memory with reference to the memory circuit,
The memory circuit has an error flag storage area that can be referred to by the CPU while the read range of the memory is programmable by the CPU.
When the patrol control circuit is instructed to start a patrol operation by the CPU, the patrol control circuit instructs a read operation to the address of the memory specified in the storage circuit, thereby receiving the presence or absence of an error from the memory, A data processor that holds an address of data relating to an error in the storage circuit and sets an error flag in the error flag storage area when an error occurs.   The memory circuit has a patrol enable bit, and the patrol operation can be started by the CPU setting the patrol enable bit, and the patrol operation is stopped by the patrol control circuit resetting the patrol enable bit. 11. A data processor according to claim 10, enabled. The storage circuit has a storage area for periodic information;
11. The data processor according to claim 10, wherein the control circuit controls an interval of a memory read operation by the patrol operation in accordance with period information set by a CPU.   11. The data according to claim 10, comprising a plurality of the memories, wherein the patrol control circuit receives presence / absence of an error from the memory according to a logical sum signal of an error signal output from the memory in response to a read operation instruction. Processor.   14. The data processor according to claim 13, wherein the plurality of memories are connected to different buses connected by a bus bridge circuit.

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