JP2013045893A - Electronic apparatus, manufacturing method of the same, and oscillator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic apparatus having good characteristics.SOLUTION: An electronic apparatus 100 comprises: a substrate 10; a function element 20 disposed on the substrate 10; and a coating structure 30 defining a cavity part 1 in which the function element 20 is housed. The coating structure 30 comprises: a first coating layer 50 having first through holes communicating with the cavity part 1 and the second through holes 54 larger than the first through holes 52 and being disposed on the cavity part 1; and a second coating layer 58 disposed on the first coating layer 50 and closing the first through holes 52 and the second through holes 54.

Description

  The present invention relates to an electronic device, a manufacturing method thereof, and an oscillator.

  2. Description of the Related Art In general, an electronic device is known in which functional elements such as MEMS (Micro Electro Mechanical Systems) are arranged in a cavity provided on a substrate. MEMS such as micro vibrators, micro sensors, and micro actuators need to be placed in a state in which a minute structure can be vibrated, deformed, or otherwise operated, and thus are housed in an operable state in a cavity. The The inside of the cavity is kept in a reduced pressure state. In such an electronic device, as the degree of vacuum in the cavity is higher, the influence of the viscosity of the gas in the cavity is reduced, and the element characteristics (frequency characteristics, etc.) are improved.

  For example, Patent Document 1 discloses a method for forming a cavity. Specifically, first, a functional element is formed on a substrate, and a sacrificial layer is formed thereon. Next, after forming a conductor film (first covering layer) on the sacrificial layer, a plurality of through holes are formed in the first covering layer. Then, an etchant is injected from the plurality of through holes to remove the sacrificial layer around the functional element and form a cavity. Next, another conductor film (second coating layer) is formed on the first coating layer by sputtering, thereby closing the plurality of through holes and reducing the pressure in the cavity. Through the above steps, a cavity is formed. The plurality of through holes formed in the first coating layer generally have the same size.

JP 2007-35290 A

  The step of closing the through hole and reducing the pressure inside the cavity is performed, for example, by forming a second coating layer by sputtering. Here, in film formation by sputtering, gas is generated from an insulating layer or the like facing the cavity due to heat generated during film formation. During the film forming process, when the through hole is not blocked, this gas is discharged from the through hole to the outside of the cavity. However, after the through hole is closed and the cavity is sealed during the film forming process, this gas is not discharged but stays in the cavity, and the degree of vacuum in the cavity decreases. Therefore, it is desirable that the time from the sealing of the cavity to the end of film formation be short. However, in this process, if the film formation time is set short in order to shorten the time from the sealing of the cavity to the end of film formation, the film formation speed varies between positions in the wafer and between wafers. As a result, all the through holes are not blocked, and the yield may be reduced.

  As described above, in this step, it is difficult to shorten the time from the sealing of the cavity to the end of the film formation, while sealing all the through holes and securely sealing the cavity. is there. Therefore, with the technique disclosed in Patent Document 1, it is difficult to increase the degree of vacuum in the cavity, and it is difficult to obtain an electronic device having good characteristics.

  One of the objects according to some embodiments of the present invention is to provide an electronic device having good characteristics and a method for manufacturing the same. Another object of some aspects of the present invention is to provide an oscillator having the electronic device described above.

An electronic device according to the present invention includes:
A substrate,
A functional element disposed above the substrate;
A covering structure that defines a cavity containing the functional element;
Including
The covering structure is
A first covering layer having a first through hole communicating with the cavity and a second through hole larger than the first through hole, and disposed above the cavity;
A second coating layer disposed above the first coating layer and blocking the through hole;
Have

  According to such an electronic device, since the first covering layer has the first through hole and the second through hole larger than the first through hole, in the step of closing the first through hole and the second through hole, One through hole is closed, and then the second through hole is closed. Thereby, compared with the case where all the through-holes of a 1st coating layer are the same magnitude | size, time after film | membrane formation is complete | finished after sealing a cavity part reliably sealing a cavity part Can be shortened. Therefore, the amount of gas generated in the cavity after the cavity is sealed can be reduced, and the degree of vacuum in the cavity can be increased. Therefore, it can have favorable characteristics.

  In the description according to the present invention, the word “upper” is used, for example, “specifically” (hereinafter referred to as “A”) is formed above another specific thing (hereinafter referred to as “B”). The word “above” is used to include the case where B is formed directly on A and the case where B is formed on A via another object. Used.

In the electronic device according to the present invention,
The first covering layer may have a plurality of the first through holes.

  According to such an electronic device, the etchant and the etching gas can be efficiently supplied in the release process for forming the cavity.

In the electronic device according to the present invention,
The area of the opening of the first through hole is 1 μm ² or more and less than 4 μm ² ,
The area of the opening of the second through hole may be 4 μm ² or more and 7 μm ² or less.

  According to such an electronic device, the etching can be performed satisfactorily in the release process for forming the cavity, and the second through hole is securely blocked in the process of closing the first through hole and the second through hole. be able to.

In the electronic device according to the present invention,
The distance between the side surface of the covering structure that defines the hollow portion and the second through hole may be smaller than the distance between the side surface of the covering structure and the first through hole.

  According to such an electronic device, the gas generated from the side surface of the covering structure can be efficiently discharged in the step of closing the first through hole and the second through hole.

An electronic device manufacturing method according to the present invention includes:
Forming a functional element above the substrate;
Forming an insulating layer above the substrate and the functional element;
Forming a first covering layer having a first through hole and a second through hole larger than the first through hole above the insulating layer;
Supplying an etchant or an etching gas through the first through hole and the second through hole, and etching the insulating layer above the functional element;
Forming a second coating layer over the first coating layer to block the first through hole and the second through hole;
Including
In the step of forming the second coating layer,
The second coating layer is formed by a vapor deposition method.

  According to such a method for manufacturing an electronic device, since the first coating layer has the first through hole and the second through hole larger than the first through hole, the step of closing the first through hole and the second through hole. , The first through hole is closed, and then the second through hole is closed. Thereby, compared with the case where all the through-holes of a 1st coating layer are the same magnitude | size, time after film | membrane formation is complete | finished after sealing a cavity part reliably sealing a cavity part Can be shortened. Therefore, the amount of gas generated in the cavity after the cavity is sealed can be reduced, and the degree of vacuum in the cavity can be increased. Therefore, an electronic device having favorable characteristics can be obtained.

In the method for manufacturing an electronic device according to the present invention,
The second coating layer may have a plurality of the first through holes.

  According to such a method for manufacturing an electronic device, an etching solution and an etching gas can be efficiently supplied in a release process for forming a cavity.

The oscillator according to the present invention is
An electronic device according to the present invention;
A circuit unit electrically connected to the functional element of the electronic device;
Including
The functional element is a vibrator.

  Such an oscillator can have good characteristics.

FIG. 6 is a cross-sectional view schematically showing the electronic device according to the embodiment. FIG. 3 is a plan view schematically showing the electronic apparatus according to the embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the electronic apparatus which concerns on the modification of this embodiment. The top view which shows typically the electronic device which concerns on the modification of this embodiment. The circuit diagram which shows the oscillator concerning this embodiment. The circuit diagram which shows the oscillator which concerns on the modification of this embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, not all of the configurations described below are essential constituent requirements of the present invention.

1. Electronic Device First, an electronic device according to the present embodiment will be described with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing an electronic device 100 according to this embodiment. FIG. 2 is a plan view schematically showing the electronic device 100 according to the present embodiment. 1 is a cross-sectional view taken along the line II of FIG. In FIG. 2, the second covering layer 58, the surrounding wall 40, the interlayer insulating layers 60 and 62, and the passivation layer 70 are omitted for convenience.

  As shown in FIGS. 1 and 2, the electronic device 100 includes a substrate 10, a functional element 20, and a covering structure 30. The electronic device 100 can further include a first wiring layer 26, a second wiring layer 28, a third wiring layer 29, an enclosure wall 40, and a passivation layer 70.

  As shown in FIG. 1, the substrate 10 can include a support substrate 12, a first base layer 14, and a second base layer 16.

  As the support substrate 12, a semiconductor substrate such as a silicon substrate can be used. As the support substrate 12, various substrates such as a ceramic substrate, a glass substrate, a sapphire substrate, a diamond substrate, and a synthetic resin substrate may be used.

  The first foundation layer 14 is formed on the support substrate 12. For example, a trench insulating layer, a LOCOS (local oxidation of silicon) insulating layer, or a semi-recessed LOCOS insulating layer can be used as the first base layer 14. The first foundation layer 14 can electrically isolate the functional element 20 from other elements (for example, a transistor, not shown).

  The second underlayer 16 is formed on the first underlayer 14. As the second underlayer 16, for example, a silicon nitride layer can be used. The second underlayer 16 can function as an etching stopper layer in the release process for forming the cavity 1.

  The functional element 20 is disposed on the substrate 10. The functional element 20 is accommodated in the cavity 1. In the illustrated example, the functional element 20 is a vibrator having a first electrode 22 formed on the second underlayer 16 and a second electrode 24 formed at a distance from the first electrode 22. . The second electrode 24 includes a support portion 24a formed on the second underlayer 16 and a beam portion 24b extending from the support portion 24a and arranged with a gap between the first electrode 22. Can have. That is, it can be said that the functional element 20 is a cantilever type MEMS vibrator. Examples of the material of the first electrode 22 and the second electrode 24 include polycrystalline silicon imparted with conductivity by doping a predetermined impurity.

  In the illustrated example, two second electrodes 24 are provided for one first electrode 22. The two second electrodes 24 may have different natural frequencies or the same natural frequency. In addition, the number of the 2nd electrodes 24 with respect to one 1st electrode 22 is not specifically limited.

  The functional element 20 is not limited to the illustrated example, and may be, for example, a double-supported beam type vibrator in which both ends of the beam portion are fixed. In addition, the functional element 20 includes a first electrode portion and a second beam portion in which the second electrode includes a support portion, and a first beam portion and a second beam portion that extend in opposite directions from the support portion. A vibrator in which a first electrode is formed opposite to each of the first and second electrodes may be used. In addition, the functional element 20 may be various functional elements such as a quartz vibrator, a SAW (surface acoustic wave) element, an acceleration sensor, a gyroscope, and a microactuator other than the vibrator. That is, the electronic device 100 can include any functional element that can be accommodated in the cavity 1.

  For example, the first wiring layer 26 is connected to the first electrode 22 of the functional element 20. The first wiring layer 26 may be formed integrally with the first electrode 22. For example, the second wiring layer 28 is connected to the second electrode 24 of the functional element 20. The second wiring layer 28 may be formed integrally with the second electrode 24. The first wiring layer 26 and the second wiring layer 28 are extended to the outside of the surrounding wall 40. The third wiring layer 29 electrically connects the two second electrodes 24. As a material of the first wiring layer 26, the second wiring layer 28, and the third wiring layer 29, for example, polycrystalline silicon imparted with conductivity by doping a predetermined impurity can be cited.

  The first wiring layer 26 and the second wiring layer 28 are electrically connected to a power supply unit (not shown). When a voltage is applied between the first electrode 22 and the second electrode 24 via the wiring layers 26 and 28, the beam portion 24 b has a thickness of the substrate 10 due to an electrostatic force generated between the electrodes 22 and 24. Can vibrate in the direction.

  The covering structure 30 defines the cavity 1 in which the functional element 20 is accommodated. In the illustrated example, the covering structure 30 includes a first covering layer 50, a second covering layer 58, and interlayer insulating layers 60 and 62. The planar shape of the cavity 1 defined by the covering structure 30 (the shape in plan view from the thickness direction of the substrate 10) is not particularly limited as long as the functional element 20 can be accommodated. It is an arbitrary shape such as a polygonal shape. The planar shape of the cavity 1 is a quadrangle in the illustrated example.

  The first coating layer 50 covers the cavity 1. The first coating layer 50 has a first through hole 52 and a second through hole 54. The first through hole 52 and the second through hole 54 communicate with the cavity 1. As will be described later, in the release process for forming the cavity 1, an etching solution or an etching gas can be supplied through the first through hole 52 and the second through hole 54. As the first covering layer 50, for example, an aluminum layer can be used. For example, the first covering layer 50 is formed integrally with the second metal layer 46.

The planar shapes of the first through hole 52 and the second through hole 54 are not particularly limited, and may be, for example, a circle, an ellipse, or a polygon. The planar shape of the first through hole 52 and the second through hole 54 is a square in the illustrated example. The second through hole 54 is larger than the first through hole 52. That is, the area of the opening of the second through hole 54 is larger than the area of the opening of the first through hole 52. In other words, the area of the second through hole 54 in plan view (the area in plan view from the thickness direction of the substrate 10) is larger than the area of the first through hole 52 in plan view. Specifically, the area of the opening of the first through hole 52 is 1 μm ² or more and less than 4 μm ² . The area of the opening of the second through hole 54 is 4 μm ² or more and 7 μm ² or less.

  The first coating layer 50 has a plurality (36 in the illustrated example) of first through holes 52. The first through holes 52 are arranged in a plurality of rows and a plurality of columns, for example. Further, the first through hole 52 is disposed so as to avoid the upper portion of the beam portion 24 b of the second electrode 24. That is, the first through hole 52 and the beam portion 24 b of the second electrode 24 do not overlap in plan view from the thickness direction of the substrate 10. The arrangement of the first through holes 52 is not particularly limited as long as the cavity 1 can be formed in the release process for forming the cavity 1.

  The first coating layer 50 has a plurality of (two in the illustrated example) second through holes 54. In addition, the number of the 2nd through-holes 54 is not specifically limited, For example, one may be sufficient and three or more may be sufficient. The number of second through holes 54 is, for example, smaller than the number of first through holes 52. For example, the second through hole 54 is disposed in the vicinity of the side surface 32 of the covering structure 30 that defines the cavity 1 (in the illustrated example, the side surfaces 61 and 63 of the interlayer insulating layers 60 and 62). For example, the distance L <b> 2 between the side surface 32 of the covering structure 30 and the second through hole 54 is smaller than the distance L <b> 1 between the side surface 32 of the covering structure 30 and the first through hole 54. Here, the distance L2 between the side surface 32 of the covering structure 30 and the second through hole 54 refers to the shortest distance between the side surface 32 of the covering structure 30 and the second through hole 54. Similarly, the distance L1 between the side surface 32 of the covering structure 30 and the first through hole 52 refers to the shortest distance between the side surface 32 of the covering structure 30 and the first through hole 52. The position of the second through hole 54 is not limited to the illustrated example, and may be disposed at an arbitrary position.

  The second coating layer 58 is disposed on the first coating layer 50. The second covering layer 58 closes the first through hole 52 and the second through hole 54. Thereby, it is possible to prevent gas or the like from entering the hollow portion 1 from the outside through the through holes 52 and 54. For example, the second covering layer 58 closes all the through holes 52 and 54 provided in the first covering layer 50. As the 2nd coating layer 58, the laminated body of an aluminum layer, a titanium layer, or an aluminum layer and a titanium layer can be used, for example. The first coating layer 50 and the second coating layer 58 can function as a sealing member that covers the cavity 1 from above and seals the cavity 1.

  The first interlayer insulating layer 60 and the second interlayer insulating layer 62 are formed on the second base layer 16 as shown in FIG. The electronic device 100 includes two interlayer insulating layers 60 and 62, but the number thereof is not particularly limited, and can be appropriately changed depending on the number of metal layers, for example. The side surface 61 of the first interlayer insulating layer 60 and the side surface 63 of the second interlayer insulating layer 62 constitute the side surface 32 of the covering structure 30. That is, the side surfaces 61 and 63 of the interlayer insulating layers 60 and 62 face the cavity 1. As the interlayer insulating layers 60 and 62, for example, a silicon oxide layer can be used. A silicon oxide layer 42 may be formed between the first interlayer insulating layer 60 and the first wiring 26.

  Here, although the case where the covering structure 30 is configured to include the first covering layer 50, the second covering layer 58, and the interlayer insulating layers 60 and 62 has been described, For example, although not illustrated, the first covering layer 50, the second covering layer 58, and the surrounding wall 40 may be included. That is, the side surface of the covering structure 30 may be configured by the side surface of the surrounding wall 40.

  The surrounding wall 40 is formed on the second foundation layer 16 and around the cavity portion 1. In the illustrated example, the surrounding wall 40 is embedded in the interlayer insulating layers 60 and 62. The surrounding wall 40 has a shape surrounding the functional element 20 in a plan view from the thickness direction of the substrate 10. The planar shape of the surrounding wall 40 is not specifically limited, For example, it is arbitrary shapes, such as circular shape and polygonal shape.

  For example, as shown in FIG. 1, the surrounding wall 40 includes a first metal layer 44 and a second metal layer 46. In the illustrated example, the first metal layer 44 and the second metal layer 46 are laminated in this order from the substrate 10 side. As the metal layers 44 and 46, for example, an aluminum layer, a titanium layer, or a stacked body of an aluminum layer and a titanium layer can be used. In the illustrated example, the surrounding wall 40 includes two metal layers 44 and 46, but the number of metal layers is not particularly limited, and may be one or three or more.

  It is desirable that a constant potential (for example, ground potential) is applied to the metal layers 44 and 46 and the first covering layer 50 of the surrounding wall 40. Thereby, the metal layers 44 and 46 and the 1st coating layer 50 can be functioned as an electromagnetic shield. Therefore, the functional element 20 can be electrically shielded from the outside. Thereby, the functional element 20 can have more stable characteristics.

  The passivation layer 70 is formed on the second interlayer insulating layer 62. For example, a silicon nitride layer can be used as the passivation layer 70.

  The electronic device 100 according to the present embodiment has the following features, for example.

  In the electronic device 100, the covering structure 30 has a first through hole 52 and a second through hole 54, and the second through hole 54 is larger than the first through hole 52. Therefore, even when all the first through holes 52 are closed in the step of closing the first through holes 52 and the second through holes 54 as compared with the case where all the through holes of the first covering layer are the same size. The second through hole 54 is not closed, and the second through hole 54 is closed at the final stage of the process. Thereby, it is possible to shorten the time from the sealing of the cavity to the end of film formation while reliably sealing the cavity. Therefore, the amount of gas generated in the cavity after the cavity is sealed can be reduced, and the degree of vacuum in the cavity can be increased. Therefore, the electronic device 100 can have good characteristics. The reason will be described below.

  In film formation by sputtering, gas is generated from an insulating layer or the like facing the cavity due to heat generated during film formation. Therefore, after the through hole is closed and the cavity is sealed during the film forming process, this gas is not discharged but stays in the cavity, and the degree of vacuum of the cavity is reduced. Therefore, it is desirable that the time from the sealing of the cavity to the end of film formation be short. However, in this process, if the film formation time is set short in order to shorten the time from the sealing of the cavity to the end of film formation, the film formation speed varies between positions in the wafer and between wafers. As a result, all the through holes are not blocked, and the yield may be reduced.

  In the electronic device 100, when the second coating layer 58 is formed by sputtering in the step of closing the through holes 52 and 54, the first through hole 52 is first closed. At this time, since the second through hole 54 is larger than the first through hole 52, it is not blocked. Therefore, the gas generated in the cavity 1 is exhausted from the second through hole 54. When the film formation is further advanced, the second through hole 54 is closed and the cavity 1 is sealed. Therefore, compared with the case where all the through holes are the same size, the time from the sealing of the cavity to the end of film formation can be shortened while reliably sealing the cavity. . Therefore, the degree of vacuum in the cavity 1 can be increased.

  Here, the case where the second coating layer 58 is formed by the sputtering method has been described, but the same problem arises by other vapor phase growth methods such as the CVD method. According to the electronic device 100, even in such a case, the degree of vacuum in the cavity 1 can be increased similarly.

  In the electronic device 100, the first coating layer 50 can have a plurality of first through holes 52. Thereby, an etching liquid and etching gas can be efficiently supplied in the release process which forms the cavity part 1. FIG.

In the electronic device 100, the opening area of the first through hole 52 is 1 μm ² or more and less than 4 μm ² , and the opening area of the second through hole 54 is 4 μm ² or more and 7 μm ² or less. When the area of the opening of the through hole is smaller than 1 μm ^2, it may be impossible to perform etching through the through hole in the release process for forming the cavity. When the area of the opening of the through hole is larger than 7 μm ² , the through hole may not be reliably blocked in the step of closing the through hole. Therefore, when the area of the opening of the first through-hole 52 and the area of the opening of the second through-hole 54 are in the above range, good etching can be performed in the release process for forming the cavity 1, and In the step of closing the through holes 52 and 54, the through holes 52 and 54 can be reliably closed.

  In the electronic device 100, the distance L <b> 2 between the side surface 32 of the covering structure 30 and the second through hole 54 is smaller than the distance L <b> 1 between the side surface 32 of the covering structure 30 and the first through hole 52. Thereby, in the process of closing the through holes 52 and 54, the gas generated from the side surface 32 of the covering structure 30 can be efficiently discharged.

  In the electronic device 100, the first through hole 52 is disposed so as to avoid the upper portion of the beam portion 24 b of the second electrode 24. Thereby, in the step of closing the through holes 52 and 54, the material constituting the second coating layer 58 enters the cavity 1 through the through holes 52 and 54, and the material enters the beam portion 24 b of the functional element 20. Accumulation can be prevented.

2. Next, a method for manufacturing an electronic device according to the present embodiment will be described with reference to the drawings. 3-8 is sectional drawing which shows typically the manufacturing process of the electronic device 100 which concerns on this embodiment. 3 to 8 correspond to FIG.

  As shown in FIG. 3, the first base layer 14 and the second base layer 16 are formed in this order on the support substrate 12 to obtain the substrate 10. The first underlayer 14 is formed by, for example, an STI (shallow trench isolation) method or a LOCOS method. The second underlayer 16 is formed by, for example, a CVD (Chemical Vapor Deposition) method or a sputtering method.

  As shown in FIG. 4, the first electrode 22 and the first wiring layer 26 connected to the first electrode 22 are formed on the second base layer 16. The first electrode 22 and the first wiring layer 26 can be integrally formed. More specifically, the first electrode 22 and the first wiring layer 26 are formed by being patterned by a CVD method, a sputtering method, or the like and then patterned by a photolithography technique and an etching technique. When the first electrode 22 and the first wiring layer 26 are made of polycrystalline silicon, a predetermined impurity is doped in order to impart conductivity.

  Next, a sacrificial layer 23 that covers the first electrode 22 is formed by performing thermal oxidation treatment. The sacrificial layer 23 may cover the first wiring layer 26 as shown in FIG. Thereby, the silicon oxide layer 42 is formed.

  Next, the second electrode 24 is formed on the sacrificial layer 23, and the second wiring layer 28 is formed on the second base layer 16. The second electrode 24 and the second wiring layer 28 can be integrally formed. The second electrode 24 and the second wiring layer 28 are formed by, for example, a film forming process and a patterning process similar to the first electrode 22 and the first wiring layer 26. When the second electrode 24 and the second wiring layer 28 are made of polycrystalline silicon, a predetermined impurity is doped to impart conductivity.

  As shown in FIG. 5, a first interlayer insulating layer 60 is formed above the substrate 10. The first interlayer insulating layer 60 can be formed by, for example, a CVD method or a coating (spin coating) method. After forming the first interlayer insulating layer 60, a process for planarizing the surface of the first interlayer insulating layer 60 may be performed.

  Next, the first metal layer 44 is formed on the first interlayer insulating layer 60. The first metal layer 44 is formed by, for example, patterning after being formed by sputtering, plating, or the like.

  As shown in FIG. 6, a second interlayer insulating layer 62 is formed on the first interlayer insulating layer 60. The second interlayer insulating layer 62 is formed by, for example, the same method as the first interlayer insulating layer 60. Next, the second interlayer insulating layer 62 is patterned to form an opening 62a so that the first metal layer 44 is exposed.

  Next, the second metal layer 46 is formed in the opening 62 a, and further, the first covering layer 50 is formed above the functional element 20. The second metal layer 46 and the first covering layer 50 can be integrally formed. The second metal layer 46 and the first covering layer 50 are formed by the same method as the first metal layer 44, for example. The surrounding wall 40 can be formed by the above process. Next, the 1st coating layer 50 is patterned and the 1st through-hole 52 and the 2nd through-hole 54 (refer FIG. 2) are formed.

  As shown in FIG. 7, a passivation layer 70 is formed on the second interlayer insulating layer 62. The passivation layer 70 is formed by, for example, patterning after being formed by a CVD method, a sputtering method, or the like. The passivation layer 70 is patterned so that an opening 70 a is formed above the functional element 20.

  As shown in FIG. 8, the interlayer insulating layers 60 and 62 and the sacrificial layer 23 above the functional element 20 are etched (removed) through the through holes 52 and 54 to form the cavity 1 (release process). Etching is performed, for example, by wet etching using an etchant such as hydrofluoric acid or buffered hydrofluoric acid (mixed liquid of hydrofluoric acid and ammonium fluoride). Etching may be performed by dry etching using an etching gas such as hydrogen fluoride gas.

  As shown in FIG. 1, a second coating layer 58 is formed on the first coating layer 50. Thereby, the through holes 52 and 54 can be closed, and the cavity 1 can be sealed. The second coating layer 58 can be formed by, for example, a vapor phase growth method such as a sputtering method or a CVD method. Thereby, the cavity part 1 can be sealed with a reduced pressure state.

  In this step, when the film formation of the second coating layer 58 is started, first, the first through hole 52 is closed. At this time, since the second through hole 54 is larger than the first through hole 52, it is not blocked. Therefore, the gas generated in the cavity 1 is exhausted from the second through hole 54. When the film formation is further advanced, the second through hole 54 is closed and the cavity 1 is sealed. The covering structure 30 can be formed by the above steps.

  The electronic device 100 according to the present embodiment can be manufactured through the above steps.

  The method for manufacturing the electronic device 100 according to the present embodiment has, for example, the following characteristics.

  According to the method for manufacturing the electronic device 100, the covering structure 30 has the first through hole 52 and the second through hole 54, and the second through hole 54 is larger than the first through hole 52. As described above, it is possible to shorten the time from the sealing of the cavity to the end of the film formation while reliably sealing the cavity. Therefore, the amount of gas generated in the cavity after the cavity is sealed can be reduced, and the degree of vacuum in the cavity can be increased. Therefore, an electronic device having favorable characteristics can be obtained.

  According to the method for manufacturing the electronic device 100, the first coating layer 50 can have a plurality of first through holes 52. Thereby, an etching liquid and etching gas can be efficiently supplied in the release process which forms the cavity part 1. FIG.

According to the method for manufacturing the electronic device 100, the area of the opening of the first through hole 52 is 1 μm ² or more and less than 4 μm ² , and the area of the opening of the second through hole 54 is 4 μm ² or more and 7 μm ² or less. Formed. Thereby, favorable etching can be performed in the release process for forming the cavity 1, and the through holes 52 and 54 can be reliably closed in the process of closing the through holes 52 and 54.

  According to the method for manufacturing the electronic device 100, the distance L2 between the side surface 32 of the covering structure 30 and the second through hole 54 is equal to the distance L1 between the side surface 32 of the covering structure 30 and the first through hole 52. It is formed so as to be smaller. Thereby, in the process of closing the through holes 52 and 54, the gas generated from the side surface 32 of the covering structure 30 can be efficiently discharged.

  According to the method for manufacturing the electronic device 100, the first through hole 52 is formed so as to be disposed above the beam portion 24 b of the second electrode 24. Thus, in the step of closing the through holes 52 and 54, the material constituting the second coating layer 58 enters the cavity 1 through the through holes 52 and 54 and is deposited on the beam 24 b of the functional element 20. Can be prevented.

3. Next, an electronic device according to a modification of the present embodiment will be described with reference to the drawings. FIG. 9 is a cross-sectional view schematically showing an electronic device 200 according to a modification of the present embodiment. FIG. 10 is a plan view schematically showing an electronic device 200 according to a modification of the present embodiment. 9 is a cross-sectional view taken along line IX-IX in FIG. In FIG. 10, the second covering layer 58, the surrounding wall 40, the interlayer insulating layers 60 and 62, and the passivation layer 70 are omitted for convenience. Hereinafter, in the electronic device 200 according to the modified example of the present embodiment, members having the same functions as the constituent members of the electronic device 100 according to the present embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the example of the electronic device 100 described above, as shown in FIGS. 1 and 2, two second electrodes 24 are provided for one first electrode 22.

  On the other hand, in the electronic device 200, as shown in FIGS. 9 and 10, one second electrode 24 is provided for one first electrode 22.

  According to the electronic device 200, the same effects as the electronic device 100 can be achieved.

  The manufacturing method of the electronic device 200 is the same as the manufacturing method of the electronic device 100 described above, except that one second electrode 24 is provided for one first electrode 22, and the description thereof is omitted. .

4). Oscillator Next, an oscillator according to this embodiment will be described with reference to the drawings. FIG. 11 is a circuit diagram showing the oscillator 400 according to the present embodiment.

  As shown in FIG. 11, the oscillator 400 includes an electronic device (for example, the electronic device 200) according to the present invention and an inverting amplifier circuit 410.

  The electronic device 200 has a first terminal 200 a electrically connected to the first wiring layer 26 and a second terminal 200 b electrically connected to the second wiring layer 28. The first terminal 200a of the electronic device 200 is at least AC connected to the input terminal 410a of the inverting amplifier circuit 410. The second terminal 200b of the electronic device 200 is connected to the output terminal 410b of the inverting amplifier circuit 410 at least in an AC manner.

  In the illustrated example, the inverting amplifier circuit 410 is configured by one inverter, but may be configured by combining a plurality of inverters (inverting circuits) and amplifier circuits so that a desired oscillation condition is satisfied. .

  The oscillator 400 may include a feedback resistor for the inverting amplifier circuit 410. In the example shown in FIG. 11, the input terminal and the output terminal of the inverter 412 are connected via a resistor 420.

  The oscillator 400 includes a first capacitor 430 connected between the input terminal 410a of the inverting amplifier circuit 410 and a reference potential (ground potential), and between the output terminal 410b of the inverting amplifier circuit 410 and the reference potential (ground potential). And a second capacitor 432 connected to the second capacitor 432. As a result, the electronic device 200 and the capacitors 430 and 432 can form an oscillation circuit that forms a resonance circuit. The oscillator 400 outputs the oscillation signal f obtained by this oscillation circuit.

  Elements (not shown) such as transistors and capacitors constituting the oscillator 400 may be formed on the substrate 10 (see FIG. 9), for example. Thereby, the electronic device 200 and the anti-amplification circuit 410 can be formed monolithically.

  When an element such as a transistor constituting the oscillator 400 is formed on the substrate 10, the element such as a transistor constituting the oscillator 400 is formed in the same process as the process for forming the electronic device 200 (electronic device 100) described above. May be. Specifically, a gate insulating layer of a transistor may be formed in the step of forming the sacrificial layer 23 (see FIG. 4). Further, in the step of forming the second electrode 24 (see FIG. 4), a gate electrode of a transistor may be formed. In this way, by simplifying the manufacturing process of the electronic device 200 and the manufacturing process of the elements such as the transistors constituting the oscillator 400, the manufacturing process can be simplified.

  The oscillator 400 includes the electronic device 200 having good characteristics. Therefore, the oscillator 400 can have good characteristics.

The oscillator 400 may further include a frequency dividing circuit 440 as shown in FIG. The frequency dividing circuit 440 divides the output signal _Vout of the oscillation circuit and outputs the oscillation signal f. Thereby, the oscillator 400 can obtain an output signal having a frequency lower than the frequency of the output signal _Vout , for example.

  In addition, embodiment mentioned above and a modification are examples, Comprising: It is not necessarily limited to these. For example, a plurality of embodiments and modifications can be combined as appropriate.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

DESCRIPTION OF SYMBOLS 1 Cavity part, 10 board | substrates, 12 support substrates, 14 1st foundation layers, 16 2nd foundation layers,
20 functional elements, 22 1st electrode, 23 sacrificial layer, 24 2nd electrode, 24a support part,
24b Beam part, 26 1st wiring layer, 28 2nd wiring layer, 29 3rd wiring layer,
30 covering structure, 32 side surface, 40 surrounding wall, 42 silicon oxide layer,
44 1st metal layer, 46 2nd metal layer, 50 1st coating layer, 52 1st through-hole,
54 second through hole, 58 second covering layer, 60 first interlayer insulating layer, 61 side surface,
62 second interlayer insulating layer, 62a opening, 63 side surface, 70 passivation layer,
70a opening, 100,200 electronic device, 200a first terminal,
200b second terminal, 400 oscillator, 410 inverting amplifier circuit, 410a input terminal,
410b output terminal, 412, 414, 416 inverter,
420, 422, 424 resistor, 430 first capacitor,
432 Second capacitor, 440 frequency divider

Claims (7)

A substrate,
A functional element disposed above the substrate;
A covering structure that defines a cavity containing the functional element;
Including
The covering structure is
A first covering layer having a first through hole communicating with the cavity and a second through hole larger than the first through hole, and disposed above the cavity;
A second coating layer disposed above the first coating layer and blocking the through hole;
An electronic device. In claim 1,
The first covering layer is an electronic device having a plurality of the first through holes. In claim 1 or 2,
The area of the opening of the first through hole is 1 μm ² or more and less than 4 μm ² ,
The area of the opening of the second through hole is an electronic device that is 4 μm ² or more and 7 μm ² or less. In any one of Claims 1 thru | or 3,
An electronic device, wherein a distance between a side surface of the covering structure that defines the hollow portion and the second through hole is smaller than a distance between a side surface of the covering structure and the first through hole. Forming a functional element above the substrate;
Forming an insulating layer above the substrate and the functional element;
Forming a first covering layer having a first through hole and a second through hole larger than the first through hole above the insulating layer;
Supplying an etchant or an etching gas through the first through hole and the second through hole, and etching the insulating layer above the functional element;
Forming a second coating layer over the first coating layer to block the first through hole and the second through hole;
Including
In the step of forming the second coating layer,
The method for manufacturing an electronic device, wherein the second coating layer is formed by vapor deposition. In claim 5,
The method for manufacturing an electronic device, wherein the second coating layer includes a plurality of the first through holes. An electronic device according to any one of claims 1 to 4,
A circuit unit electrically connected to the functional element of the electronic device;
Including
The functional element is an oscillator.

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