JP6060569B2 - Manufacturing method of electronic device - Google Patents

Description

  The present invention relates to an electronic device manufacturing method.

  MEMS (Micro Electro Mechanical Systems) is one of micro structure forming techniques, and refers to, for example, a technique for producing a micro electro-mechanical system of micron order and its product.

  In recent years, MEMS devices based on such semiconductor manufacturing techniques have been widely used. In particular, demand for MEMS elements (MEMS vibrators) in the oscillator market has been increasing year by year. Such an oscillator structure includes a case where the MEMS vibrator and the operating circuit of the oscillator are formed on separate semiconductor substrates (semiconductor chips), and a case where the MEMS vibrator and the operating circuit of the oscillator are formed on the same substrate. It is divided roughly.

  When the MEMS vibrator and the operation circuit of the oscillator are formed by separate semiconductor chips, it is common to mount the respective semiconductor chips on separate packages and connect them by wire bonding or the like. However, in this case, package cost and mounting cost are required, which is disadvantageous in cost compared to the case where the MEMS vibrator and the operation circuit of the oscillator are formed on the same substrate.

  On the other hand, when the MEMS vibrator and the operation circuit of the oscillator are formed on the same substrate, there is a problem that the manufacturing process increases. With respect to this problem, in Patent Document 1, the lower electrode of the ONO capacitor unit is formed using the first silicon layer, and the lower structure of the MEMS structure unit and the upper electrode of the ONO capacitor unit are formed of the second silicon layer. Forming the upper structure of the MEMS structure portion and the gate electrode of the CMOS circuit portion using the third silicon layer, thereby simplifying the manufacturing process and reducing the cost.

  In such an electronic device having a MEMS vibrator and a circuit portion formed on the same substrate, it is desired to further simplify the manufacturing process.

JP 2008-153817 A

  One of the objects according to some aspects of the present invention is to provide an electronic device manufacturing method capable of simplifying the manufacturing process. Another object of some aspects of the present invention is to provide an electronic device that can simplify the manufacturing process.

An electronic device manufacturing method according to the present invention includes:
A method of manufacturing an electronic device having a MEMS vibrator and a circuit unit formed above a substrate,
Forming a first structure constituting the MEMS vibrator and a first electrode of a capacitor constituting the circuit unit using a first silicon layer;
Forming a sacrificial layer covering the first structure;
Forming a second structure constituting the MEMS vibrator, a second electrode of the capacitor constituting the circuit unit, and a gate electrode of a transistor constituting the circuit unit using a second silicon layer; When,
Removing the sacrificial layer to form a gap between the first structure and the second structure;
including.

  According to such an electronic device manufacturing method, the first structure and the first electrode can be formed in the same process by forming the first structure and the first electrode using the first silicon layer. it can. Furthermore, the second structure, the second electrode, and the gate electrode can be formed in the same step by forming the second structure, the second electrode, and the gate electrode using the second silicon layer. Therefore, the manufacturing process can be simplified.

  In the description according to the present invention, the word “upper” is used, for example, “specifically” (hereinafter referred to as “A”) is formed above another specific thing (hereinafter referred to as “B”). The word “above” is used to include the case where B is formed directly on A and the case where B is formed on A via another object. Used.

In the method for manufacturing an electronic device according to the present invention,
Before the step of forming the second structure, the second electrode, and the gate electrode using the second silicon layer, a first oxide film that covers the first structure and the first electrode is formed. Process,
Forming a second oxide film covering the first structure covered with the first oxide film, and a gate insulating film constituting the transistor by thermal oxidation;
Including
The sacrificial layer is formed of the first oxide film and the second oxide film,
In the step of forming the second structure, the second electrode, and the gate electrode using the second silicon layer, the second structure is formed above the second oxide film, and the gate insulating film The gate electrode may be formed above the gate.

  According to such an electronic device manufacturing method, the layer for forming a gap between the first structure and the second structure and the dielectric layer of the capacitor are formed in the same process. Can do. Furthermore, the layer for forming the gap between the first structure and the second structure and the gate insulating film can be formed in the same process. Therefore, the manufacturing process can be simplified. Furthermore, the size of the gap between the first structure and the second structure can be controlled by the thicknesses of the first oxide film and the second oxide film.

In the method for manufacturing an electronic device according to the present invention,
Before the step of forming the second structure, the second electrode, and the gate electrode using the second silicon layer, a first oxide film that covers the first structure and the first electrode is formed. Process,
Removing the first oxide film covering the first structure;
Forming a second oxide film covering the first structure from which the first oxide film has been removed, and a gate insulating film constituting the transistor by thermal oxidation;
Including
The sacrificial layer is formed of the second oxide film,
In the step of forming the second structure, the second electrode, and the gate electrode using the second silicon layer, the second structure is formed above the second oxide film, and the gate insulating film The gate electrode may be formed above the gate.

  According to such a method for manufacturing an electronic device, the layer and the gate insulating film can be formed in the same process in order to form a gap (gap) between the first structure and the second structure. Therefore, the manufacturing process can be simplified. Further, the size of the gap between the first structure and the second structure can be controlled by the thickness of the second oxide film.

An electronic device manufacturing method according to the present invention includes:
A method of manufacturing an electronic device having a MEMS vibrator and a circuit unit formed above a substrate,
Forming a first structure constituting the MEMS vibrator, a first electrode of a capacitor constituting the circuit unit, and a gate electrode of a transistor constituting the circuit unit using a first silicon layer; ,
Forming a sacrificial layer covering the first structure;
Forming a second electrode of the capacitor constituting the circuit portion and a second structure constituting the MEMS vibrator using a second silicon layer;
Removing the sacrificial layer to form a gap between the first structure and the second structure;
including.

  According to such an electronic device manufacturing method, the first structure, the first electrode, and the gate electrode are formed by using the first silicon layer to form the first structure, the first electrode, and the gate electrode. Can be formed in the same step. Furthermore, by forming the second structure body and the second electrode using the second silicon layer, the second structure body and the second electrode can be formed in the same process. Therefore, the manufacturing process can be simplified.

An electronic device according to the present invention includes:
An electronic device having a MEMS vibrator and a circuit unit formed above a substrate,
The MEMS vibrator is
A first structure;
A second structure formed so as to be vibrated by an electrostatic force between the first structure and a gap between the first structure and the first structure;
Have
The circuit section is
A capacitor comprising a first electrode and a second electrode facing the first electrode;
A transistor with a gate electrode;
Have
The first structure of the MEMS vibrator and the first electrode of the capacitor are formed using a first silicon layer,
The second structure of the MEMS vibrator, the second electrode of the capacitor, and the gate electrode of the transistor are formed using a second silicon layer.

  According to such an electronic device, the first structure of the MEMS vibrator and the first electrode of the capacitor are formed using the first silicon layer, and the second structure of the MEMS vibrator and the second electrode of the capacitor are formed. Since the gate electrode of the transistor is formed using the second silicon layer, the manufacturing process can be simplified.

An electronic device according to the present invention includes:
An electronic device having a MEMS vibrator and a circuit unit formed above a substrate,
The MEMS vibrator is
A first structure;
A second structure formed so as to be vibrated by an electrostatic force between the first structure and a gap between the first structure and the first structure;
Have
The circuit section is
A capacitor comprising a first electrode and a second electrode facing the first electrode;
A transistor with a gate electrode;
Have
The first structure of the MEMS vibrator, the first electrode of the capacitor, and the gate electrode of the transistor are formed using a first silicon layer,
The second structure of the MEMS vibrator and the second electrode of the capacitor are formed using a second silicon layer.

  According to such an electronic device, the first structure of the MEMS vibrator, the first electrode of the capacitor, and the gate electrode of the transistor are formed using the first silicon layer, and the second structure of the MEMS vibrator Since the second electrode of the capacitor is formed using the second silicon layer, the manufacturing process can be simplified.

FIG. 3 is a cross-sectional view schematically showing the electronic device according to the first embodiment. 1 is a circuit diagram showing an electronic device according to a first embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on the modification of 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on the modification of 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on the modification of 1st Embodiment. Sectional drawing which shows the electronic device which concerns on 2nd Embodiment typically. Sectional drawing which shows the manufacturing process of the electronic device which concerns on 2nd Embodiment typically. Sectional drawing which shows the manufacturing process of the electronic device which concerns on 2nd Embodiment typically. Sectional drawing which shows the manufacturing process of the electronic device which concerns on 2nd Embodiment typically. Sectional drawing which shows the manufacturing process of the electronic device which concerns on 2nd Embodiment typically. Sectional drawing which shows the manufacturing process of the electronic device which concerns on 2nd Embodiment typically. Sectional drawing which shows the manufacturing process of the electronic device which concerns on 2nd Embodiment typically. Sectional drawing which shows the manufacturing process of the electronic device which concerns on 2nd Embodiment typically. Sectional drawing which shows the manufacturing process of the electronic device which concerns on 2nd Embodiment typically.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, not all of the configurations described below are essential constituent requirements of the present invention.

1. 1. First embodiment 1.1. Electronic Device First, an electronic device according to a first embodiment will be described with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing an electronic device 100 according to the first embodiment.

  As shown in FIG. 1, the electronic device 100 includes a substrate 10, a MEMS vibrator 20, and a circuit unit 3. Furthermore, the electronic device 100 includes the first underlayer 12, the second underlayer 14, the interlayer insulating layers 50 and 52, the surrounding wall 60, the first covering layer 70, the second covering layer 72, and the passivation layer. 90.

  For example, a semiconductor substrate such as a silicon substrate is used as the substrate 10. As the substrate 10, various substrates such as a ceramic substrate, a glass substrate, a sapphire substrate, a diamond substrate, and a synthetic resin substrate may be used. Above the substrate 10, the MEMS vibrator 20 and the circuit unit 3 are formed. That is, the MEMS vibrator 20 and the circuit unit 3 are formed on the same substrate 10.

  The first foundation layer 12 is formed on the substrate 10. The first underlayer 12 is, for example, a LOCOS (local oxidation of silicon) insulating layer, a semi-recessed LOCOS insulating layer, or a trench insulating layer. The first underlayer 12 can electrically separate the transistor 30 from the MEMS vibrator 20 and the capacitor 40.

  The second underlayer 14 is formed on the first underlayer 12. The second foundation layer 14 is, for example, a silicon nitride layer. The second underlayer 14 can function as an etching stopper layer in a release process described later.

  The MEMS vibrator 20 is formed on the second underlayer 14 (above the substrate 10). The MEMS vibrator 20 is accommodated (arranged) in the cavity 2 in the illustrated example. The MEMS vibrator 20 is, for example, a cantilever type vibrator. In the illustrated example, the MEMS vibrator 20 has a gap between the first structure (hereinafter also referred to as “lower structure”) 22 formed on the second underlayer 14 and the lower structure 22. And a second structure (hereinafter also referred to as “upper structure”) 24 formed to be vibrated by an electrostatic force between the lower structure 22 and the lower structure 22.

  The lower structure 22 is a flat member. The planar shape (the shape seen from the thickness direction of the substrate 10) of the lower structure 22 is, for example, a rectangle. The planar shape of the lower structure 22 is not limited to a rectangle, and may be a polygon other than a rectangle. The lower structure 22 is formed using the first silicon layer 4. The lower structure 22, the lower electrode 42 of the capacitor 40, and the conductive layer 62 are formed using the first silicon layer 4. The material of the lower structure 22 (first silicon layer 4) is, for example, polycrystalline silicon provided with conductivity by doping a predetermined impurity (for example, boron).

  The upper structure 24 is formed at a predetermined interval with respect to the lower structure 22. The upper structure 24 includes a support portion 24a formed on the second underlayer 14, and a beam portion 24b extending from the support portion 24a and disposed so as to face the lower structure 22. The planar shape of the beam part 24b is not specifically limited, For example, it is a rectangle. The planar shape of the beam portion 24b is not limited to a rectangle, and may be a polygon other than a rectangle. The upper structure 24 is formed using the second silicon layer 8. The upper structure 24, the gate electrode 34 of the transistor 30, and the upper electrode 44 of the capacitor 40 are formed using the second silicon layer 8. The material of the upper structure 24 (second silicon layer 8) is, for example, polycrystalline silicon imparted with conductivity by doping a predetermined impurity (for example, boron).

  In the MEMS vibrator 20, when a voltage (alternating voltage) is applied between the lower structure 22 and the upper structure 24, the beam portion 24 b causes the electrostatic force generated between the structures 22 and 24 to Vibrates in the thickness direction.

  Note that the MEMS vibrator 20 is not limited to the illustrated example, and may be, for example, a double-supported beam type vibrator in which both ends of the beam portion are fixed. Further, in the MEMS vibrator 20, the upper structure has a support portion, and a first beam portion and a second beam portion that extend in opposite directions from the support portion, and the first beam portion and the second beam. A vibrator in which a lower structure is formed opposite to each of the parts may be used. If the MEMS vibrator 20 is formed so as to be able to vibrate by an electrostatic force between the upper structure 24 and the lower structure 22 with a gap between the upper structure 24 and the lower structure 22, the structure Is not particularly limited.

  The cavity 2 is a space for accommodating the MEMS vibrator 20. The cavity 2 is formed on the second underlayer 14 (above the substrate 10), and the MEMS vibrator 20 is disposed therein. In the illustrated example, the cavity 2 is defined (defined) by the second underlayer 14, the surrounding wall 60, and the covering layers 70 and 72. The inside of the cavity 2 is in a reduced pressure state, for example. Thereby, the operation accuracy of the MEMS vibrator 20 can be improved. Although not shown, the cavity 2 may be further defined by the interlayer insulating layer 50.

  The circuit unit 3 includes an operation circuit of the electronic device 100. For example, the circuit unit 3 includes an oscillator operation circuit. The circuit unit 3 may include a temperature sensor for temperature compensation, an analog / digital conversion circuit, a logic circuit, a clock circuit, a power supply control circuit, and the like. The circuit unit 3 includes a transistor 30 and a capacitor 40. The circuit unit 3 can further include wiring layers 80, 82, 84, 86.

  The transistor 30 is formed on the substrate 10. In the illustrated example, the transistor 30 is formed in a region of the substrate 10 where the first underlayer 12 is not formed. The transistor 30 is a MOS transistor having a gate insulating film 32, a gate electrode 34, a source region 36, a drain region 37, and a sidewall 38.

  The gate insulating film 32 is formed on the substrate 10. The gate insulating film 32 is made of, for example, a silicon oxide layer. A part of the gate insulating film 32 is sandwiched between the substrate 10 and the gate electrode 34. The gate electrode 34 is formed on the gate insulating film 32. The gate electrode 34 is formed using the second silicon layer 8. The material of the gate electrode 34 is, for example, polycrystalline silicon imparted with conductivity by doping a predetermined impurity. The source region 36 and the drain region 37 are formed in the substrate 10. The source region 36 and the drain region 37 are formed by doping the substrate 10 with a predetermined impurity. The sidewall 38 is formed on the side of the gate electrode 34. The material of the sidewall 38 is, for example, silicon oxide.

  The capacitor 40 is formed on the first foundation layer 12. The capacitor 40 includes a first electrode (hereinafter also referred to as “lower electrode”) 42, a second electrode (hereinafter also referred to as “upper electrode”) 44, a dielectric layer 46 between the lower electrode 42 and the upper electrode 44, 48. The capacitor 40 is, for example, a PIP (PolySilicon-Insulator-Polysilicon) capacitor.

The lower electrode 42 is formed on the first foundation layer 12. The lower electrode 42 is formed using the first silicon layer 4. The dielectric layers 46 and 48 are formed on the lower electrode 42. The first dielectric layer 46 is, for example, a silicon oxide layer, and the second dielectric layer 48 is, for example, a silicon nitride layer. Although the case where the dielectric layers 46 and 48 are two layers has been described here, the total number of dielectric layers is not particularly limited, and may be a single layer or three or more layers. Good. The capacitor 40 may be an ONO capacitor in which a silicon nitride layer is sandwiched between silicon oxide layers as a dielectric layer. The upper electrode 44 is formed on the second dielectric layer 48. The upper electrode 44 is formed to face the lower electrode 42 with the dielectric layers 46 and 48 interposed therebetween. The upper electrode 44 is formed using the second silicon layer 8. The planar shape of the electrodes 42 and 44 is, for example, a rectangle. The material of the electrodes 42 and 44 is, for example, polycrystalline silicon provided with conductivity by doping a predetermined impurity (for example, boron).

  The first wiring layer 80 is formed on the interlayer insulating layer 50. Further, the first wiring layer 80 is formed in a through hole 51 a provided in the interlayer insulating layer 50 and connected to the source region 36 or the drain region 37. The first wiring layer 80 is a wiring for connecting the source region 36 or the drain region 37 and the second wiring layer 82.

  The second wiring layer 82 is formed on the interlayer insulating layer 52. Further, the second wiring layer 82 is formed in a through hole 53 a provided in the interlayer insulating layer 52 and connected to the first wiring layer 80. The second wiring layer 82 is a wiring for connecting the first wiring layer 80 and other elements (for example, the MEMS vibrator 20 and the capacitor 40).

  The third wiring layer 84 is provided on the interlayer insulating layer 50. Further, the third wiring layer 84 is formed in a through hole 51 b provided in the interlayer insulating layer 50 and connected to the lower electrode 42 or the upper electrode 44. The third wiring layer 84 is a wiring for connecting the lower electrode 42 or the upper electrode 44 and the fourth wiring layer 86.

  The fourth wiring layer 86 is formed on the interlayer insulating layer 52. Further, the fourth wiring layer 86 is formed in a through hole 53 b provided in the interlayer insulating layer 52 and connected to the third wiring layer 84. The fourth wiring layer 86 is a wiring for connecting the third wiring layer 84 and other elements (for example, the MEMS vibrator 20 and the transistor 30).

  As the wiring layers 80, 82, 84, 86, for example, an aluminum layer, a titanium layer, or a laminate of an aluminum layer and a titanium layer is used. The circuit unit 3 may include elements other than the transistor 30 and the capacitor 40.

  The interlayer insulating layer 50 is formed on the first base layer 12, the second base layer 14, and the gate insulating film 32 (above the substrate 10). The interlayer insulating layer 52 is formed on the interlayer insulating layer 50. The interlayer insulating layers 50 and 52 are formed around the cavity 2. The interlayer insulating layers 50 and 52 are, for example, silicon oxide layers. In the illustrated example, the electronic device 100 includes two interlayer insulating layers 50 and 52, but the number thereof is not particularly limited.

  The surrounding wall 60 defines the cavity 2. Although not shown, the surrounding wall 60 has a shape surrounding the MEMS vibrator 20 in a plan view. The planar shape of the surrounding wall 60 is not particularly limited, and may be any shape such as a circular shape or a polygonal shape.

  The surrounding wall 60 includes a conductive layer 62, a first metal layer 64, and a second metal layer 66. In the illustrated example, the conductive layer 62, the first metal layer 64, and the second metal layer 66 are laminated in this order from the substrate 10 side. In the illustrated example, the surrounding wall 60 includes two metal layers 64 and 66, but the number is not particularly limited.

The conductive layer 62 is formed using, for example, the first silicon layer 4. The material of the conductive layer 62 is, for example, polycrystalline silicon imparted with conductivity by doping a predetermined impurity. The first metal layer 64 and the second metal layer 66 are, for example, an aluminum layer, a titanium layer, or a stacked body of an aluminum layer and a titanium layer.

  The first covering layer 70 is formed so as to cover the cavity 2 from above. The first covering layer 70 defines the upper surface of the cavity 2. A through hole 71 is provided in the first coating layer 70. In the illustrated example, three through holes 71 are provided, but the number is not limited. As will be described later, an etching solution or an etching gas can be supplied through the through hole 71 in the release process for forming the cavity 2.

  The second coating layer 72 is disposed on the first coating layer 70. The second coating layer 72 closes the through hole 71 formed in the first coating layer 70. Thereby, it is possible to prevent gas or the like from entering the cavity 2 from the outside through the through hole 71. The second coating layer 72 is, for example, an aluminum layer, a titanium layer, or a stacked body of an aluminum layer and a titanium layer. The first coating layer 70 and the second coating layer 72 can function as a sealing member that covers the cavity 2 from above and seals the cavity 2.

  It is desirable that a constant potential (for example, ground potential) is applied to the surrounding wall 60 and the first covering layer 70. Thereby, the surrounding wall 60 and the 1st coating layer 70 can be functioned as an electromagnetic shield. Therefore, the MEMS vibrator 20 can be electrically shielded from the outside.

  The passivation layer 90 is formed on the interlayer insulating layer 52, the second wiring layer 82, the fourth wiring layer 86, and the second metal layer 66. The passivation layer 90 is, for example, a silicon nitride layer.

  FIG. 2 is a circuit diagram showing the electronic device 100 according to the present embodiment.

  As shown in FIG. 2, the electronic device 100 includes, for example, a MEMS vibrator 20 and an inverting amplifier circuit 110. The inverting amplifier circuit 110 is provided, for example, in the circuit unit 3 shown in FIG.

  The MEMS vibrator 20 has a first terminal 20 a electrically connected to the lower structure 22 and a second terminal 20 b electrically connected to the upper structure 24. The first terminal 20a of the MEMS vibrator 20 is connected at least with the input terminal 110a of the inverting amplifier circuit 110 in an AC manner. The second terminal 20b of the MEMS vibrator 20 is connected to the output terminal 110b of the inverting amplifier circuit 110 at least in an AC manner.

  In the illustrated example, the inverting amplifier circuit 110 is configured by one inverter, but may be configured by combining a plurality of inverters (inverting circuits) and amplifier circuits so that a desired oscillation condition is satisfied. .

  The electronic device 100 may include a feedback resistor for the inverting amplifier circuit 110. In the example shown in FIG. 2, the input terminal and the output terminal of the inverting amplifier circuit 110 are connected via a resistor 120. The resistor 120 is provided in the circuit unit 3, for example.

The electronic device 100 includes a first capacitor 130 connected between an input terminal 110a of the inverting amplifier circuit 110 and a reference potential (ground potential), an output terminal 110b of the inverting amplifier circuit 110, and a reference potential (ground potential). And a second capacitor 132 connected therebetween. As a result, the MEMS vibrator 20 and the capacitors 130 and 132 can form an oscillation circuit that forms a resonance circuit. The electronic device 100 outputs the oscillation signal f obtained by this oscillation circuit. The capacitor 40 shown in FIG. 1 may be the first capacitor 130 or the second capacitor 132.

  Note that the electronic device 100 may further include a frequency dividing circuit (not shown). The frequency divider circuit may divide the output signal of the oscillation circuit and output the oscillation signal f. The frequency dividing circuit may be provided in the circuit unit 3.

  The electronic device 100 according to the present embodiment has the following features, for example.

  According to the electronic device 100, the lower structure 22 of the MEMS vibrator 20 and the lower electrode 42 of the capacitor 40 are formed using the first silicon layer 4. Thereby, the lower structure 22 and the lower electrode 42 can be formed in the same process. Furthermore, according to the electronic device 100, the upper structure 24 of the MEMS vibrator 20, the upper electrode 44 of the capacitor 40, and the gate electrode 34 of the transistor 30 are formed using the second silicon layer 8. Thereby, the upper structure 24, the upper electrode 44, and the gate electrode 34 can be formed in the same process. Therefore, the manufacturing process can be simplified. Therefore, for example, cost reduction can be achieved.

  The electronic device 100 includes the MEMS vibrator 20 and the circuit unit 3 that are formed above the substrate 10. Therefore, according to the electronic device 100, the circuit unit 3 including the MEMS vibrator 20 and the operation circuit of the oscillator can be formed into one chip.

1.2. Next, a method for manufacturing an electronic device according to the first embodiment will be described with reference to the drawings. 3-14 is sectional drawing which shows typically the manufacturing process of the electronic device 100 which concerns on this embodiment.

  As shown in FIG. 3, the first underlayer 12 is formed on the substrate 10. The first underlayer 12 is formed by, for example, a LOCOS method or an STI (shallow trench isolation) method. In this step, a silicon oxide layer 12 a having a thickness smaller than that of the first base layer 12 is formed in a region other than the region where the first base layer 12 is formed on the substrate 10.

  As shown in FIG. 4, the second underlayer 14 is formed on the first underlayer 12. The second underlayer 14 is formed by, for example, forming a film by a CVD (Chemical Vapor Deposition) method or a sputtering method and then patterning the film by a photolithography technique and an etching technique.

  As shown in FIG. 5, the lower structure 22, the lower electrode 42, and the conductive layer 62 are formed using the first silicon layer 4. Specifically, first, the first silicon layer 4 is formed above the substrate 10 by CVD, sputtering, or the like. The first silicon layer 4 is formed on the substrate 10 and the underlying layers 12 and 14. Next, the first silicon layer 4 is doped with predetermined impurities to impart conductivity. Next, the first silicon layer 4 is patterned by a photolithography technique and an etching technique. Through the above steps, the lower structure 22, the lower electrode 42, and the conductive layer 62 are formed. Thus, in this step, the lower structure 22, the lower electrode 42, and the conductive layer 62 are simultaneously formed using the first silicon layer 4. The first silicon layer 4 is, for example, a polycrystalline silicon layer or an amorphous silicon layer.

As shown in FIG. 6, a first oxide film 5 that covers the lower structure 22, the lower electrode 42, and the conductive layer 62 is formed. The first oxide film 5 is formed, for example, by oxidizing (thermal oxidation) the surfaces of the lower structure 22, the lower electrode 42, and the conductive layer 62. The thermal oxidation treatment of the lower structure 22, the lower electrode 42, and the conductive layer 62 is performed at, for example, 800 ° C. or higher and 1100 ° C. or lower. In this step, the first oxide film 5 covering the lower structure 22, the first oxide film 5 covering the lower electrode 42, and the first oxide film 5 covering the conductive layer 62 are formed simultaneously. The first oxide film 5 is, for example, a silicon oxide layer. The first oxide film 5 covering the lower electrode 42 becomes the first dielectric layer 46. Note that the first oxide film 5 may be formed using a CVD method or a sputtering method.

  As shown in FIG. 7, a second dielectric layer 48 that covers the lower electrode 42 covered with the first oxide film 5 is formed. The second dielectric layer 48 is formed, for example, by being deposited by a CVD method or the like and then patterned by a photolithography technique and an etching technique. The exposed surface of the second underlayer 14 is etched by etching when the second dielectric layer 48 is formed. That is, a part of the region where the lower structure 22 and the conductive layer 62 are not formed in the second foundation layer 14 is etched, and a recess is formed on the surface of the second foundation layer 14. The second dielectric layer 48 is, for example, a silicon nitride layer. When the number of dielectric layers is three or more, the film formation and patterning are repeated in the same process as the process of forming the second dielectric layer 48.

  As shown in FIG. 8, the silicon oxide layer 12a is removed. The removal of the silicon oxide layer 12a is performed by a known etching technique. At this time, the first oxide film 5 covering the lower structure 22 and the conductive layer 62 is not removed.

  As shown in FIG. 9, the region where the substrate 10 is exposed (the region where the first underlayer 12 is not formed), the lower structure 22 covered with the first oxide film 5, and the first oxide film 5. A second oxide film 6 covering the conductive layer 62 is formed. The second oxide film 6 is formed, for example, by oxidizing (thermal oxidation) the surfaces of the substrate 10, the lower structure 22, and the conductive layer 62. The second oxide film 6 on the exposed region of the substrate 10 becomes the gate insulating film 32. In this step, the gate oxide film 32, the second oxide film 6 covering the lower structure 22 covered with the first oxide film 5, and the second oxide film 6 covering the conductive layer 62 covered with the first oxide film 5. Are formed simultaneously. In this step, a sacrificial layer 7 composed of the first oxide film 5 and the second oxide film 6 covering the lower structure 22 is formed.

  As shown in FIG. 10, the upper structure 24, the upper electrode 44, and the gate electrode 34 are formed using the second silicon layer 8.

  Specifically, first, the second silicon layer 8 is formed above the substrate 10 by CVD or sputtering. The second silicon layer 8 is formed on the gate insulating film 32, the second underlayer 14, the second oxide film 6, and the second dielectric layer 48. Next, the second silicon layer 8 is doped with a predetermined impurity to impart conductivity. Next, the second silicon layer 8 is patterned by a photolithography technique and an etching technique. Through the above steps, the upper structure 24, the upper electrode 44, and the gate electrode 34 are formed. Thus, in this step, the upper structure 24, the upper electrode 44, and the gate electrode 34 are simultaneously formed using the second silicon layer 8. In this step, the upper structure 24 is formed on the second oxide film 6 that covers the lower structure 22. That is, the upper structure 24 is formed above the lower structure 22 via the oxide films 5 and 6. In this step, the gate electrode 34 is formed on the gate insulating film 32. The second silicon layer 8 is, for example, a polycrystalline silicon layer or an amorphous silicon layer. In this step, the MEMS vibrator 20 and the capacitor 40 are formed.

As shown in FIG. 11, a source region 36, a drain region 37, and a sidewall 38 are formed. In this step, first, a predetermined impurity is implanted into a region of the substrate 10 where the first underlayer 12 is not formed to form an impurity region. Next, a sidewall 38 is formed on the side of the gate electrode 34 by a known method. Next, using the sidewall 38 as a mask, a predetermined impurity is further implanted into the substrate 10 to form a source region 36 and a drain region 37. Thereby, an LDD (Lightly Doped Drain) structure can be formed. In this step, the transistor 30 is formed.

  As shown in FIG. 12, an interlayer insulating layer 50 is formed above the substrate 10 so as to cover the MEMS vibrator 20, the transistor 30, the capacitor 40, and the conductive layer 62. The interlayer insulating layer 50 is formed by, for example, a CVD method or a coating (spin coating) method. After forming the interlayer insulating layer 50, a process for planarizing the surface of the interlayer insulating layer 50 may be performed.

  Next, the interlayer insulating layer 50 is patterned to form through holes 51a, 51b, 51c. The patterning is performed by, for example, a photolithography technique and an etching technique. The through hole 51 a is formed so as to expose the source region 36 or the drain region 37. The through hole 51 b is formed so as to expose the lower electrode 42 or the upper electrode 44. The through hole 51 c is formed so as to expose the conductive layer 62. The through hole 51c is formed so as to surround the MEMS vibrator 20 in a plan view.

  Next, the first wiring layer 80, the third wiring layer 84, and the first metal layer 64 are formed. The first wiring layer 80 is formed on the interlayer insulating layer 50 and in the through hole 51a. The third wiring layer 84 is formed on the interlayer insulating layer 50 and in the through hole 51b. The first metal layer 64 is formed on the interlayer insulating layer 50 and in the through hole 51c. The first wiring layer 80, the third wiring layer 84, and the first metal layer 64 are formed by being formed by a CVD method, a sputtering method, or the like and then patterned by a photolithography technique and an etching technique. In this step, the first wiring layer 80, the third wiring layer 84, and the first metal layer 64 can be formed in the same step.

  As shown in FIG. 13, an interlayer insulating layer 52 is formed on the interlayer insulating layer 50 so as to cover the first wiring layer 80, the third wiring layer 84, and the first metal layer 64. The interlayer insulating layer 52 is formed by, for example, a CVD method or a coating (spin coating) method. After the interlayer insulating layer 52 is formed, a process for planarizing the surface of the interlayer insulating layer 52 may be performed.

  Next, the interlayer insulating layer 52 is patterned to form through holes 53a, 53b, and 53c. The patterning is performed by, for example, a photolithography technique and an etching technique. The through hole 53 a is formed so as to expose the first wiring layer 80. The through hole 53 b is formed so as to expose the third wiring layer 84. The through hole 53 c is formed so as to expose the first metal layer 64. The through hole 53c is formed so as to surround the MEMS vibrator 20 in a plan view.

  Next, the second wiring layer 82, the fourth wiring layer 86, the second metal layer 66, and the first covering layer 70 are formed. The second wiring layer 82 is formed on the interlayer insulating layer 52 and in the through hole 53a. The fourth wiring layer 86 is formed on the interlayer insulating layer 52 and in the through hole 53b. The second metal layer 66 is formed on the interlayer insulating layer 52 and in the through hole 53c. The first covering layer 70 is formed on the interlayer insulating layer 52. The second wiring layer 82, the fourth wiring layer 86, the second metal layer 66, and the first covering layer 70 are formed by a CVD method or a sputtering method, and then patterned by a photolithography technique and an etching technique. It is formed by. In this step, the second wiring layer 82, the fourth wiring layer 86, the second metal layer 66, and the first covering layer 70 can be formed in the same step. In this step, the surrounding wall 60 is formed.

  Next, the 1st coating layer 70 is patterned and the through-hole 71 is formed. The through hole 71 may be formed at the same time as the step of forming the first coating layer 70. Thereby, simplification of a manufacturing process can be achieved.

  As shown in FIG. 14, a passivation layer 90 is formed on the first covering layer 70 and the interlayer insulating layer 52. The passivation layer 90 is formed by, for example, forming a film by a CVD method or a sputtering method, and then patterning the film by a photolithography technique and an etching technique.

  Next, the sacrificial layer 7 composed of the interlayer insulating layers 50 and 52 and the oxide films 5 and 6 above the MEMS vibrator 20 is removed by passing an etching solution or etching gas through the through-hole 71 to form the cavity 2 (release). Process). The release process is performed, for example, by wet etching using hydrofluoric acid or buffered hydrofluoric acid (mixed liquid of hydrofluoric acid and ammonium fluoride), dry etching using a hydrogen fluoride-based gas, or the like. . By forming the surrounding wall 60 and the first covering layer 70 from a material that is not etched in the release process, the cavity 2 can be prevented from spreading to the outside of the surrounding wall 60. The second underlayer 14 can function as an etching stopper layer. In the release process, the sacrificial layer 7 made of the oxide films 5 and 6 is removed, whereby a gap (gap) is formed between the lower structure 22 and the upper structure 24 of the MEMS vibrator 20. That is, the oxide films 5 and 6 constitute a sacrificial layer for forming a gap between the lower structure 22 and the upper structure 24.

  As shown in FIG. 1, a second coating layer 72 that closes the through hole 71 is formed on the first coating layer 70 and the passivation layer 90. The second coating layer 72 is formed by, for example, forming a film by a vapor phase growth method such as a CVD method or a sputtering method, and then patterning the film by a photolithography technique and an etching technique. Thereby, the cavity 2 can be sealed in a reduced pressure state.

  Through the above steps, the electronic device 100 can be manufactured.

  The manufacturing method of the electronic device 100 according to the present embodiment has the following characteristics.

  The manufacturing method of the electronic device 100 according to the present embodiment includes a step of forming the lower structure 22 constituting the MEMS vibrator 20 and the lower electrode 42 of the capacitor 40 using the first silicon layer 4, and MEMS vibration. Forming the upper structure 24 constituting the child 20, the gate electrode 34 of the transistor 30, and the upper electrode 44 of the capacitor 40 using the second silicon layer 8. Thus, by forming the lower structure 22 and the lower electrode 42 using the first silicon layer 4, the lower structure 22 and the lower electrode 42 can be formed in the same process. Further, by forming the upper structure 24, the gate electrode 34, and the upper electrode 44 using the second silicon layer 8, the upper structure 24, the gate electrode 34, and the upper electrode 44 can be formed in the same process. it can. Therefore, according to the method for manufacturing the electronic device 100 according to the present embodiment, the manufacturing process can be simplified. Therefore, for example, cost reduction can be achieved.

The method for manufacturing the electronic device 100 according to the present embodiment includes the step of forming the first oxide film 5 that covers the lower structure 22 of the MEMS vibrator 20 and the lower electrode 42 of the capacitor 40, and the first oxide film 5 covers the method. A step of forming the second oxide film 6 covering the lower structure 22 and the gate insulating film 32 constituting the transistor 30 by thermal oxidation. The upper structure 24, the upper electrode 44, the gate electrode 34, Is formed using the second silicon layer 8, the upper structure 24 is formed on the second oxide film 6, and the gate electrode 34 is formed on the gate insulating film 32. As described above, in the present embodiment, the layer constituting the sacrificial layer 7 for forming a gap (gap) between the lower structure 22 and the upper structure 24 of the MEMS vibrator 20, and the first of the capacitor 40. The layers constituting the dielectric layer 46 can be formed in the same process. Furthermore, the layer constituting the sacrificial layer 7 and the gate insulating film 32 can be formed in the same process. Therefore, the manufacturing process can be simplified. In addition, the size of the gap between the lower structure 22 and the upper structure 24 can be controlled by the thicknesses of the first oxide film 5 and the second oxide film 6.

  In the method for manufacturing the electronic device 100 according to the present embodiment, the electronic device 100 including the MEMS vibrator 20 and the circuit unit 3 formed above the substrate 10 can be obtained. Therefore, it is possible to obtain the electronic device 100 in which the circuit unit 3 including the MEMS vibrator 20 and the operation circuit of the oscillator can be integrated into one chip.

1.3. Modification of Method for Manufacturing Electronic Device Next, a modification of the method for manufacturing the electronic device 100 according to the first embodiment will be described with reference to the drawings. 15 to 17 are cross-sectional views schematically showing manufacturing steps of the electronic device 100 according to the modification of the first embodiment. Hereinafter, in the method for manufacturing the electronic device according to the present modification, differences from the example of the method for manufacturing the electronic device according to the first embodiment described above will be described, and description of similar points will be omitted.

  In the method of manufacturing the electronic device 100 according to the present modification, steps until the second dielectric layer 48 covering the lower electrode 42 covered with the first oxide film 5 shown in FIG. 7 is formed (FIGS. 3 to 7). The process shown) is the same as the manufacturing process of the electronic device 100 according to the first embodiment described above. Therefore, the description is omitted.

  As shown in FIG. 15, the first oxide film 5 covering the silicon oxide layer 12a and the lower structure 22 is removed. The first oxide film 5 covering the silicon oxide layer 12a and the lower structure 22 is removed by a known etching technique. In the illustrated example, the first oxide film 5 covering the conductive layer 62 is not removed, but in this step, the first oxide film 5 covering the conductive layer 62 may be removed.

  As shown in FIG. 16, the substrate 10 is covered with the exposed region (the region where the first underlayer 12 is not formed), the lower structure 22 from which the first oxide film 5 is removed, and the first oxide film 5. A second oxide film 6 covering the conductive layer 62 is formed. The second oxide film 6 on the region where the substrate 10 is exposed becomes the gate insulating film 32. The second oxide film 6 is formed by thermal oxidation, for example. In this step, a sacrificial layer 7 made of the second oxide film 6 covering the lower structure 22 is formed.

  As shown in FIG. 17, the upper structure 24, the upper electrode 44, and the gate electrode 34 are formed using the second silicon layer 8.

  Specifically, first, the second silicon layer 8 is formed above the substrate 10 by CVD or sputtering. The second silicon layer 8 is formed on the gate insulating film 32, the second underlayer 14, the first oxide film 5, the second oxide film 6, and the second dielectric layer 48. Next, the second silicon layer 8 is doped with a predetermined impurity to impart conductivity. Next, the second silicon layer 8 is patterned by a photolithography technique and an etching technique. Through the above steps, the upper structure 24, the upper electrode 44, and the gate electrode 34 are formed. Thus, in this step, the upper structure 24, the upper electrode 44, and the gate electrode 34 are simultaneously formed using the second silicon layer 8. In this step, the upper structure 24 is formed on the second oxide film 6 that covers the lower structure 22. That is, the upper structure 24 is formed on the lower structure 22 via the second oxide film 6. In this step, the MEMS vibrator 20 and the capacitor 40 are formed.

  The subsequent steps are the same as those in the method for manufacturing the electronic device 100 according to the first embodiment described above (see FIGS. 11 to 14). Therefore, the description is omitted.

  Through the above steps, the electronic device 100 can be manufactured.

  According to the method for manufacturing the electronic device 100 according to this modification, the step of forming the first oxide film 5 that covers the lower structure 22 of the MEMS vibrator 20 and the lower electrode 42 of the capacitor 40, and the lower structure 22 are covered. The step of removing the first oxide film 5, the second oxide film 6 covering the lower structure 22 from which the first oxide film 5 has been removed, and the gate insulating film 32 constituting the transistor 30 are formed by thermal oxidation. A step of forming the upper structure 24, the upper electrode 44, and the gate electrode 34 using the second silicon layer 8, and forming the upper structure 24 on the second oxide film 6 to provide gate insulation. A gate electrode 34 is formed on the film 32. Thus, in this modification, the sacrificial layer 7 and the gate insulating film 32 for forming a gap (gap) between the lower structure 22 and the upper structure 24 of the MEMS vibrator 20 are formed in the same process. Can be formed. Therefore, the manufacturing process can be simplified. Further, the size of the gap between the lower structure 22 and the upper structure 24 can be controlled by the thickness of the second oxide film 6.

2. Second Embodiment 2.1. Electronic Device Next, an electronic device according to a second embodiment will be described with reference to the drawings. FIG. 18 is a cross-sectional view schematically showing the electronic device 100 according to the second embodiment.

  In the electronic device 100 described above, as shown in FIG. 1, the lower structure 22 of the MEMS vibrator 20 and the lower electrode 42 of the capacitor 40 are formed using the first silicon layer 4. Further, the upper structure 24 of the MEMS vibrator 20, the gate electrode 34 of the transistor 30, and the upper electrode 44 of the capacitor 40 are formed using the second silicon layer 8.

  On the other hand, in the electronic device 200, as shown in FIG. 18, the lower structure 22 of the MEMS vibrator 20, the gate electrode 34 of the transistor 30, and the lower electrode 42 of the capacitor 40 use the first silicon layer 4. Is formed. Further, the upper structure 24 of the MEMS vibrator 20 and the upper electrode 44 of the capacitor 40 are formed using the second silicon layer 8.

  According to the electronic device 200, the lower structure 22 of the MEMS vibrator 20, the gate electrode 34 of the transistor 30, and the lower electrode 42 of the capacitor 40 are formed using the first silicon layer 4. Thereby, the lower structure 22, the gate electrode 34, and the lower electrode 42 can be formed in the same process. Furthermore, according to the electronic device 200, the upper structure 24 of the MEMS vibrator 20 and the upper electrode 44 of the capacitor 40 are formed using the second silicon layer 8. Thereby, the upper structure 24 and the upper electrode 44 can be formed in the same process. Therefore, the manufacturing process can be simplified. Therefore, for example, cost reduction can be achieved.

2.2. Method for Manufacturing Electronic Device Next, a method for manufacturing an electronic device according to the second embodiment will be described with reference to the drawings. 19 to 26 are cross-sectional views schematically showing the manufacturing process of the electronic device 100 according to the second embodiment. Hereinafter, in the method for manufacturing the electronic device 200 according to the second embodiment, differences from the above-described example of the method for manufacturing the electronic device 100 according to the first embodiment will be described, and description of similar points will be omitted. Hereinafter, in the method for manufacturing the electronic device 200 according to the second embodiment, differences from the above-described example of the method for manufacturing the electronic device 100 according to the first embodiment will be described, and description of similar points will be omitted.

In the manufacturing method of the electronic device 200 according to the second embodiment, the steps (steps shown in FIGS. 3 and 4) until the step of forming the second underlayer 14 shown in FIG. 4 are the same as those in the first embodiment described above. This is the same as the manufacturing process of the electronic device 100. Therefore, the description is omitted.

  As shown in FIG. 19, the silicon oxide layer 12a is removed. The removal of the silicon oxide layer 12a is performed by a known etching technique.

  As shown in FIG. 20, the gate insulating film 32 is formed by oxidizing the surface of the substrate 10.

  As shown in FIG. 21, the lower structure 22, the gate electrode 34, the lower electrode 42, and the conductive layer 62 are formed using the first silicon layer 4. Specifically, first, the first silicon layer 4 is formed above the substrate 10 by CVD, sputtering, or the like. The first silicon layer 4 is formed on the gate insulating film 32 and the underlying layers 12 and 14. Next, the first silicon layer 4 is doped with predetermined impurities to impart conductivity. Next, the first silicon layer 4 is patterned by a photolithography technique and an etching technique. Through the above steps, the lower structure 22, the gate electrode 34, the lower electrode 42, and the conductive layer 62 are formed. Thus, in this process, the lower structure 22, the gate electrode 34, the lower electrode 42, and the conductive layer 62 are simultaneously formed using the first silicon layer 4. The first silicon layer 4 is, for example, a polycrystalline silicon layer or an amorphous silicon layer.

  As shown in FIG. 22, a source region 36, a drain region 37, and a sidewall 38 are formed. In this step, the transistor 30 is formed.

  As shown in FIG. 23, a protective layer 30a covering the transistor 30 is formed. The material of the protective layer 30a is, for example, silicon oxide. The material of the protective layer 30a may be silicon nitride. The protective layer 30a is formed by being patterned by a CVD method or the like and then patterned by a photolithography technique and an etching technique.

  As shown in FIG. 24, the first oxide film 5 that covers the lower structure 22, the lower electrode 42, and the conductive layer 62 is formed. The first oxide film 5 is formed, for example, by oxidizing (thermal oxidation) the surfaces of the lower structure 22, the lower electrode 42, and the conductive layer 62. The first oxide film 5 covering the lower electrode 42 becomes the first dielectric layer 46. In this step, a sacrificial layer 7 made of the first oxide film 5 covering the lower structure 22 is formed. Note that the first oxide film 5 may be formed using a CVD method or a sputtering method.

  As shown in FIG. 25, the 2nd dielectric material layer 48 which covers the lower electrode 42 covered with the 1st oxide film 5 is formed. The second dielectric layer 48 is formed, for example, by being deposited by a CVD method or the like and then patterned by a photolithography technique and an etching technique. The exposed surface of the second underlayer 14 is etched by etching when the second dielectric layer 48 is formed. The second dielectric layer 48 is, for example, a silicon nitride layer.

  As shown in FIG. 26, the upper structure 24 and the upper electrode 44 are formed using the second silicon layer 8.

Specifically, first, the second silicon layer 8 is formed above the substrate 10 by CVD or sputtering. The second silicon layer 8 is formed on the second underlayer 14, the first oxide film 5, and the second dielectric layer 48. Next, the second silicon layer 8 is doped with a predetermined impurity to impart conductivity. Next, the second silicon layer 8 is patterned by a photolithography technique and an etching technique. Through the above steps, the upper structure 24 and the upper electrode 44 are formed. Thus, in this step, the upper structure 24 and the upper electrode 44 are simultaneously formed using the second silicon layer 8. The upper structure 24 is formed on the lower structure 22 via the first oxide film 5. In this step, the MEMS vibrator 20 and the capacitor 40 are formed. Note that the protective layer 30a may be removed after this step. Further, the protective layer 30a may be used as a part of the interlayer insulating layer 50 without removing the protective layer 30a.

  The subsequent steps are the same as those in the method for manufacturing the electronic device 100 according to the first embodiment described above. Therefore, the description is omitted.

  Through the above steps, the electronic device 200 can be manufactured.

  In the method for manufacturing the electronic device 200 according to the present embodiment, the lower structure 22 constituting the MEMS vibrator 20, the gate electrode 34 of the transistor 30, and the lower electrode 42 of the capacitor 40 are used using the first silicon layer 4. And a step of forming the upper structure 24 constituting the MEMS vibrator 20 and the upper electrode 44 of the capacitor 40 constituting the circuit unit 3 using the second silicon layer 8. In this manner, the lower structure 22, the gate electrode 34, and the lower electrode 42 are formed using the first silicon layer 4, so that the lower structure 22, the gate electrode 34, and the lower electrode 42 are formed in the same process. can do. Furthermore, by forming the upper structure 24 and the upper electrode 44 using the second silicon layer 8, the upper structure 24 and the upper electrode 44 can be formed in the same process. Therefore, according to the method for manufacturing the electronic device 200 according to the present embodiment, the manufacturing process can be simplified. Therefore, for example, cost reduction can be achieved.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

DESCRIPTION OF SYMBOLS 2 ... Cavity part, 3 ... Circuit part, 4 ... 1st silicon layer, 5 ... 1st oxide film, 6 ... 2nd oxide film, 7 ... Sacrificial layer, 8 ... 2nd silicon layer, 10 ... Substrate, 12 ... 1st DESCRIPTION OF SYMBOLS 1 base layer, 14 ... 2nd base layer, 20 ... MEMS vibrator, 20a ... 1st terminal, 20b ... 2nd terminal, 22 ... 1st structure (lower structure), 24 ... 2nd structure (upper structure) Body), 24a ... support portion, 24b ... beam portion, 30 ... transistor, 32 ... gate insulating film, 34 ... gate electrode, 36 ... source region, 37 ... drain region, 38 ... side wall, 40 ... capacitor, 42th 1 electrode (lower electrode), 44 ... second electrode (upper electrode), 46 ... first dielectric layer, 48 ... second dielectric layer, 50 ... interlayer insulating layer, 51a, 51b, 51c ... through hole, 52 ... Interlayer insulating layer, 53a, 53b, 53c ... through hole, 60 ... enclosure wall, 62 ... lead 64, first metal layer, 66, second metal layer, 70, first coating layer, 71, through hole, 72, second coating layer, 80, first wiring layer, 82, second wiring layer, 84. ... third wiring layer, 86 ... fourth wiring layer, 90 ... passivation layer, 100 ... electronic device, 110 ... inverting amplifier circuit, 110a ... input terminal, 110b ... output terminal, 120 ... resistor, 130 ... first capacitor, 132 ... Second capacitor, 200 ... Electronic device

Claims (2)

A method of manufacturing an electronic device having a MEMS vibrator and a circuit unit formed above a substrate,
Forming a first structure constituting the MEMS vibrator and a first electrode of a capacitor constituting the circuit unit using a first silicon layer;
Forming a sacrificial layer covering the first structure;
Forming a second structure constituting the MEMS vibrator, a second electrode of the capacitor constituting the circuit unit, and a gate electrode of a transistor constituting the circuit unit using a second silicon layer; When,
Removing the sacrificial layer to form a gap between the first structure and the second structure;
Forming the second structure, the second electrode, and the gate electrode using the second silicon layer
Forming a first oxide film covering the first structure and the first electrode before the step of performing
,
A second oxide film covering the first structure covered with the first oxide film, and the transistor
Forming a gate insulating film to be formed by thermal oxidation;
Including
The sacrificial layer is formed of the first oxide film and the second oxide film,
Forming the second structure, the second electrode, and the gate electrode using the second silicon layer
Forming the second structure over the second oxide film, and forming the gate insulating film
Forming the gate electrode above
A method for manufacturing an electronic device. A method of manufacturing an electronic device having a MEMS vibrator and a circuit unit formed above a substrate,
Forming a first structure constituting the MEMS vibrator and a first electrode of a capacitor constituting the circuit unit using a first silicon layer;
Forming a sacrificial layer covering the first structure;
Forming a second structure constituting the MEMS vibrator, a second electrode of the capacitor constituting the circuit unit, and a gate electrode of a transistor constituting the circuit unit using a second silicon layer; When,
Removing the sacrificial layer to form a gap between the first structure and the second structure;
Forming the second structure, the second electrode, and the gate electrode using the second silicon layer
Forming a first oxide film covering the first structure and the first electrode before the step of performing
,
Removing the first oxide film covering the first structure;
A second oxide film covering the first structure from which the first oxide film has been removed; and the transistor
A step of forming a gate insulating film that constitutes by thermal oxidation;
Including
The sacrificial layer is formed of the second oxide film,
Forming the second structure, the second electrode, and the gate electrode using the second silicon layer
Forming the second structure over the second oxide film, and forming the gate insulating film
A method of manufacturing an electronic device , wherein the gate electrode is formed above the substrate .

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