JP2011177824A - Method of manufacturing electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an electronic device including a functional element having excellent characteristics. <P>SOLUTION: The method of manufacturing the electronic device includes: a step of forming the functional element 20 above a substrate 10; a step of forming the interlayer insulating layers 30a, 30b, 30c covering the functional element 20; a step of forming a first coating layer 40 above the functional element 20 and the interlayer insulating layers 30a, 30b, 30c; a step of forming a through-hole 42 in the first coating layer 40; a step of forming a resin layer 50 above the interlayer insulating layers 30a, 30b, 30c and above the first coating layer 40; a step of forming an opening part 52 communicating with the through-hole 42 in the resin layer 50 above the through-hole 42; a step of forming a cavity part 32 by removing the interlayer insulating layers 30a, 30b, 30c above the functional element 20 through the through-hole 42; a step of closing the through-hole 42 by forming a second covering layer 60 above the through-hole 42. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an electronic device manufacturing method.

  In general, an electronic device is known in which functional elements such as MSMS (Micro Electro Mechanical Systems) are arranged in a cavity formed on a substrate. MEMS such as micro vibrators, micro sensors, and micro actuators need to be placed in a state in which a minute structure can be vibrated, deformed, or otherwise operated, and thus are housed in an operable state in a cavity. The For example, the inside of the cavity is in a reduced pressure state in order to prevent deterioration of the characteristics of the functional element.

  As a method for forming the above-described cavity, Patent Document 1 discloses that a MEMS structure is formed on a substrate, a sacrificial layer is formed thereon, and then a first sealing member having a through hole is formed. A method is described in which the sacrificial layer is removed through the through hole of the first sealing member, the movable part of the MEMS structure is released, and finally the through hole of the first sealing member is covered with the second sealing member to close it. Has been.

  By the way, WCSP (Wafer Level Chip Size Package) that can be reduced in size and cost is attracting attention as a package of a semiconductor device. As an example of WCSP, for example, Patent Document 2 describes a structure in which an external electrode is formed above a resin layer formed on a substrate having an integrated circuit. Patent Document 2 describes that a polyimide resin, a silicone-modified polyimide resin, an epoxy resin, or the like is used as the resin layer. In the process of forming these resin layers, generally, heat treatment is performed at a temperature of 300 ° C. or higher to cure the resin.

JP-A-2005-123561 JP 2007-142481 A

  For example, when this WCSP technology is applied to an electronic device in which a functional element such as MSMS is arranged in a cavity formed on a substrate, gas is generated in the cavity by the heat treatment in the process of forming a resin layer. As a result, the pressure may increase and the characteristics of the functional element may be deteriorated.

  One of the objects according to some embodiments of the present invention is to provide a manufacturing method capable of manufacturing an electronic device having a functional element with good characteristics.

According to the method for manufacturing an electronic device according to the present invention,
Forming a functional element above the substrate;
Forming an interlayer insulating layer covering the functional element;
Forming a first covering layer above the functional element and above the interlayer insulating layer;
Forming a through hole in the first coating layer;
Forming a resin layer above the interlayer insulating layer and above the first covering layer;
Forming an opening communicating with the through hole in the resin layer above the through hole;
Removing the interlayer insulating layer above the functional element through the through hole to form a cavity;
Forming a second coating layer above the through hole and closing the through hole;
including.

  According to such a method for manufacturing an electronic device, the step of forming the cavity can be performed after the step of forming the resin layer. Therefore, even if the heat treatment is performed in the step of forming the resin layer, the cavity is not formed, so that there is no problem that the pressure is increased due to the generation of gas in the cavity. Therefore, according to such a method for manufacturing an electronic device, an electronic device having a functional element with good characteristics can be manufactured.

  In the description according to the present invention, the word “upper” is used, for example, “specifically” (hereinafter referred to as “A”) is formed above another specific thing (hereinafter referred to as “B”). The word “above” is used to include the case where B is formed directly on A and the case where B is formed on A via another object. Used.

In the method for manufacturing an electronic device according to the present invention,
Forming a wiring layer formed above the resin layer and electrically connected to the functional element;
Forming an external terminal formed above the wiring layer and electrically connected to the wiring layer;
Can further be included.

  According to such an electronic device manufacturing method, the step of forming the external terminal can be performed in the wafer process. Therefore, a low-cost and high-quality electronic device can be manufactured.

In the method for manufacturing an electronic device according to the present invention,
In the step of forming the wiring layer, a metal layer can be formed above the second coating layer.

  According to such an electronic device manufacturing method, it is possible to reduce damage to the second coating layer in the step of forming the wiring layer.

In the method for manufacturing an electronic device according to the present invention,
In the step of forming the opening, the opening can be formed so as to expose at least a part of the upper surface of the first covering layer.

  According to such a method for manufacturing an electronic device, the influence of the film stress of the resin layer on the first coating layer and the second coating layer can be reduced.

In the method for manufacturing an electronic device according to the present invention,
The step of forming the first covering layer and the step of forming the through hole can be performed in the same step.

  According to such a method for manufacturing an electronic device, the manufacturing process can be simplified.

FIG. 6 is a cross-sectional view schematically showing the electronic device according to the embodiment. FIG. 3 is a plan view schematically showing the electronic apparatus according to the embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. The figure for demonstrating the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the electronic apparatus which concerns on the modification of this embodiment.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

1. Electronic Device First, an electronic device according to the present embodiment will be described with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing an electronic device 100 according to this embodiment. FIG. 2 is a plan view schematically showing the electronic device 100. 1 is a cross-sectional view taken along the line II of FIG. In FIG. 2, the resist layer 8 is not shown for convenience.

  As shown in FIGS. 1 and 2, the electronic device 100 includes a substrate 10, a functional element 20, interlayer insulating layers (first interlayer insulating layer 30a, second interlayer insulating layer 30b, and third interlayer insulating layer 30c), The 1st coating layer 40, the resin layer 50, and the 2nd coating layer 60 are included. The electronic device 100 can further include a metal layer 70, a wiring layer 80, an external terminal 82, and a drive circuit 90.

  As the substrate 10, for example, a semiconductor substrate such as a silicon substrate can be used. As the substrate 10, various substrates such as a ceramic substrate, a glass substrate, a sapphire substrate, and a synthetic resin substrate may be used. The substrate 10 includes a functional element formation region 12 in which the functional element 20 is formed, and a drive circuit formation region 14 in which a drive circuit 90 for driving the functional element 20 is formed.

  The functional element 20 is accommodated in the cavity 32 of the interlayer insulating layers 30a, 30b, 30c. As shown in FIG. 1, the functional element 20 is a vibrator composed of a fixed electrode 22 formed on the element isolation layer 11 and a movable electrode 24 formed at a fixed interval from the fixed electrode 22. is there. The movable electrode 24 connects the fixed portion 24a formed on the element isolation layer 11, the oscillating movable portion (beam) 24b disposed to face the fixed electrode 22, and the movable portion 24b and the fixed portion 24a. And a support portion 24c for supporting the As a material of the fixed electrode 22 and the movable electrode 24, for example, polycrystalline silicon imparted with conductivity by doping a predetermined impurity can be cited.

  The fixed electrode 22 and the movable electrode 24 are electrically connected to the drive circuit 90. When a voltage is applied between the electrodes 22 and 24 from the drive circuit 90, the movable electrode 24 vibrates due to the electrostatic force generated between the electrodes 22 and 24. Thus, a desired frequency can be obtained by vibrating the functional element 20 by the drive circuit 90. That is, the electronic device 100 is an oscillator in which a vibrator and a drive circuit (oscillation circuit) 90 are provided on the same substrate 10.

  The functional element 20 may be various functional elements such as a crystal resonator, a SAW (surface acoustic wave) element, an acceleration sensor, a gyroscope, and a microactuator other than the above-described vibrator. In other words, the electronic device of the present invention only needs to have any functional element that can be accommodated in the cavity 32.

  Interlayer insulating layers 30 a, 30 b and 30 c are formed on the substrate 10. The interlayer insulating layers 30a, 30b, and 30c have a cavity 32 in which the functional element 20 is accommodated. The inside of the cavity 32 is in a reduced pressure state, for example. In the illustrated example, the cavity 32 is a region defined by the side surfaces of the interlayer insulating layers 30a, 30b, and 30c, the first covering layer 40, and the substrate 10 (element isolation layer 11).

  Surrounding walls (guard rings) (first surrounding wall 2a, second surrounding wall 2b, and third surrounding wall 2c) are formed in the cavity portion 32. Each surrounding wall 2 a, 2 b, 2 c has a planar shape surrounding the functional element 20. The planar shape of the surrounding walls 2a, 2b, 2c is not particularly limited as long as it surrounds the functional element 20, and is, for example, an arbitrary shape such as a circular shape or a polygonal shape. Each of the surrounding walls 2 a, 2 b, 2 c is conductively connected, and is configured as an integral side wall surrounding the functional element 20. The surrounding walls 2a, 2b, 2c may be formed avoiding wiring (not shown) for connecting the functional element 20 and the drive circuit 90. Examples of the material of the surrounding walls 2a, 2b, and 2c include polycrystalline silicon, metals such as aluminum, copper, tungsten, and titanium, and alloys thereof.

  As shown in FIG. 1, the first covering layer 40 is formed above the cavity 32. A through hole 42 is formed in the first coating layer 40. The number of through holes 42 is two in the example of FIG. 1, but the number is not limited. In the illustrated example, the first covering layer 40 is formed integrally with the third surrounding wall 2c. The first covering layer 40 covers the upper portion of the cavity 32. Therefore, the functional element 20 is surrounded by the substrate 10, the surrounding walls 2 a, 2 b, 2 c and the first covering layer 40. The first coating layer 40 has a laminated structure in which, for example, a titanium layer, a titanium nitride layer, an aluminum-copper alloy layer, and a titanium nitride layer are laminated in this order. The film thickness of the first coating layer 40 is, for example, about several hundred nm.

  It is desirable that a constant potential (for example, ground potential) is applied to the surrounding walls 2a, 2b, 2c and the first covering layer 40. Thereby, the surrounding walls 2a, 2b, 2c and the first covering layer 40 can function as electromagnetic shields. That is, the functional element 20 can be shielded to some extent electromagnetically from the outside.

  The resin layer 50 is formed above the interlayer insulating layers 30a, 30b, and 30c, avoiding the upper part of the cavity 32. That is, the resin layer 50 is not formed above the cavity 32. In the example of FIG. 1, the resin layer 50 is formed above the interlayer insulating layers 30a, 30b, and 30c with the passivation film 6 interposed therebetween. For example, by providing the opening 52 in the resin layer 50, it is possible to provide a region where the resin layer 50 is not formed above the cavity 32. The resin layer 50 can have, for example, a stress relaxation function. The resin layer 50 can be formed of a resin such as polyimide resin, silicone-modified polyimide resin, epoxy resin, silicone-modified epoxy resin, benzocyclobutene (BCB), polybenzoxazole (PBO). The film thickness of the resin layer 50 is, for example, 10 μm or more. The side surface of the resin layer 50 may be inclined so that the bottom surface is larger than the top surface. The resin layer 50 can be formed between the interlayer insulating layers 30 a, 30 b, 30 c and the external terminal 82.

  The second coating layer 60 is formed on the first coating layer 40. In the example of FIG. 1, the second coating layer 60 is formed on the first coating layer 40 and the resin layer 50. That is, a part of the second coating layer 60 is formed above the first coating layer 40 via the resin layer 50. The second coating layer 60 closes the through hole 42 of the first coating layer 40. Examples of the material of the second coating layer 60 include metals such as aluminum, titanium, and tungsten. The film thickness of the second coating layer 60 is, for example, about 3 μm. The first coating layer 40 and the second coating layer 60 can function as a sealing member that covers the cavity 32 from above and seals the cavity 32.

  The metal layer 70 is formed on the second coating layer 60. In the illustrated example, the metal layer 70 is formed so as to cover the second coating layer 60. By forming the metal layer 70 on the second coating layer 60, the strength of the second coating layer 60 can be improved. The metal layer 70 has a laminated structure in which, for example, a titanium-tungsten alloy layer and a copper layer are laminated in this order. The metal layer 70 may have a single-layer structure of metal layers such as a copper layer, a chromium layer, and an aluminum layer, or a stacked structure in which these layers are stacked.

  The wiring layer 80 is formed on the resin layer 50. In the illustrated example, the wiring layer 80 is formed so as to extend from the electrode 4 to the upper surface of the resin layer 80. The wiring layer 80 is electrically connected to the functional element 20 via, for example, the electrode 4, the wiring 5, and the drive circuit 90. Examples of the material of the wiring layer 80 include the same material as that of the metal layer 70. As will be described later, the wiring layer 80 and the metal layer 70 can be formed in the same process.

  The metal layer 70 is covered with a resist layer 8 as shown in FIG. The wiring layer 80 is covered with the resist layer 8 except for the region where the external terminals 82 are formed. Therefore, oxidation and corrosion of the wiring layer 80 and the metal layer 70 can be prevented, and an electrical failure can be prevented.

  The external terminal 82 is formed on the wiring layer 80. That is, the external terminal 82 is formed above the resin layer 50 via the wiring layer 80. The external terminal 82 is electrically connected to the wiring layer 80. The external terminal 82 is a metal (for example, an alloy) having conductivity, and is for melting and achieving electrical connection (for example, solder). The external terminal 82 is spherical, for example. In the example of FIG. 2, four external terminals 82 are provided, but the number is not limited.

  When the substrate 10 is a semiconductor chip, the external terminals 82 can be directly provided on the semiconductor chip, so that the electronic device 100 can have a package size substantially equal to that of the semiconductor chip. That is, the package structure of the electronic device 100 is a WCSP structure.

  The drive circuit 90 is formed on the substrate 10. The drive circuit 90 includes, for example, the transistor 92 and the capacitor 96 shown in FIG. The drive circuit 90 is a circuit for driving the functional element 20. At least an oscillation circuit is formed in the drive circuit 90, one of the output portions thereof is electrically connected to the fixed electrode 22 of the functional element 20, and the other of the output portions is electrically connected to the movable electrode 24.

  The electronic device 100 has the following features, for example.

  According to the electronic device 100, the resin layer 50 can be formed avoiding the upper portion of the cavity portion 32. Therefore, it is possible to reduce the influence of the film stress of the resin layer 50 (the tensile stress and the compressive stress that the resin layer 50 has) on the coating layers 40 and 60. Thereby, the coating layers 40 and 60 are destroyed due to the film stress of the resin layer 50 and the pressure of the cavity portion 32 is increased, or the coating layers 40 and 60 are deformed to hinder the operation of the functional element 20. Can be prevented. Therefore, the electronic device 100 can have a functional element with good characteristics and high reliability.

  According to the electronic device 100, the metal layer 70 can be formed on the second coating layer 60. Thereby, the intensity | strength of the 2nd coating layer 60 can be improved. Therefore, for example, the coating layers 40 and 60 can be prevented from being broken due to a difference in thermal expansion coefficient between the substrate 10 and the coating layers 40 and 60 due to heat from the outside, and the pressure in the cavity 32 can be prevented from rising. . Thereby, the deterioration of the characteristic of the functional element 20 can be prevented, and reliability can be improved.

  According to the electronic device 100, the wiring layer 80 formed on the resin layer 50 and electrically connected to the functional element 20, and the external terminal 82 formed on the wiring layer 80 and electrically connected to the wiring layer 80. , Can be included. That is, in the electronic device 100, since the external terminals 82 can be directly provided on the substrate 10 (semiconductor chip) without using bonding wires or the like, the size and cost of the device can be reduced.

  According to the electronic device 100, the drive circuit 90 can be formed on the substrate 10. Therefore, the size and cost of the device can be reduced as compared with the case where the drive circuit is provided outside the device.

2. Next, a method for manufacturing the electronic device 100 according to the present embodiment will be described with reference to the drawings. 3 to 12 are cross-sectional views schematically showing the manufacturing process of the electronic device 100. FIG. 13 is a diagram for explaining a manufacturing process of the electronic device 100.

  As shown in FIG. 3, the functional element 20 is formed on the substrate 10. The substrate 10 is, for example, a silicon wafer. Specifically, first, the fixed electrode 22 is formed by a film forming process such as a CVD method or a sputtering method, and a patterning process. When the fixed electrode 22 is made of polycrystalline silicon, a predetermined impurity is doped in order to impart conductivity. In FIG. 3, the fixed electrode 22 is formed on the element isolation layer 11, but may be formed on a base layer (not shown) made of, for example, silicon nitride. This underlayer can function as an etching stop layer in a release process described later.

  Next, a sacrificial layer 25 that covers the fixed electrode 22 is formed by performing thermal oxidation treatment. Next, the movable electrode 24 is formed on the sacrificial layer 25. The movable electrode 24 is formed by a film forming process such as a CVD method or a sputtering method, and a patterning process. When the movable electrode 24 is made of polycrystalline silicon, a predetermined impurity is doped in order to impart conductivity. The functional element 20 is formed by the above process.

  Note that the members such as the transistor 92 and the capacitor 96 constituting the driving circuit 90 may be formed in the same process or the same process as the process of forming the functional element 20 described above. Specifically, for example, in the step of forming the fixed electrode 22 described above, the lower electrode 97 of the capacitor 96 is formed, and in the step of forming the sacrificial layer 25, the gate oxide film 94 of the transistor 92 and the insulating film of the capacitor 96 are formed. 98 may be formed. Further, in the step of forming the movable electrode 24, the gate electrode 93 of the transistor 92 and the upper electrode 99 of the capacitor 96 may be formed. In this way, by sharing the manufacturing process of the functional element 20 and the drive circuit 90, the manufacturing process can be simplified.

  As shown in FIG. 4, the 1st interlayer insulation layer 30a which covers the functional element 20 is formed. Further, the first interlayer insulating layer 30 a may be formed so as to cover the transistor 92 and the capacitor 96. The first interlayer insulating layer 30a can be formed by, for example, a CVD method or a coating (spin coating) method. After forming the first interlayer insulating layer 30a, a process for planarizing the surface of the first interlayer insulating layer 30a may be performed.

  Next, the first surrounding wall 2a surrounding the functional element 20 is formed. The first surrounding wall 2a is formed, for example, by patterning the first interlayer insulating layer 30a to form a groove penetrating the first interlayer insulating layer 30a and embedding a metal such as aluminum in the groove.

  As shown in FIG. 5, a second interlayer insulating layer 30b, a third interlayer insulating layer 30c, a second surrounding wall 2b, and a third surrounding wall 2c are formed. The second interlayer insulating layer 30b, the third interlayer insulating layer 30c, the second surrounding wall 2b, and the third surrounding wall 2c are formed, for example, in the same manner as the first interlayer insulating layer 30a and the first surrounding wall 2a.

  Next, the first covering layer 40 is formed on the third interlayer insulating layer 30 c above the functional element 20. The first coating layer 40 can be formed by, for example, forming a film by a sputtering method, a CVD method, or the like and then patterning the film by a photolithography technique or the like.

  The electrode 4 and the wiring 5 that electrically connect the functional element 20 and the wiring layer 80 (see FIG. 1), the wiring (not shown) that connects the functional element 20 and the drive circuit 90, and the like are included in the surrounding wall 2a. , 2b, 2c and the first coating layer 40 may be formed by the same process or the same process. Thus, the manufacturing process can be simplified by sharing the manufacturing process of the surrounding walls 2a, 2b, 2c, the first covering layer 40, the wiring 5, the electrode 4, and the like.

  As shown in FIG. 6, a through hole 42 is formed in the first coating layer 40. The through hole 42 is formed by, for example, a photolithography technique. The step of forming the through hole 42 may be performed in the same step as the step of forming the first coating layer 40. That is, the through hole 42 may be formed by patterning in the step of forming the first coating layer 40. Thereby, a manufacturing process can be simplified.

As shown in FIG. 7, the passivation film 6 is formed on the third interlayer insulating layer 30c. As the passivation film 6, a polyimide film, a PSG (Phosphorus Silicon Glass) film formed by a CVD method, or a Si ₃ N ₄ film formed by a plasma CVD method can be used.

  Next, the resin layer 50 is formed on the third interlayer insulating layer 30 c and the first covering layer 40. In the illustrated example, the resin layer 50 is formed above the third interlayer insulating layer 30 c and on the first covering layer 40 via the passivation film 6. The resin layer 50 is formed, for example, by applying a resin by a spin coating method and performing a heat treatment at about 300 to 400 ° C. in a nitrogen atmosphere.

  As shown in FIG. 8, an opening 52 is formed in the resin layer 50. The opening 52 is formed at least above the through hole 42 and is formed to communicate with the through hole 42. In the illustrated example, by forming the opening 52 in the resin layer 50, the resin layer 50 is formed on the third interlayer insulating layer 30c while avoiding the upper side of the functional element 20 (above the region where the cavity 32 is formed). Is formed. That is, the opening 52 is formed so that the first coating layer 40 is exposed. The opening 52 is formed by etching the resin layer 50 by a known etching technique. In this step, the resin layer 50 in other regions such as above the electrode 4 may be removed.

  As shown in FIG. 9, the interlayer insulating layers 30a, 30b, 30c and the sacrificial layer 25 above the functional element 20 are removed through the through holes 42 to form the cavity 32 (release process). For example, the interlayer insulating layers 30a and 30b may be formed by wet etching using hydrofluoric acid or buffered hydrofluoric acid (mixed liquid of hydrofluoric acid and ammonium fluoride) or dry etching using a hydrogen fluoride-based gas. 30c and the sacrificial layer 25 can be etched to form the cavity 32. The surrounding walls 2a, 2b, 2c and the first covering layer 40 are formed of a material that is not etched in the release process, so that the cavity 32 can be prevented from spreading outside the surrounding walls 2a, 2b, 2c. .

  As shown in FIG. 10, the second coating layer 60 is formed on the first coating layer 40 and the resin layer 50. The second coating layer 60 is formed on at least the through hole 42 of the first coating layer 40. Thereby, the through-hole 42 can be plugged and the cavity 32 can be sealed. The second coating layer 60 can be formed by, for example, a vapor phase growth method such as a sputtering method or a CVD method. Thereby, the cavity part 32 can be sealed with a reduced pressure state.

  As shown in FIG. 11, an opening is formed in the passivation film 6 to expose the electrode 4. The opening can be formed by, for example, a photolithography technique.

  Next, the wiring layer 80 is formed on the resin layer 50. In this step, the metal layer 70 may be formed on the second coating layer 60. As an example of the formation process of the wiring layer 80, first, a barrier layer (not shown) made of a titanium-tungsten alloy and copper are formed on the entire surface of the second coating layer 60, the resin layer 80, and the electrode 4. A seed layer (not shown) is formed. Next, a copper layer (not shown) is formed by electroplating over the region to be the wiring layer 80 and the second coating layer 60 using photolithography technology. Next, the seed layer in the region where the copper layer is not formed is removed by wet etching using an aqueous ammonium persulfate solution, and the barrier layer is removed by dry etching. Here, when the seed layer and the barrier layer are etched, the metal layer 70 (laminated body including the barrier layer, the seed layer, and the copper layer) is formed on the second coating layer 60. Thus, damage to the second coating layer 60 can be reduced. Through the above steps, the wiring layer 80 is formed.

  As shown in FIG. 12, a resist layer 8 is formed on the resin layer 50, the metal layer 70, and the wiring layer 80. The resist layer 8 is formed so as to avoid a region where the external terminal 82 of the wiring layer 80 is formed. The resist layer 8 can be formed by, for example, a spin coating method.

  Next, external terminals 82 are formed on the wiring layer 80. The external terminals 82 are formed by forming a solder layer (not shown) on the wiring layer 80 and then heating to melt the solder.

  As shown in FIG. 13, the blade 1 is used for dicing, and as shown in FIG. 2, it is cut into individual electronic devices.

  Through the above steps, the electronic device 100 can be manufactured.

  The method for manufacturing the electronic device 100 has the following features, for example.

  According to the method for manufacturing the electronic device 100, the step of forming the cavity 32 can be performed after the step of forming the resin layer 50. Therefore, even if heat treatment is performed in the process of forming the resin layer 50, the cavity portion 32 is not formed, so that there is no problem that gas is generated in the cavity portion 32 and the pressure increases. Therefore, according to the manufacturing method of the electronic device 100, an electronic device having a functional element with good characteristics can be manufactured.

  According to the method for manufacturing the electronic device 100, the opening 52 can be formed in the resin layer 50. Thereby, the influence which the film | membrane stress of the resin layer 50 has on the coating layers 40 and 60 can be reduced. Accordingly, it is possible to prevent the coating layers 40 and 60 from being broken and the pressure of the cavity portion 32 from being increased due to the film stress of the resin layer, or the coating layers 40 and 60 from being deformed to hinder the operation of the functional element 20. Can do. Therefore, according to the method for manufacturing the electronic device 100, an electronic device having a functional element with good characteristics and high reliability can be manufactured.

  Furthermore, according to the method for manufacturing the electronic device 100, in the step of forming the opening 52, the opening 52 can be formed so as to expose the first coating layer 40. Therefore, the influence which the film | membrane stress of the resin layer 50 has on the coating layers 40 and 60 can be further reduced.

  According to the method for manufacturing the electronic device 100, the metal layer 70 can be formed on the second coating layer 60 in the step of forming the wiring layer 80. Therefore, in the step of forming the wiring layer 80, damage that the second coating layer 60 receives can be reduced.

  According to the method for manufacturing the electronic device 100, as described above, the step of forming the external terminal 82 can be performed in the wafer process. Therefore, the conventional packaging process, that is, the inner lead bonding process, the external terminal forming process, etc. may not be performed on each individual semiconductor chip. Moreover, when forming a resin layer, substrates, such as a patterned film, become unnecessary. According to the method for manufacturing the electronic device 100, a low-cost and high-quality electronic device can be manufactured for these reasons.

3. Next, an electronic device 200 according to a modification of the present embodiment will be described with reference to the drawings. FIG. 14 is a cross-sectional view schematically showing the electronic device 200 and corresponds to FIG. Hereinafter, in the electronic device 200, members having the same functions as the components of the electronic device 100 according to the present embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the example of the electronic device 100, the resin layer 50 is formed on the third interlayer insulating layer 30 c so as to avoid the upper portion of the cavity 32. That is, the resin layer 50 was not formed above the hollow portion 32. In the electronic device 200, the resin layer 50 is also formed on a part above the hollow portion 32. That is, as shown in FIG. 14, the resin layer 50 is formed on the first covering layer 40 and the third interlayer insulating layer 30 c and has an opening 52 formed in a part above the cavity 32. Can do. Therefore, similarly to the electronic device 100, the influence of the film stress of the resin layer 50 on the coating layers 40 and 60 can be reduced as compared with the case where the opening 52 is not formed.

  In the electronic device 200, the resin layer 50 is not formed on a part of the upper surface of the first coating layer 40 by forming the opening 52 in the resin layer 50. That is, the opening 52 penetrates the resin layer 50. Thereby, compared with the case where the opening part 52 does not penetrate the resin layer 50, the influence which the film | membrane stress of the resin layer 50 has on the coating layers 40 and 60 can be reduced.

  Although not shown, the opening 52 may not penetrate the resin layer 50. That is, the opening 52 is a region where the resin layer 50 is thinner than the region where the opening 52 of the resin layer 50 is not formed. In this case, the resin layer 50 may be formed on the entire top surface of the first coating layer 40 (except on the through holes 42), and the second coating layer 60 is formed via the resin layer 50. Formed on top.

  The position where the opening 52 is formed is not particularly limited as long as it is above the cavity 32. In the illustrated example, one opening 52 is provided, but a plurality of openings 52 may be provided. The plurality of openings 52 may be provided in a lattice shape or a stripe shape, for example.

  Since the manufacturing method of the electronic device 200 is the same as the manufacturing method of the electronic device 100, description thereof is omitted.

  According to the electronic device 200, the same effect as the electronic device 100 can be obtained.

  The present invention is not limited to the above-described embodiments and modifications, and various modifications can be made within the scope of the gist of the present invention.

  For example, in the example of the electronic device 100 and the electronic device 200, the drive circuit 90 is formed on the substrate 10, but the drive circuit for driving the functional element may be provided outside. That is, the electronic device may not have a driving circuit. The external terminal of the electronic device may be electrically connected to the functional element through wiring or the like.

  In addition, embodiment mentioned above and a modification are examples, Comprising: It is not necessarily limited to these. For example, the embodiment and the modification examples can be appropriately combined.

  Although the embodiments of the present invention have been described in detail as described above, those skilled in the art will readily understand that many modifications are possible without substantially departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention.

2a 1st surrounding wall, 2b 2nd surrounding wall, 2c 3rd surrounding wall, 4 electrodes, 5 wiring,
6 Passivation film, 8 Resist layer, 10 Substrate, 11 Device isolation layer,
12 functional element forming area, 14 drive circuit forming area, 20 functional element, 22 fixed electrode,
24 movable electrode, 25 sacrificial layer, 30a first interlayer insulating layer, 30b second interlayer insulating layer,
30c 3rd interlayer insulation layer, 32 cavity part, 40 1st coating layer, 42 through-hole,
50 resin layer, 52 opening, 60 second coating layer, 70 metal layer, 80 wiring layer,
82 external terminal, 90 driving circuit, 92 transistor, 93 gate,
94 gate oxide film, 96 capacitor, 97 lower electrode, 98 insulating layer,
99 Upper electrode, 100,200 Electronic device

Claims (5)

Forming a functional element above the substrate;
Forming an interlayer insulating layer covering the functional element;
Forming a first covering layer above the functional element and above the interlayer insulating layer;
Forming a through hole in the first coating layer;
Forming a resin layer above the interlayer insulating layer and above the first covering layer;
Forming an opening communicating with the through hole in the resin layer above the through hole;
Removing the interlayer insulating layer above the functional element through the through hole to form a cavity;
Forming a second coating layer above the through hole and closing the through hole;
A method for manufacturing an electronic device, comprising: In claim 1,
Forming a wiring layer formed above the resin layer and electrically connected to the functional element;
Forming an external terminal formed above the wiring layer and electrically connected to the wiring layer;
A method for manufacturing an electronic device, further comprising: In claim 2,
The method of manufacturing an electronic device, wherein in the step of forming the wiring layer, a metal layer is formed above the second coating layer. In any one of Claims 1 thru | or 3,
The method of manufacturing an electronic device, wherein, in the step of forming the opening, the opening is formed so as to expose at least a part of the upper surface of the first covering layer. In any one of Claims 1 thru | or 4,
The process for forming the first covering layer and the process for forming the through hole are performed in the same process.

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