JP2012146893A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a fuse element with stable characteristics.SOLUTION: A semiconductor device 100 includes: a substrate 10; a coating structure 30 that is formed above the substrate 10 and defines a cavity part 20; and fuse elements 40a, 40b, and 40c contained in the cavity part 20. The coating structure 30 has a conductive layer. The material of the fuse elements 40a, 40b, and 40c is the same as the material of the conductive layer.

Description

  The present invention relates to a semiconductor device.

  In general, a semiconductor device in which a semiconductor integrated circuit formed of a transistor, a capacitor, or the like, or a functional element such as MSMS (Micro Electro Mechanical Systems) is formed on a semiconductor substrate is known (for example, Patent Documents 1 and 2). reference).

  In such a semiconductor device, for example, an element having good characteristics may be selected and used from a plurality of elements formed on a semiconductor substrate in order to improve product yield. For example, in Patent Document 2, a defective capacitor having a large leak current is detected in a defect inspection process, and a fuse element connected to the defective capacitor is blown to electrically isolate the defective capacitor from the circuit. Semiconductor devices that can be described are described. In the semiconductor device described in Patent Document 2, a fuse portion (fuse element) is provided in an interlayer insulating film having a laminated structure.

JP-A-2005-123561 JP 2005-123376 A

  However, in the fuse element formed in the interlayer insulating layer, the heat generated by the fuse element when the fuse element is blown may be absorbed by the interlayer insulating layer, and the amount of current required for blowing may increase. For this reason, the amount of current and time required for fusing may fluctuate, which may cause a problem that the characteristics of the fuse element are not stable.

  An object of some aspects of the present invention is to provide a semiconductor device having a fuse element with stable characteristics.

A semiconductor device according to the present invention includes:
A substrate,
A covering structure formed above the substrate and defining a cavity;
A fuse element housed in the cavity,
Including
The covering structure has a conductive layer;
The material of the fuse element is the same as the material of the conductive layer.

  According to such a semiconductor device, since the fuse element is accommodated in the cavity, it is possible to make it difficult for heat generated by the fuse element to escape when the fuse element is melted. Therefore, the characteristics of the fuse element can be stabilized.

  In the description according to the present invention, the word “upper” is used, for example, “specifically” (hereinafter referred to as “A”) is formed above another specific thing (hereinafter referred to as “B”). The word “above” is used to include the case where B is formed directly on A and the case where B is formed on A via another object. Used.

In the semiconductor device according to the present invention,
A plurality of the fuse elements may be accommodated in the cavity.

In the semiconductor device according to the present invention,
Furthermore, a wall portion that partitions between adjacent fuse elements may be included.

  According to such a semiconductor device, it is possible to prevent the blown fuse element from scattering and adhering to other fuse elements.

In the semiconductor device according to the present invention,
The cavity may be in a reduced pressure state.

  According to such a semiconductor device, the heat generated by the fuse element can be made difficult to escape. Therefore, the characteristics of the fuse element can be further stabilized.

In the semiconductor device according to the present invention,
The fuse element may be separated from the substrate.

  According to such a semiconductor device, the heat generated by the fuse element can be made difficult to escape. Therefore, the characteristics of the fuse element can be further stabilized.

In the semiconductor device according to the present invention,
The conductive layer may surround the cavity in plan view.

1 is a circuit diagram of a semiconductor device according to a first embodiment. FIG. 2 is a plan view schematically showing the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view schematically showing the semiconductor device according to the first embodiment. Sectional drawing which shows typically the wiring of the semiconductor device which concerns on 1st Embodiment. FIG. 3 is a cross-sectional view schematically showing the fuse element of the semiconductor device according to the first embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on 1st Embodiment. Sectional drawing which shows typically the semiconductor device which concerns on the 1st modification of 1st Embodiment. The top view which shows typically the semiconductor device which concerns on the 2nd modification of 1st Embodiment. Sectional drawing which shows typically the semiconductor device which concerns on the 2nd modification of 1st Embodiment. Sectional drawing which shows typically the semiconductor device which concerns on the 3rd modification of 1st Embodiment. Sectional drawing which shows typically the semiconductor device which concerns on the 4th modification of 1st Embodiment. Sectional drawing which shows typically the semiconductor device which concerns on 2nd Embodiment.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

1. 1. First embodiment 1.1. Semiconductor Device First, the semiconductor device according to the first embodiment will be described with reference to the drawings. FIG. 1 is a circuit diagram of a semiconductor device 100 according to the present embodiment. FIG. 2 is a plan view schematically showing the semiconductor device 100. FIG. 3 is a cross-sectional view schematically showing the semiconductor device 100. 3 is a cross-sectional view taken along line III-III in FIG. 2, the illustration of the substrate 10, the base layer 11, the first covering layer 32, the second covering layer 34, the interlayer insulating layers 36a, 36b, 36c, and the protective films 50, 52 is omitted for convenience.

  1 to 3, the semiconductor device 100 includes a substrate 10, a cavity 20, a covering structure 30, fuse elements 40a, 40b, 40c, protective films 50, 52, resistors R1, R2, R3, R4.

As shown in FIG. 1, the semiconductor device 100 includes a resistance voltage dividing circuit that can generate a voltage _VOUT that is proportional to the input voltage V _DD . In the semiconductor device 100, a desired voltage _VOUT can be obtained by selecting the resistors R2, R3, and R4 by the fuse elements 40a, 40b, and 40c.

  As the substrate 10, for example, a semiconductor substrate such as a silicon substrate can be used. As the substrate 10, various substrates such as a ceramic substrate, a glass substrate, a sapphire substrate, and a synthetic resin substrate may be used. As shown in FIG. 3, a base layer 11 is formed on the substrate 10. The underlayer 11 has, for example, a stacked structure in which a silicon oxide layer and a silicon nitride layer are stacked in this order from the substrate 10 side.

  As illustrated in FIG. 3, the covering structure 30 is formed above the substrate 10 and defines the cavity 20. The covering structure 30 includes surrounding walls (guard rings) 30a, 30b, 30c, and 30d, covering layers 32 and 34, and interlayer insulating layers 36a, 36b, and 36c.

  The surrounding walls 30 a, 30 b, 30 c and 30 d are formed above the substrate 10. The first surrounding wall 30 a is provided on the foundation layer 11. The second surrounding wall 30b is provided on the first surrounding wall 30a, the third surrounding wall 30c is provided on the second surrounding wall 30b, and the fourth surrounding wall 30d is provided on the third surrounding wall 30c. ing. Each surrounding wall 30a, 30b, 30c, 30d consists of a conductive layer. The material of the first surrounding wall 30a is, for example, polycrystalline silicon imparted with conductivity by being doped with a predetermined impurity, and the materials of the second to fourth surrounding walls 30b, 30c, 30d are, for example, A metal such as aluminum, copper, tungsten, titanium, or an alloy thereof. As shown in FIG. 2, the surrounding walls 30a, 30b, 30c, and 30d are formed so as to surround the cavity 20 in a plan view. The shape of the surrounding walls 30a, 30b, 30c, and 30d is not particularly limited as long as it is a shape that surrounds the cavity 20 in plan view, and is, for example, a circular shape or a polygonal shape. The surrounding walls 30 a, 30 b, 30 c, and 30 d are conductively connected and constitute an integral side wall that surrounds the cavity 20. The surrounding walls 30a, 30b, 30c, and 30d are formed so as to avoid the wiring 42 as shown in FIG.

  In the example of FIGS. 2 and 3, wirings other than the wiring 42 and the surrounding walls 30a, 30b, 30c, and 30d and resistors R1, R2, R3, and R4 are not shown, but on the substrate 10 and between the layers. Other wirings and resistors R1, R2, R3, and R4 are formed in the insulating layers 36a, 36b, and 36c.

  The first covering layer 32 covers the upper portion of the cavity 20. A through hole 33 is formed in the first coating layer 32. The number of through holes 33 is not particularly limited. For example, the first covering layer 32 is formed integrally with the fourth surrounding wall 30d. The first coating layer 32 has a laminated structure in which, for example, a titanium layer, a titanium nitride layer, an aluminum-copper alloy layer, and a titanium nitride layer are laminated in this order. The film thickness of the first coating layer 32 is, for example, about several hundred nm.

  It is desirable that a constant potential (for example, ground potential) is applied to the surrounding walls 30a, 30b, 30c, 30d and the first covering layer 32. Thereby, the surrounding walls 30a, 30b, 30c, 30d and the first covering layer 32 can function as an electromagnetic shield.

  The second coating layer 34 is formed on the first coating layer 32. The second coating layer 34 closes the through hole 33 of the first coating layer 32. Examples of the material of the second coating layer 34 include metals such as aluminum, titanium, and tungsten. The film thickness of the second coating layer 34 is, for example, about 3 μm. The first coating layer 32 and the second coating layer 34 can function as a sealing member that covers the cavity 20 from above and seals the cavity 20.

  The interlayer insulating layers 36a, 36b, and 36c are formed above the substrate 10. The interlayer insulating layers 36a, 36b, and 36c are three layers in the illustrated example, but the number of stacked layers is not particularly limited. The interlayer insulating layers 36a, 36b, and 36c are formed so as to surround the cavity 20 in plan view. The material of the interlayer insulating layers 36a, 36b, 36c is, for example, silicon oxide.

  The cavity 20 is a region surrounded by the covering structure 30 and the base layer 11. The cavity 20 accommodates the first fuse element 40a, the second fuse element 40b, and the third fuse element 40c. In the illustrated example, three fuse elements 40a, 40b, and 40c are accommodated in the hollow portion 20, but the number is not limited. The cavity 20 is in a reduced pressure state, for example.

  The fuse elements 40a, 40b, 40c are made of, for example, a linear or plate-like conductor, and are blown by heat generated by the fuse elements 40a, 40b, 40c themselves when a current (melting current) of a certain level or more flows. It is a soluble body provided. The fuse elements 40a, 40b, and 40c are electrically connected to the wiring 42, and a fusing current is supplied by the wiring 42. The widths of the fuse elements 40a, 40b, and 40c are smaller than the width of the wiring 42 in plan view as shown in FIG.

  The wiring 42 is a wiring for supplying a fusing current to the fuse elements 40a, 40b, and 40c. The wiring 42 is electrically connected to a pad (not shown) provided outside the cavity 20. The wiring 42 can supply a fusing current to the fuse elements 40a, 40b, and 40c by supplying a current from the pad.

  As shown in FIGS. 2 and 3, the fuse elements 40 a, 40 b, and 40 c are supported by the wiring 42, and are separated from the base layer 11 (substrate 10) in the cavity 20. That is, the fuse elements 40a, 40b, and 40c are not in contact with members other than the wiring 42. The height of the fuse elements 40a, 40b, 40c (distance from the upper surface of the substrate 10) is the same as the height of the upper surface of the first interlayer insulating layer 36a in the example of FIG. As will be described later in the manufacturing process, the fuse elements 40a, 40b, 40c and the second surrounding wall 30b are formed of the same conductive layer. That is, the material of the fuse elements 40a, 40b, and 40c is the same material as that of the conductive layer that constitutes the second surrounding wall 30b. The height of the fuse elements 40a, 40b, and 40c is the same as the height of the upper surface of the second interlayer insulating layer 36b, and the material of the fuse elements 40a, 40b, and 40c is the conductive layer that constitutes the third surrounding wall 30c. The same material may be used.

  In the illustrated example, the wiring 42 and the fuse elements 40a, 40b, and 40c are not in contact with the base layer 11, but the wiring 42 may be in contact with the base layer 11. In that case, the wiring 42 may have a support member for separating the fuse elements 40a, 40b, and 40c from the base layer 11.

  FIG. 4 is a cross-sectional view schematically showing the wiring 42 of the semiconductor device 100. FIG. 5 is a cross-sectional view schematically showing the second fuse element 40 b of the semiconductor device 100. 4 is a cross-sectional view taken along the line IV-IV in FIG. 2, and FIG. 5 is a cross-sectional view taken along the line V-V in FIG.

  As illustrated in FIG. 4, the wiring 42 includes a first layer 46 and a second layer 48 that sandwiches the first layer 46. The second fuse element 40b includes a first layer 46 as shown in FIG. In the illustrated example, the thickness of the second fuse element 40 b is thinner than the thickness of the wiring 42 by the thickness of the second layer 48. The material of the first layer 46 is, for example, an aluminum-copper alloy, and the material of the second layer 48 is, for example, titanium nitride. Thus, since the wiring 42 has the second layer 48 made of titanium nitride having a high melting point and the second fuse element 40b does not have the second layer 48, the second fuse element 40b is blown out compared to the wiring 42. Can be easier. Although the second fuse element 40b has been described here, the first fuse element 40a and the third fuse element 40c may have the same structure.

  As shown in FIG. 3, the first protective film 50 is formed on the first covering layer 32 and the third interlayer insulating layer 36c. The material of the first protective film 50 is, for example, silicon oxide. The second protective film 52 is formed on the first protective film 50. The material of the second protective film 52 is, for example, silicon nitride.

  For example, the semiconductor device 100 has the following characteristics.

  In the semiconductor device 100, the fuse elements 40 a, 40 b, and 40 c are accommodated in the cavity 20. Further, fuse elements 40a, 40b, and 40c are provided apart from the base layer 11 (substrate 10). That is, according to the semiconductor device 100, the fuse elements 40 a, 40 b, and 40 c can be provided so as not to contact other members other than the wiring 42. For example, when a fuse element is provided in an interlayer insulating layer, the fuse element is covered with the interlayer insulating layer. Therefore, when the fuse element is blown, the heat generated by the fuse element is absorbed by the interlayer insulating layer and the fusing current is increased. There may be no. Therefore, the amount of current and time required for fusing the fuse element vary, and stable characteristics may not be obtained. On the other hand, in the semiconductor device 100, the fuse elements 40a, 40b, and 40c can be provided so as not to contact other members than the wiring 42. Therefore, the heat generated by the fuse elements 40a, 40b, 40c can be made difficult to escape when the fuse elements 40a, 40b, 40c are melted, and there is no member that holds down the fuse elements 40a, 40b, 40c. , 40b, 40c can be surely fused with a predetermined current. Therefore, according to the semiconductor device 100, the characteristics of the fuse element can be stabilized.

  Further, for example, when a fuse element is provided in the interlayer insulating layer, the interlayer insulating layer and the protective film for protecting the wiring are destroyed by fusing the fuse element and formed in the interlayer insulating layer. Other wiring may be broken or the other wiring may be exposed and corroded. In the semiconductor device 100, since the fuse elements 40a, 40b, and 40c are accommodated in the cavity 20, such a problem does not occur. Therefore, reliability can be improved. Furthermore, for example, a guard ring for protecting the wiring formed in the interlayer insulating layer is not necessary.

  According to the semiconductor device 100, since the cavity 20 is in a decompressed state, it is possible to make it difficult for the heat generated by the fuse elements 40a, 40b, and 40c to escape when the fuse elements 40a, 40b, and 40c are fused. Therefore, the characteristics of the fuse elements 40a, 40b, and 40c can be further stabilized.

1.2. Method for Manufacturing Semiconductor Device Next, a method for manufacturing the semiconductor device 100 according to the present embodiment will be described with reference to the drawings. 6 to 8 are cross-sectional views schematically showing the manufacturing process of the semiconductor device 100. 6 to 8 correspond to FIG.

  As shown in FIG. 6, fuse elements 40a, 40b, 40c, surrounding walls 30a, 30b, 30c, 30d, interlayer insulating layers 36a, 36b, 36c, covering layers 32, 34, and protective films 50, 52 are formed on the substrate 10. To do. First, the first surrounding wall 30 a is formed on the base layer 11. The first surrounding wall 30a is formed by, for example, a film forming process such as a CVD method or a sputtering method, and a patterning process such as photolithography. Next, a first interlayer insulating layer 36a is formed on the base layer 11 and the first surrounding wall 30a. The first interlayer insulating layer 36a is formed by, for example, a CVD method or a coating (spin coating) method. Next, the second surrounding wall 30b, the fuse elements 40a, 40b, 40c, and the wiring 42 are formed. First, the first interlayer insulating layer 36a is patterned to form a groove penetrating the first interlayer insulating layer 36a, and then a conductive layer is formed on the first interlayer insulating layer 36a and in the groove by CVD or sputtering. Film. By patterning this conductive layer, the second surrounding wall 30b, the fuse elements 40a, 40b, and 40c and the wiring 42 are formed. Next, the second interlayer insulating layer 36b, the third surrounding wall 30c, the third interlayer insulating layer 36c, the fourth surrounding wall 30d, and the first covering layer 32 are the same as the first interlayer insulating layer 36a and the second surrounding wall 30b. To form. A through hole 33 is formed in the first coating layer 32. Next, the first protective film 50 and the second protective film 52 are formed in this order on the third interlayer insulating layer 36c. The protective films 50 and 52 are formed by CVD or sputtering.

  Although not shown, in the step of forming the surrounding walls 30a, 30b, 30c, 30d, other wirings and resistors R1, R2, R3, R4 other than the wiring 42 and the fuse elements 40a, 40b, 40c are formed. May be.

  As shown in FIG. 7, the protective films 50 and 52 are etched to expose the through holes 33 formed in the first covering layer 32. Specifically, first, a resist (not shown) is applied on the second protective film 52, and then exposed and developed to expose the etching regions of the protective films 50 and 52. Next, the protective films 50 and 52 are etched to expose the through holes 33, and then the resist is peeled off.

  As shown in FIG. 8, the interlayer insulating layers 36 a, 36 b, and 36 c around the fuse elements 40 a, 40 b, and 40 c are removed through the through holes 33 to form the cavity 20. Specifically, first, a resist 2 that covers the protective films 50 and 52 is formed. Next, for example, by wet etching using hydrofluoric acid or buffered hydrofluoric acid (mixed liquid of hydrofluoric acid and ammonium fluoride) or dry etching using a hydrogen fluoride-based gas, the fuse The interlayer insulating layers 36a, 36b, and 36c around the elements 40a, 40b, and 40c are removed, and the cavity 20 is formed. The surrounding walls 30a, 30b, 30c, 30d and the first covering layer 32 are formed of a material having a lower etching rate than the interlayer insulating layers 36a, 36b, 36c in this etching step, thereby functioning as an etching stopper.

  As shown in FIG. 3, the second coating layer 34 is formed on the first coating layer 32. The second coating layer 34 is formed at least on the through hole 33 of the first coating layer 32. Thereby, the through-hole 33 can be plugged and the cavity 20 can be sealed. The second coating layer 34 is formed by, for example, a vapor phase growth method such as a sputtering method or a CVD method. Thereby, the cavity 20 can be sealed in a reduced pressure state.

  Through the above steps, the semiconductor device 100 can be manufactured.

1.3. Modified Example Next, a semiconductor device according to a modified example of this embodiment will be described with reference to the drawings. Hereinafter, in the semiconductor device according to the modification of the present embodiment, members having the same functions as those of the constituent members of the semiconductor device 100 are denoted by the same reference numerals, and detailed description thereof is omitted.

(1) First Modification First, a semiconductor device according to a first modification of the present embodiment will be described. FIG. 9 is a cross-sectional view schematically showing a semiconductor device 200 according to the first modification.

  In the example of the semiconductor device 100 described above, the fuse elements 40 a, 40 b, and 40 c are formed apart from the base layer 11. On the other hand, in the semiconductor device 200, as shown in FIG. 9, fuse elements 40 a, 40 b, and 40 c are formed on the base layer 11. In the semiconductor device 200, since the fuse elements 40a, 40b, and 40c are supported by the base layer 11, compared with the example of the semiconductor device 100, it is more resistant to impact and can improve reliability.

  The material of the fuse elements 40a, 40b, and 40c is the same material as that of the conductive layer constituting the first surrounding wall 30a. That is, the material of the fuse elements 40a, 40b, and 40c is, for example, polycrystalline silicon to which conductivity is imparted by doping a predetermined impurity.

  According to the semiconductor device 200, similarly to the semiconductor device 100, for example, the characteristics of the fuse element can be stabilized as compared with the case where the fuse element is provided in the interlayer insulating layer.

(2) Second Modification Next, a semiconductor device according to a second modification of the present embodiment will be described. FIG. 10 is a plan view schematically showing a semiconductor device 300 according to the second modification. FIG. 11 is a cross-sectional view schematically showing the semiconductor device 300. 11 is a cross-sectional view taken along line XI-XI in FIG. In FIG. 10, for convenience, illustration of the substrate 10, the base layer 11, the interlayer insulating layers 36 a, 36 b, 36 c, the first coating layer 32, the second coating layer 34, and the protective films 50, 52 is omitted.

  As shown in FIGS. 10 and 11, the semiconductor device 200 can have a wall portion 310 that partitions adjacent fuse elements 40a, 40b, and 40c.

  As shown in FIG. 10, the wall portion 310 is formed between adjacent fuse elements 40a, 40b, and 40c. As shown in FIG. 11, the wall portion 310 is formed on the first portion 310a formed on the base layer 11, the second portion 310b formed on the first portion 310a, and the second portion 310b. A third portion 310c. The first portion 310a, the second portion 310b, and the third portion 310c are integrally formed. The height of the wall portion 310 (the distance between the upper surface of the wall portion 310 and the substrate 10) is, for example, equal to or higher than the height of the fuse elements 40a, 40b, and 40c (the distance between the upper surface of the fuse element and the substrate 10). It is.

  The material of the first portion 310a is, for example, polycrystalline silicon imparted with conductivity by being doped with a predetermined impurity, and the material of the second portion 310b and the third portion 310c is, for example, aluminum, copper, Examples thereof include metals such as tungsten and titanium and alloys thereof. The wall part 310 can be formed in the same process as the process of forming the surrounding walls 30a, 30b, 30c, 30d, for example.

  According to the semiconductor device 300, it is possible to have the wall portion 310 that partitions the adjacent fuse elements 40a, 40b, and 40c. Therefore, it is possible to prevent the fused fuse elements 40a, 40b, and 40c from scattering and adhering to other fuse elements. Thereby, a short circuit between fuse elements 40a, 40b, and 40c can be prevented. Furthermore, the wall portion 310 can prevent the covering layers 32 and 34 from being deformed and coming into contact with the fuse elements 40a, 40b and 40c. Since the cavity 20 is in a reduced pressure state, a pressure difference from the outside is generated. For this reason, the coating layers 32 and 34 may be deformed by this pressure difference and come into contact with the fuse elements 40a, 40b and 40c. The wall portion 310 can support the deformed coating layers 32 and 34 to prevent the coating layers 32 and 34 from coming into contact with the fuse elements 40a, 40b, and 40c.

(3) Third Modification Next, a semiconductor device according to a third modification of the present embodiment will be described. FIG. 12 is a cross-sectional view schematically showing a semiconductor device 400 according to the third modification.

  In the semiconductor device 400, as shown in FIG. 12, the second protective film 52 covers the second covering layer. Thereby, the 2nd coating layer 34 can be protected.

(4) Fourth Modification Next, a semiconductor device according to a fourth modification of the present embodiment will be described. FIG. 13 is a cross-sectional view schematically showing a semiconductor device 500 according to the fourth modification.

  In the semiconductor device 500, as shown in FIG. 13, the third protective film 54 covers the second coating layer 34. Thereby, the 2nd coating layer 34 can be protected. The third protective film 54 is formed on the second protective film 52 and the second coating layer 34. The material of the third protective film 54 is, for example, silicon oxide or silicon nitride.

2. Second Embodiment Next, a semiconductor device 600 according to a second embodiment will be described. FIG. 14 is a cross-sectional view schematically showing a semiconductor device 600 according to this embodiment. Hereinafter, in the semiconductor device according to the present embodiment, members having the same functions as those of the constituent members of the semiconductor device 100 are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 14, the semiconductor device 600 includes a substrate 10, a cavity 20, a covering structure 30, fuse elements 40 a, 40 b, 40 c, protective films 50, 52, and a functional element 60. .

  As shown in FIG. 14, the functional element 60 is accommodated in a cavity 20 that is different from the cavity 20 in which the fuse elements 40a, 40b, and 40c are accommodated. Although not shown, three functional elements 60 are accommodated in the cavity 20 and are electrically connected to the corresponding fuse elements 40a, 40b, and 40c, respectively.

  The semiconductor device 600 can constitute, for example, an oscillator. In the semiconductor device 600, the fuse elements 40a, 40b, and 40c function as a selection unit for selecting the functional element (vibrator) 60. For example, in an oscillator incorporating a semiconductor device 600 including three functional elements 60 having different natural frequencies, these functional elements 60 can be selected by the fuse elements 40a, 40b, and 40c. Can be output. For example, in an oscillator incorporating a semiconductor device 600 including three functional elements 60 having natural frequencies close to a desired frequency, these functional elements 60 can be selected by the fuse elements 40a, 40b, and 40c. Therefore, a frequency closer to the desired frequency can be obtained. Therefore, an oscillator with high frequency accuracy can be obtained. The number of functional elements 60 is not limited as long as it has a plurality of fuse elements respectively corresponding to the plurality of functional elements.

  The functional element 60 is a vibrator that includes a fixed electrode 62 formed on the base layer 11 and a movable electrode 64 formed with a fixed interval from the fixed electrode 62. The movable electrode 64 includes a fixed portion 64 a formed on the base layer 11, a movable portion (beam) 64 b that can be vibrated disposed opposite to the fixed electrode 62, and the movable portion 64 b and the fixed portion 64 a. And a support portion 64c to be supported. When a voltage is applied between the electrodes 62 and 64 from an external oscillation circuit unit (not shown), the movable electrode 64 vibrates due to an electrostatic force generated between the electrodes 62 and 64. The fixed electrode 62 is electrically connected to the corresponding fuse elements 40a, 40b, and 40c through, for example, wiring (not shown). The functional element 60 is connected to an external oscillation circuit unit. The oscillation circuit unit may be formed on the substrate 10. Examples of the material of the fixed electrode 62 and the movable electrode 64 include polycrystalline silicon to which conductivity is imparted by doping with a predetermined impurity.

  The functional element 60 may be various functional elements such as a crystal resonator, a SAW (surface acoustic wave) element, an acceleration sensor, a gyroscope, and a microactuator other than the above-described vibrator. That is, the semiconductor device according to the present embodiment may be any device including any functional element that can be accommodated in the cavity 20.

  In the semiconductor device 600, as in the semiconductor device 100, for example, the characteristics of the fuse element can be stabilized as compared with the case where the fuse element is provided in the interlayer insulating layer.

  In addition, embodiment mentioned above and a modification are examples, Comprising: It is not necessarily limited to these. For example, it is possible to combine the embodiment and each modification as appropriate.

  Although the embodiments of the present invention have been described in detail as described above, those skilled in the art will readily understand that many modifications are possible without substantially departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention.

10 substrate, 11 foundation layer, 20 cavity, 30 covering structure, 30a first surrounding wall,
30b 2nd surrounding wall, 30c 3rd surrounding wall, 30d 4th surrounding wall, 32 1st coating layer,
33 through hole, 34 second covering layer, 36a first interlayer insulating layer, 36b second interlayer insulating layer,
36c third interlayer insulating layer, 40a first fuse element, 40b second fuse element,
40c 3rd fuse element, 42 wiring, 46 1st layer, 48 2nd layer,
50 1st protective film, 52 2nd protective film, 54 3rd protective film, 60 functional element,
62 fixed electrode, 64 movable electrode, 64a fixed part, 64b movable part, 64c support part,
100, 200, 300 semiconductor device, 310 wall, 310a first part,
310b Second part, 310c Third part, 400, 500, 600 Semiconductor device

Claims (6)

A substrate,
A covering structure formed above the substrate and defining a cavity;
A fuse element housed in the cavity,
Including
The covering structure has a conductive layer;
A semiconductor device, wherein the material of the fuse element is the same as the material of the conductive layer. In claim 1,
A semiconductor device, wherein a plurality of the fuse elements are accommodated in the cavity. In claim 2,
Furthermore, the semiconductor device including the wall part which partitions off between the said adjacent fuse elements. In any one of Claims 1 thru | or 3,
The semiconductor device, wherein the cavity is in a reduced pressure state. In any one of Claims 1 thru | or 4,
The semiconductor device, wherein the fuse element is separated from the substrate. In any one of Claims 1 thru | or 5,
The semiconductor device, wherein the conductive layer surrounds the cavity in a plan view.

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