JP2014073551A - Electronic apparatus and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic apparatus capable of inhibiting a coating layer for sealing a cavity part, in which a function element is disposed, from falling in.SOLUTION: An electronic apparatus 100 includes: a substrate 10; a function element 20 formed above the substrate 10; a first insulation layer 50 which is formed around a cavity part 2 for storing the function element 20; a second insulation layer 90 formed above the first insulation layer 50; a first coating layer 70 which defines an upper surface of the cavity part 2, the first coating layer 70 in which a through hole 71 which allows the cavity part 2 to communicate with the exterior is formed; a second coating layer 72 which is formed on the second insulation layer 90 and the first coating layer 70 and seals the through hole 71; and a wiring layer 40 formed on the second insulation layer 90.

Description

  The present invention relates to an electronic device and a method for manufacturing the electronic device.

  MEMS (Micro Electro Mechanical Systems) is one of micro structure forming techniques, and refers to, for example, a technique for producing a micro electro-mechanical system of micron order and its product.

  In recent years, MEMS vibrators manufactured using MEMS technology have attracted attention. In particular, development of a technique for forming a MEMS vibrator and a semiconductor element such as a CMOS transistor on the same substrate with a common manufacturing process is underway (see, for example, Patent Document 1).

  In an electronic apparatus including such a functional element such as a MEMS vibrator and a semiconductor element, for example, as disclosed in Patent Document 2, the functional element is accommodated in a reduced pressure state in a cavity. Specifically, in Patent Document 2, a first covering layer that covers a cavity from above and has a through hole, and a covering structure that has a second covering layer that is formed on the first covering layer and seals the through hole. A cavity is defined, and the functional element is accommodated in the cavity. The two coating layers of the first coating layer and the second coating layer function as a sealing member for sealing the cavity. Patent Document 2 describes that the thickness of the second coating layer is as thick as 3 μm.

JP 2008-153817 A JP 2012-96316 A

  However, when the through hole is closed with a thick second coating layer as in the electronic device disclosed in Patent Document 2, a convex portion is formed on the surface of the electronic device (chip) by the second coating layer. . In such an electronic device, for example, when the second coating layer side is mounted on the mounting substrate (face-down mounting) or when the electronic device is mounted over another chip, the second coating layer is pressed. In some cases, pressure is applied and the second coating layer is depressed. When the second coating layer is depressed, there may be a problem that the degree of vacuum in the cavity portion is lowered, or a problem that the first coating layer and the functional element come into contact with each other.

  One of the objects according to some aspects of the present invention is to provide an electronic device and a method for manufacturing the same that can suppress the depression of a coating layer for sealing a cavity in which a functional element is disposed. There is.

An electronic device according to the present invention includes:
A substrate,
A functional element formed above the substrate;
A first insulating layer formed around a cavity that accommodates the functional element;
A second insulating layer formed above the first insulating layer;
A first coating layer that defines an upper surface of the cavity and has a through-hole that allows the cavity to communicate with the outside;
A second coating layer formed on the second insulating layer and the first coating layer and sealing the through hole;
A wiring layer formed on the second insulating layer;
including.

  According to such an electronic device, the second covering layer and the wiring layer are both formed on the second insulating layer. Thereby, the pressure applied to the second coating layer at the time of mounting can be reduced by the wiring layer, and the depression of the second coating layer can be suppressed. Therefore, for example, it is possible to prevent the problem that the second covering layer is depressed and the degree of vacuum is lowered, and the problem that the first covering layer is in contact with the functional element are prevented.

  In the description according to the present invention, the word “upper” is used, for example, “specifically” (hereinafter referred to as “A”) is formed above another specific thing (hereinafter referred to as “B”). The word “above” is used to include the case where B is formed directly on A and the case where B is formed on A via another object. Used.

In the electronic device according to the present invention,
The film thickness of the wiring layer and the film thickness of the second coating layer may be the same.

  According to such an electronic device, the pressure applied to the second coating layer can be more reliably reduced by the wiring layer. Therefore, it can suppress more reliably that a 2nd coating layer sinks.

In the electronic device according to the present invention,
The wiring layer may constitute an inductor element.

  According to such an electronic device, the loss in the inductor element can be reduced while simplifying the manufacturing process.

In the electronic device according to the present invention,
The thickness of the wiring layer may be larger than the thickness of other wiring layers formed on the first insulating layer.

  According to such an electronic device, the resistance of the wiring layer formed on the second insulating layer can be made smaller than the resistance of the other wiring layers. Therefore, for example, the wiring layer can be used as a wiring for flowing a larger current than other wiring layers.

In the electronic device according to the present invention,
The second covering layer and the wiring layer may be formed using the same metal layer.

  According to such an electronic device, since the second covering layer and the wiring layer can be formed in the same process, the manufacturing process can be simplified.

In the electronic device according to the present invention,
A protective film covering the second covering layer and the wiring layer may be included.

  According to such an electronic device, the second covering layer and the wiring layer can be protected, and the reliability can be improved.

An electronic device manufacturing method according to the present invention includes:
Forming a functional element above the substrate;
Forming a first insulating layer so as to cover the functional element;
Forming a first covering layer above the first insulating layer;
Forming a through hole in the first coating layer;
Forming a second insulating layer above the first insulating layer;
Removing the first insulating layer above the functional element through the through hole to form a cavity;
Forming a metal layer on the second insulating layer and the first covering layer, sealing the through hole, and forming a wiring layer on the second insulating layer;
including.

  According to such an electronic device, since the second covering layer and the wiring layer can be formed using the same metal layer, the manufacturing process can be simplified. Furthermore, since both the second covering layer and the wiring layer can be formed on the second insulating layer, the pressure applied to the second covering layer during mounting can be reduced by the wiring layer, and the second covering layer is depressed. Can be suppressed.

In the method for manufacturing an electronic device according to the present invention,
In the step of forming the second covering layer and the wiring layer, the wiring layer may be formed to constitute an inductor element.

  According to such an electronic device, since the inductor element can be formed of the same metal layer as the second coating layer, the manufacturing process can be simplified.

FIG. 3 is a cross-sectional view schematically showing the electronic device according to the first embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on 1st Embodiment. Sectional drawing which shows typically the electronic device which concerns on the modification of 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on the modification of 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on the modification of 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on the modification of 1st Embodiment. Sectional drawing which shows the electronic device which concerns on 2nd Embodiment typically. The circuit diagram which shows the electronic device which concerns on 3rd Embodiment. The circuit diagram which shows the electronic device which concerns on the modification of 3rd Embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, not all of the configurations described below are essential constituent requirements of the present invention.

1. 1. First embodiment 1.1. Electronic Device First, an electronic device according to a first embodiment will be described with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing an electronic device 100 according to the first embodiment.

  As shown in FIG. 1, the electronic device 100 includes a substrate 10, a functional element 20, a wiring layer 40, a first insulating layer (hereinafter also referred to as “interlayer insulating layer”) 50, coating layers 70 and 72, A second insulating layer (hereinafter also referred to as “protective film”) 90. Further, the electronic device 100 can include a first foundation layer 12, a second foundation layer 14, a transistor 30, an enclosure wall 60, and wiring layers (other wiring layers) 80 and 82.

  For example, a semiconductor substrate such as a silicon substrate is used as the substrate 10. As the substrate 10, various substrates such as a ceramic substrate, a glass substrate, a sapphire substrate, a diamond substrate, and a synthetic resin substrate may be used. Above the substrate 10, a functional element 20 and a circuit unit 3 including a transistor 30 are formed. That is, the functional element 20 and the circuit unit 3 are formed on the same substrate 10.

  The first foundation layer 12 is formed on the substrate 10. The first underlayer 12 is, for example, a LOCOS (local oxidation of silicon) insulating layer, a semi-recessed LOCOS insulating layer, or a trench insulating layer. The first underlayer 12 can electrically separate the transistor 30 and the functional element 20.

  The second underlayer 14 is formed on the first underlayer 12. The second foundation layer 14 is, for example, a silicon nitride layer. The second underlayer 14 can function as an etching stopper layer in a release process described later.

  The functional element 20 is formed on the second underlayer 14 (above the substrate 10). The functional element 20 is accommodated (arranged) in the cavity 2 in the illustrated example. The functional element 20 is, for example, a cantilever type MEMS vibrator. In the illustrated example, the functional element 20 has a static gap between the first electrode 22 and a gap between the first electrode 22 formed on the second underlayer 14 and the first electrode 22. And a second electrode 24 formed to be able to vibrate by electric power.

  The first electrode 22 is a flat member. The planar shape of the first electrode 22 (the shape seen from the thickness direction of the substrate 10) is, for example, a rectangle. The planar shape of the first electrode 22 is not limited to a rectangle, and may be a polygon other than a rectangle.

  The second electrode 24 is formed with a predetermined distance from the first electrode 22. The second electrode 24 includes a support part 24 a formed on the second underlayer 14, and a beam part 24 b extending from the support part 24 a and facing the first electrode 22. The planar shape of the beam part 24b is not specifically limited, For example, it is a rectangle. The material of the first electrode 22 and the second electrode 24 is, for example, polycrystalline silicon provided with conductivity by doping a predetermined impurity (for example, boron).

  In the functional element 20, when a voltage (alternating voltage) is applied between the first electrode 22 and the second electrode 24, the beam portion 24 b causes the electrostatic force generated between the electrodes 22 and 24 to generate a thickness direction of the substrate 10. Vibrate.

The functional element 20 is not limited to the illustrated example, and may be, for example, a double-supported beam type MEMS vibrator in which both ends of the beam portion are fixed. In addition, the functional element 20 includes a first electrode portion and a second beam portion in which the second electrode includes a support portion, and a first beam portion and a second beam portion that extend in opposite directions from the support portion. A MEMS vibrator in which a first electrode is formed opposite to each of the first and second electrodes may be used. Further, the functional element 20 may be various functional elements such as a quartz crystal vibrator, a SAW (surface acoustic wave) element, an acceleration sensor, a gyro sensor, and a microactuator other than the MEMS vibrator. As described above, the electronic device 100 can include an arbitrary functional element that can be accommodated in the cavity 2.

  The cavity 2 is a space for accommodating the functional element 20. The cavity 2 is formed on the second underlayer 14 (above the substrate 10), and the functional element 20 is disposed therein. In the illustrated example, the cavity 2 is defined (defined) by the second underlayer 14, the surrounding wall 60, and the covering layers 70 and 72. The inside of the cavity 2 is in a reduced pressure state, for example. Thereby, the operational accuracy of the functional element 20 can be improved. Although not shown, the cavity 2 may be further defined by the interlayer insulating layer 50.

  For example, the circuit unit 3 includes an operation circuit of the electronic device 100. In the electronic device 100, for example, the circuit unit 3 and the functional element 20 can constitute an oscillation circuit. In the illustrated example, the circuit unit 3 includes a transistor 30 and wiring layers 40, 80, and 82. Although not shown, the circuit unit 3 may be configured to include other elements (for example, capacitors) and other wirings.

  The transistor 30 is formed on the substrate 10. In the illustrated example, the transistor 30 is formed in a region of the substrate 10 where the first underlayer 12 is not formed. The transistor 30 is a MOS transistor having a gate insulating film 32, a gate electrode 34, a source region 36, a drain region 37, and a sidewall 38.

  The gate insulating film 32 is formed on the substrate 10. The gate insulating film 32 is made of, for example, a silicon oxide layer. A part of the gate insulating film 32 is sandwiched between the substrate 10 and the gate electrode 34. The gate electrode 34 is formed on the gate insulating film 32. The material of the gate electrode 34 is, for example, polycrystalline silicon imparted with conductivity by doping a predetermined impurity. The source region 36 and the drain region 37 are formed in the substrate 10. The source region 36 and the drain region 37 are formed by doping the substrate 10 with a predetermined impurity. The sidewall 38 is formed on the side of the gate electrode 34. The material of the sidewall 38 is, for example, silicon oxide.

  The first wiring layer 80 is formed on the first interlayer insulating layer 52. Further, the first wiring layer 80 is formed in the through hole 51 provided in the first interlayer insulating layer 52 and connected to the source region 36 or the drain region 37. The first wiring layer 80 is a wiring for connecting the source region 36 or the drain region 37 and the second wiring layer 82.

  The second wiring layer 82 is formed on the second interlayer insulating layer 54. Further, the second wiring layer 82 is formed in the through hole 53 provided in the second interlayer insulating layer 54 and connected to the first wiring layer 80. The second wiring layer 82 is a wiring for connecting the first wiring layer 80 and the third wiring layer 40.

  The third wiring layer 40 is formed on the protective film 90. The third wiring layer 40 is formed on the second protective film 94 in the illustrated example. Further, the third wiring layer 40 is formed in the through hole 91 that penetrates the protective film 90 (the first protective film 92 and the second protective film 94), and is connected to the second wiring layer 82. The third wiring layer 40 is, for example, wiring for connecting the second wiring layer 82 and another element (not shown).

The third wiring layer 40 and the second covering layer 72 are both formed on the protective film 90. The third wiring layer 40 and the second coating layer 72 are formed in the uppermost layer among the wiring layers constituting the electronic device 100. That is, the third wiring layer 40 and the second covering layer 72 are configured by a wiring layer (metal layer) that is farthest from the substrate 10.

  The third wiring layer 40 and the second covering layer 72 are formed using the same metal layer 8 (see FIG. 9). Specifically, the third wiring layer 40 and the second covering layer 72 are formed by forming the metal layer 8 on the protective film 90 and the first covering layer 70 and patterning the formed metal layer 8. ,It is formed. Therefore, the film thickness t1 of the third wiring layer 40 is the same as the film thickness t2 of the second coating layer 72. The film thickness t 1 of the third wiring layer 40 is the film thickness of the third wiring layer 40 on the protective film 90. The film thickness t2 of the second coating layer 72 is the film thickness of the second coating layer 72 on the protective film 90. The third wiring layer 40 is thicker than the other wiring layers 80 and 82 formed on the first interlayer insulating layer 52 and the second interlayer insulating layer 54. Therefore, the third wiring layer 40 can flow a larger current than the other wiring layers 80 and 82. The third wiring layer 40 can be used, for example, as a wiring for flowing a large current. For example, the third wiring layer 40 may be used as a high-frequency wiring. The film thickness t1 of the third wiring layer 40 is, for example, about 3 μm. The film thicknesses of the other wiring layers 80 and 82 are, for example, about 0.5 to 1 μm.

  Although not shown, the film thickness t1 of the third wiring layer 40 and the film thickness t2 of the second coating layer 72 may be different. The film thickness t1 of the third wiring layer 40 may be larger than the film thickness t2 of the second coating layer 72, and the film thickness t1 of the third wiring layer 40 is larger than the film thickness t2 of the second coating layer 72. May be thin.

  As the wiring layers 80, 82, 40, for example, an aluminum layer, a titanium layer, or a laminate of an aluminum layer and a titanium layer can be used.

  The interlayer insulating layer 50 is formed above the substrate 10. The interlayer insulating layer 50 is formed around the cavity 2. A first cover layer 70 is formed on the interlayer insulating layer 50. In the illustrated example, a second wiring layer 82 is further formed on the interlayer insulating layer 50. In the illustrated example, the interlayer insulating layer 50 is composed of two layers, a first interlayer insulating layer 52 and a second interlayer insulating layer 54. The interlayer insulating layer 50 may be a single layer or may be composed of three or more layers.

  The first interlayer insulating layer 52 is formed on the first base layer 12, the second base layer 14, and the gate insulating film 32 (above the substrate 10). A first wiring layer 80 and a second conductive layer 64 are formed on the first interlayer insulating layer 52. That is, the first wiring layer 80 and the second conductive layer 64 are formed in the same layer.

  The second interlayer insulating layer 54 is formed on the first interlayer insulating layer 52. A first covering layer 70 (third conductive layer 66) and a second wiring layer 82 are formed on the second interlayer insulating layer 54. That is, the first covering layer 70 (third conductive layer 66) and the second wiring layer 82 are formed in the same layer. The first interlayer insulating layer 52 and the second interlayer insulating layer 54 are, for example, silicon oxide layers.

  The surrounding wall 60 defines the cavity 2. Although not shown, the surrounding wall 60 has a shape surrounding the functional element 20 in plan view. The planar shape of the surrounding wall 60 is not particularly limited, and may be any shape such as a circular shape or a polygonal shape.

  The surrounding wall 60 includes a first conductive layer 62, a second conductive layer 64, and a third conductive layer 66. In the illustrated example, the first conductive layer 62, the second conductive layer 64, and the third conductive layer 66 are stacked in this order from the substrate 10 side. In the illustrated example, the surrounding wall 60 includes three conductive layers 62, 64, 66, but the number is not particularly limited. The number of stacked conductive layers 62, 64, and 66 constituting the surrounding wall 60 can be determined according to the number of stacked layers of the interlayer insulating layer 50, for example.

  The first conductive layer 62 is formed on the second base layer 14. The material of the first conductive layer 62 is, for example, polycrystalline silicon imparted with conductivity by doping a predetermined impurity.

  The second conductive layer 64 is formed on the first conductive layer 62 and the first interlayer insulating layer 52. The third conductive layer 66 is formed on the second conductive layer 64 and the second interlayer insulating layer 54. The second conductive layer 64 and the third conductive layer 66 are, for example, an aluminum layer, a titanium layer, or a stacked body of an aluminum layer and a titanium layer.

  The first covering layer 70 is formed so as to cover the cavity 2 from above. The first covering layer 70 defines the upper surface of the cavity 2. The first coating layer 70 is provided with a through-hole 71 that allows communication between the cavity 2 and the outside (outside the cavity 2). The through hole 71 extends from the upper surface to the lower surface of the first coating layer 70. In the illustrated example, three through holes 71 are provided, but the number is not limited. As will be described later, an etching solution or an etching gas can be supplied through the through hole 71 in the release process for forming the cavity 2. The first covering layer 70 is provided integrally with the third conductive layer 66. The film thickness of the 1st coating layer 70 is about 0.5-1 micrometer, for example.

  The second coating layer 72 is formed on the first coating layer 70 and the protective film 90. The second coating layer 72 closes the through hole 71 formed in the first coating layer 70. Thereby, it is possible to prevent gas or the like from entering the cavity 2 from the outside through the through hole 71. The second coating layer 72 is, for example, an aluminum layer, a titanium layer, or a stacked body of an aluminum layer and a titanium layer. The first coating layer 70 and the second coating layer 72 can function as a sealing member that covers the cavity 2 from above and seals the cavity 2. The film thickness t2 of the second coating layer 72 is 3 μm, for example. That is, the film thickness t <b> 2 of the second coating layer 72 is larger than the film thickness of the first coating layer 70. In the electronic device 100, two coating layers 70 and 72 that define the cavity 2 are provided.

  It is desirable that a constant potential (for example, ground potential) is applied to the surrounding wall 60 and the first covering layer 70. Thereby, the surrounding wall 60 and the 1st coating layer 70 can be functioned as an electromagnetic shield. Therefore, the functional element 20 can be electrically shielded from the outside.

  The protective film 90 is provided on the interlayer insulating layer 50. In the illustrated example, the protective film 90 is formed on the interlayer insulating layer 50 (second interlayer insulating layer 54), the second wiring layer 82, and the third conductive layer 66 (first covering layer 70). . In the illustrated example, the protective film 90 is formed in the uppermost layer (the layer farthest from the substrate 10) among the insulating layers constituting the electronic device 100. On the protective film 90, the third wiring layer 40 and the second covering layer 72 are formed. That is, the third wiring layer 40 and the second covering layer 72 are formed in the same layer. In the illustrated example, the protective film 90 includes two layers, a first protective film 92 and a second protective film 94. The number of layers of the protective film 90 is not limited to this, and may be one layer or three or more layers. The protective film 90 is formed so as to avoid the region where the through hole 71 of the first coating layer 70 is formed. A through hole 91 is formed in the protective film 90. The through hole 91 extends from the lower surface of the first protective film 92 to the upper surface of the second protective film 94. A third wiring layer 40 is formed in the through hole 91.

The first protective film 92 is formed on the interlayer insulating layer 50. In the illustrated example, the first protective film 92 is formed on the interlayer insulating layer 50 (second interlayer insulating layer 54), the second wiring layer 82, and the third conductive layer 66 (first covering layer 70). ing. The second protective film 94 is formed on the first protective film 92. The first protective film 92 and the second protective film 94 are, for example, silicon nitride layers.

  The electronic device 100 according to the present embodiment has the following features, for example.

  The electronic device 100 is configured to include a second coating layer 72 formed on the protective film 90 and the first coating layer 70, and a third wiring layer 40 formed on the protective film 90. That is, both the second covering layer 72 and the third wiring layer 40 are formed on the protective film 90. Thereby, the pressure applied to the second coating layer 72 at the time of mounting can be reduced by the third wiring layer 40, and the depression of the coating layers 70 and 72 can be suppressed. Therefore, for example, it is possible to prevent the problem that the coating layers 70 and 72 are depressed and the degree of vacuum is lowered, and the problem that the first coating layer 70 and the functional element 20 are in contact with each other.

  For example, when the third wiring layer 40 is not formed on the protective film 90, the second coating layer 72 causes a convex portion on the surface of the electronic device 100. In such an electronic device, for example, when the second coating layer 72 side is mounted on the mounting substrate (face-down mounting), or when the electronic device 100 is mounted over another chip, the second coating layer 72 is used. May be pressed to apply pressure and the second coating layer 72 may be depressed. When the second coating layer 72 is depressed, there may be a problem that the degree of vacuum in the cavity 2 is lowered or a problem that the first coating layer 70 and the functional element 20 are in contact with each other. According to the electronic device 100, since the third wiring layer 40 is formed on the protective film 90 in addition to the second coating layer 72, the second coating layer 72 and the third wiring layer 40 form the surface of the electronic device 100. A convex part can be formed. Therefore, the pressure applied to the second coating layer 72 at the time of mounting can be reduced by the third wiring layer 40, and the depression of the second coating layer 72 can be suppressed. Further, since the third wiring layer 40 is formed on the protective film 90 in addition to the second coating layer 72, for example, when a resin layer (not shown) is formed on the surface of the electronic device 100 during mounting, The surrounding area of the resin layer can be improved.

  Furthermore, in the electronic device 100, since the film thickness of the third wiring layer 40 and the film thickness of the second coating layer 72 are the same, the pressure applied to the second coating layer 72 during mounting is applied by the third wiring layer 40. It can reduce more reliably.

  According to the electronic device 100, the third wiring layer 40 and the second covering layer 72 are both formed on the protective film 90 and can have the same film thickness. Therefore, the third wiring layer 40 and the second covering layer 72 can be formed using the same metal layer 8 (see FIG. 9).

  Here, in the manufacturing process of the electronic device 100, the second covering layer 72 is, for example, after the step of forming the protective film 90 in the manufacturing process of the electronic device 100, that is, the functional element 20, the transistor 30, and the interlayer insulating layer 50. These are formed in the final step after the surrounding wall 60, the first covering layer 70, the wiring layers 80 and 82, and the protective film 90 are formed. Thereby, after sealing the functional element 20 in the cavity part 2, it can suppress that gas is generated in the cavity part 2 by processing heat, and the vacuum degree in the cavity part 2 can be stabilized. Therefore, the characteristics of the functional element 20 can be stabilized.

  Further, the third wiring layer 40 may be formed at a position away from the substrate 10 in order to reduce the possibility of causing a malfunction by giving noise to the circuit unit 3 including the transistor 30 by electromagnetic induction or the like. desirable. Therefore, the third wiring layer 40 is desirably formed on the protective film 90 of the electronic device 100. Thereby, the circuit part 3 can be operated stably.

According to the electronic device 100, since the third wiring layer 40 and the second coating layer 72 are formed on the protective film 90 using the same metal layer 8, for example, the third wiring layer 40 and the second coating layer 72 are used. Can be formed on the protective film 90 away from the substrate 10 in the final step of the manufacturing process of the electronic device 100. Therefore, in the electronic device 100, the functional element 20 and the circuit unit 3 can be stably operated while simplifying the manufacturing process. Therefore, for example, the yield can be improved and the cost can be reduced.

  In addition, the second coating layer 72 reliably closes the through hole 71 of the first coating layer 70 and withstands the pressure difference between the cavity 2 and the outside, and thus the first coating layer 70 and other wiring layers 80. , 82 is required to be thicker. Further, when a large current is passed through the third wiring layer 40, the third wiring layer 40 needs to have resistance to heat generation and electromigration, and therefore has a larger film thickness than the other wiring layers 80 and 82. Needed. In the electronic device 100, since the second coating layer 72 and the third wiring layer 40 that require a thick film can be formed of the same metal layer 8, the manufacturing process can be simplified efficiently.

  The electronic device 100 includes the functional element 20 and the circuit unit 3 formed above the substrate 10. Therefore, according to the electronic device 100, the functional element 20 and the circuit unit 3 can be integrated into one chip.

1.2. Next, a method for manufacturing an electronic device according to the first embodiment will be described with reference to the drawings. 2-9 is sectional drawing which shows typically the manufacturing process of the electronic device 100 which concerns on 1st Embodiment.

  As shown in FIG. 2, the first underlayer 12 is formed on the substrate 10. The first underlayer 12 is formed by, for example, a LOCOS method or an STI (shallow trench isolation) method.

  Next, the second underlayer 14 is formed on the first underlayer 12. The second underlayer 14 is formed by, for example, forming a film by a CVD (Chemical Vapor Deposition) method or a sputtering method, and then patterning the film by a photolithography technique and an etching technique.

  As shown in FIG. 3, the first electrode 22 is formed on the second underlayer 14. The first electrode 22 is formed by being patterned by a CVD method or a sputtering method and then patterned by a photolithography technique and an etching technique. When the first electrode 22 is made of polycrystalline silicon, a predetermined impurity is doped in order to impart conductivity.

  Next, the sacrificial layer 4 and the gate insulating film 32 are formed. The sacrificial layer 4 is formed so as to cover the first electrode 22. The gate insulating film 32 is formed on the substrate 10 on which the first foundation layer 12 is not formed. The sacrificial layer 4 and the gate insulating film 32 are, for example, silicon oxide layers. The sacrificial layer 4 is formed by thermally oxidizing the first electrode 22. The gate insulating film 32 is formed by thermally oxidizing the substrate 10. The thermal oxidation treatment of the first electrode 22 and the gate insulating film 32 is performed at a temperature of 800 ° C. or higher and 1100 ° C. or lower, for example. In this step, the first electrode 22 and the gate insulating film 32 can be formed in the same step. The thickness of the sacrificial layer 4 and the thickness of the gate insulating film 32 can be controlled by adjusting the crystallinity and impurity concentration of the first electrode 22 and the substrate 10. 32 may be formed using a CVD method or a sputtering method.

As shown in FIG. 4, the second electrode 24, the first conductive layer 62, and the gate electrode 34 are formed. The second electrode 24 is formed on the sacrificial layer 4 and the second underlayer 14. The first conductive layer 62 is
It is formed on the second underlayer 14. The gate electrode 34 is formed on the gate insulating film 32. The second electrode 24, the first conductive layer 62, and the gate electrode 34 are formed by being formed by a CVD method, a sputtering method, or the like and then patterned by a photolithography technique and an etching technique. In the case where the second electrode 24, the first conductive layer 62, and the gate electrode 34 are made of polycrystalline silicon, a predetermined impurity is doped to impart conductivity. In this step, the second electrode 24, the first conductive layer 62, and the gate electrode 34 can be formed in the same step. In this step, the functional element 20 can be formed on the second underlayer 14 (above the substrate 10). The first conductive layer 62 may be formed in the same process as the first electrode 22 without being formed in the same process as the second electrode 24 and the gate electrode 34.

  Next, a predetermined impurity is implanted into the region of the substrate 10 where the first underlayer 12 is not formed using the gate electrode 34 as a mask. Next, a sidewall 38 is formed on the side of the gate electrode 34. The sidewall 38 is formed by a known method. Next, using the sidewall 38 as a mask, a predetermined impurity is implanted to form a source region 36 and a drain region 37. By this step, impurities are added at a high concentration. Thereby, an LDD (Lightly Doped Drain) structure can be formed. In this step, the transistor 30 can be formed.

  As shown in FIG. 5, a first interlayer insulating layer 52 is formed over the substrate 10 so as to cover the functional element 20, the first conductive layer 62, and the transistor 30. The first interlayer insulating layer 52 is formed by, for example, a CVD method or a coating (spin coating) method. After forming the first interlayer insulating layer 52, a process for planarizing the surface of the first interlayer insulating layer 52 may be performed.

  Next, the first interlayer insulating layer 52 is patterned to form the through holes 51 and 51a. The patterning is performed by, for example, a photolithography technique and an etching technique. The through hole 51 is formed so as to expose the source region 36 or the drain region 37. The through hole 51 a is formed so as to expose the first conductive layer 62.

  Next, the first wiring layer 80 and the second conductive layer 64 are formed. The first wiring layer 80 is formed on the first interlayer insulating layer 52 and in the through hole 51. The second conductive layer 64 is formed on the first interlayer insulating layer 52 and in the through hole 51a. The first wiring layer 80 and the second conductive layer 64 are formed by being patterned by a CVD method, a sputtering method, or the like and then patterned by a photolithography technique and an etching technique. In this step, the first wiring layer 80 and the second conductive layer 64 can be formed in the same step.

  As shown in FIG. 6, a second interlayer insulating layer 54 is formed on the first interlayer insulating layer 52 so as to cover the first wiring layer 80 and the second conductive layer 64. The second interlayer insulating layer 54 is formed by, for example, a CVD method or a coating (spin coating) method. After forming the second interlayer insulating layer 54, a process for planarizing the surface of the second interlayer insulating layer 54 may be performed. In this step, an interlayer insulating layer 50 composed of two layers, a first interlayer insulating layer 52 and a second interlayer insulating layer 54 is formed.

  Next, the second interlayer insulating layer 54 is patterned to form the through holes 53 and 53a. The patterning is performed by, for example, a photolithography technique and an etching technique. The through hole 53 is formed so as to expose the first wiring layer 80. The through hole 53a is formed so as to expose the second conductive layer 64.

Next, the second wiring layer 82, the third conductive layer 66, and the first covering layer 70 are formed. The second wiring layer 82 is formed on the second interlayer insulating layer 54 and in the through hole 53. The third conductive layer 66 is formed on the second interlayer insulating layer 54 and in the through hole 53a. The first covering layer 70 is formed on the second interlayer insulating layer 54. The second wiring layer 82, the third conductive layer 66, and the first covering layer 70 are formed by being patterned by a CVD method, a sputtering method, or the like and then patterned by a photolithography technique and an etching technique. In this step, the second wiring layer 82, the third conductive layer 66, and the first covering layer 70 can be formed in the same step. In this step, the surrounding wall 60 is formed.

  Next, the 1st coating layer 70 is patterned and the through-hole 71 is formed. The through hole 71 may be formed at the same time as the step of forming the first coating layer 70. Thereby, simplification of a manufacturing process can be achieved.

  As shown in FIG. 7, a protective film 90 is formed on the interlayer insulating layer 50 (second interlayer insulating layer 54) and on the first covering layer 70 (third conductive layer 66). Specifically, first, the first protective film 92 is formed on the second interlayer insulating layer 54, the second wiring layer 82, and the first covering layer 70 (third conductive layer 66). Next, a second protective film 94 is formed on the first protective film 92. The first protective film 92 and the second protective film 94 are formed by being patterned by a CVD method or a sputtering method and then patterned by a photolithography technique and an etching technique. A through hole 91 and an opening 93 are formed in the protective film 90. The through hole 91 is formed so that the second wiring layer 82 is exposed. The opening 93 is formed so as to communicate with the through hole 71 of the first coating layer 70. By forming the opening 93, the protective film 90 is formed avoiding the through hole 71. That is, the protective film 90 is formed so as not to block the through hole 71.

  As shown in FIG. 8, the interlayer insulating layer 50 and the sacrificial layer 4 above the functional element 20 are removed by passing an etching solution or etching gas through the through-hole 71 to form the cavity 2 (release process). The release process is performed, for example, by wet etching using hydrofluoric acid or buffered hydrofluoric acid (mixed liquid of hydrofluoric acid and ammonium fluoride), dry etching using a hydrogen fluoride-based gas, or the like. . By forming the surrounding wall 60 and the first covering layer 70 from a material that is not etched in the release process, the cavity 2 can be prevented from spreading to the outside of the surrounding wall 60. The second underlayer 14 can function as an etching stopper layer. In the release process, the sacrificial layer 4 is removed, whereby a gap (gap) is formed between the first electrode 22 and the second electrode 24 of the functional element 20.

  As shown in FIG. 9, the metal layer 8 is formed on the protective film 90, the first coating layer 70, the through hole 91, and the opening 93. The metal layer 8 is, for example, an aluminum layer, a titanium layer, or a stacked body of an aluminum layer and a titanium layer. The metal layer 8 can be formed by, for example, a vapor phase growth method such as a CVD method or a sputtering method. Thereby, the cavity 2 can be sealed in a reduced pressure state.

  As shown in FIG. 1, the metal layer 8 is patterned. As a result, the second coating layer 72 is formed on the protective film 90 and the first coating layer 70, and the third wiring layer 40 is formed on the protective film 90 and in the through hole 91. That is, the second covering layer 72 and the third wiring layer 40 are formed using the metal layer 8. The patterning of the metal layer 8 is performed by a photolithography technique and an etching technique. In this step, the second covering layer 72 and the third wiring layer 40 can be formed in the same step.

  Through the above steps, the electronic device 100 can be manufactured.

  The method for manufacturing the electronic device 100 according to this embodiment has the following features, for example.

In the method for manufacturing the electronic device 100 according to the present embodiment, the metal layer 8 is formed on the protective film 90 and the first coating layer 70 to seal the through hole 71 of the first coating layer 70. 72 and a step of forming the third wiring layer 40 on the protective film 90. Thereby, the 2nd coating layer 72 and the 3rd wiring layer 40 can be formed in the same process. Therefore, according to the method for manufacturing the electronic device 100 according to the present embodiment, the manufacturing process can be simplified. Therefore, for example, cost reduction can be achieved. Furthermore, since both the second covering layer 72 and the third wiring layer 40 can be formed on the protective film 90, the pressure applied to the second covering layer 72 during mounting can be reduced by the third wiring layer 40. It is possible to suppress the second coating layer 72 from sinking.

  In the method for manufacturing the electronic device 100 according to the present embodiment, the electronic device 100 including the functional element 20 and the circuit unit 3 formed above the substrate 10 can be obtained. Therefore, the electronic device 100 in which the functional element 20 and the circuit unit 3 can be integrated into one chip can be obtained.

1.3. Modification of Electronic Device Next, a modification of the electronic device according to the first embodiment will be described with reference to the drawings. FIG. 10 is a cross-sectional view schematically showing an electronic device 200 according to a modification of the first embodiment. Hereinafter, in the electronic device 200 according to this modification, members having the same functions as those of the components of the electronic device 100 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the example of the electronic device 100 described above, the second coating layer 72 and the third wiring layer 40 are formed on the protective film 90 as shown in FIG.

  On the other hand, in the electronic device 200, as shown in FIG. 10, the second covering layer 72 and the third wiring layer 40 are formed on the interlayer insulating layer (first insulating layer) 50. It is formed on (second insulating layer) 56. Further, in the electronic device 200, the second covering layer 72 and the third wiring layer 40 are covered with the protective film 210.

  The third interlayer insulating layer 56 is formed on the second interlayer insulating layer 54. In the illustrated example, the third interlayer insulating layer 56 is formed on the second interlayer insulating layer 54, the first covering layer 70 (third conductive layer 66), and the second wiring layer 82. A through hole 57 is formed in the third interlayer insulating layer 56. A third wiring layer 40 is formed in the through hole 57. In the illustrated example, the third wiring layer 40 is formed on the third interlayer insulating layer 56 and in the through hole 57. The third interlayer insulating layer 56 is formed avoiding the through hole 71 of the first coating layer 70. On the third interlayer insulating layer 56, a second covering layer 72, a third wiring layer 40, and a protective film 210 are formed. The third interlayer insulating layer 56 is, for example, a silicon oxide layer.

  The protective film 210 is formed so as to cover the second coating layer 72 and the third wiring layer 40. The protective film 210 is formed on the third interlayer insulating layer 56, the second covering layer 72, and the third wiring layer 40. The protective film 210 is a film for protecting the second coating layer 72 and the third wiring layer 40. The protective film 210 is, for example, a TEOS (tetraethoxysilane) layer or a silicon nitride layer.

  The electronic device 200 according to this modification has the following features, for example.

The electronic device 200 includes a second coating layer 72 formed on the third interlayer insulating layer 56 and the first coating layer 70, and a third wiring layer 40 formed on the third interlayer insulating layer 56. It consists of That is, the second covering layer 72 and the third wiring layer 40 are both formed on the third interlayer insulating layer 56. Thereby, the pressure applied to the second coating layer 72 at the time of mounting can be reduced by the third wiring layer 40, and the depression of the coating layers 70 and 72 can be suppressed. Therefore, for example, it is possible to prevent the problem that the coating layers 70 and 72 are depressed and the degree of vacuum is lowered, and the problem that the first coating layer 70 and the functional element 20 are in contact with each other.

  The electronic device 200 can include a protective film 210 that covers the second coating layer 72 and the third wiring layer 40. Thereby, the 2nd coating layer 72 and the 3rd wiring layer 40 can be protected, and reliability can be improved.

  Next, a method for manufacturing the electronic device 200 according to this modification will be described with reference to the drawings. 11 to 13 are cross-sectional views schematically showing manufacturing steps of the electronic device 200 according to this modification. Hereinafter, in the method for manufacturing the electronic device 200 according to the present modification, differences from the example of the method for manufacturing the electronic device 100 according to the first embodiment described above will be described, and description of similar points will be omitted.

  In the method for manufacturing the electronic device 200 according to the present modification, steps until the second wiring layer 82, the third conductive layer 66, and the first covering layer 70 shown in FIG. 6 are formed (steps shown in FIGS. 2 to 6). ) Is the same as the manufacturing process of the electronic device 100 according to the first embodiment described above. Therefore, the description is omitted.

  As shown in FIG. 11, a third interlayer insulating layer 56 is formed on the second interlayer insulating layer 54 so as to cover the first covering layer 70 and the second wiring layer 82. The third interlayer insulating layer 56 is formed by, for example, a CVD method or a coating (spin coating) method. After the third interlayer insulating layer 56 is formed, a process for planarizing the surface of the third interlayer insulating layer 56 may be performed. A through hole 57 and an opening 58 are formed in the third interlayer insulating layer 56. The through hole 57 is formed so that the second wiring layer 82 is exposed. The opening 58 is formed so as to communicate with the through hole 71 of the first coating layer 70. By forming the opening 58, the third interlayer insulating layer 56 is formed avoiding the through hole 71 of the first covering layer 70.

  As shown in FIG. 12, the first interlayer insulating layer 52, the second interlayer insulating layer 54 and the sacrificial layer 4 above the functional element 20 are removed by passing an etching solution or etching gas through the through hole 71 to form the cavity 2. (Release process) In the release process, the sacrificial layer 4 is removed, whereby a gap (gap) is formed between the first electrode 22 and the second electrode 24 of the functional element 20.

  As shown in FIG. 13, the metal layer 8 is formed on the third interlayer insulating layer 56, the first coating layer 70, the through hole 57, and the opening 58. The metal layer 8 is, for example, an aluminum layer, a titanium layer, or a stacked body of an aluminum layer and a titanium layer. The metal layer 8 can be formed by, for example, a vapor phase growth method such as a CVD method or a sputtering method. Thereby, the cavity 2 can be sealed in a reduced pressure state.

  As shown in FIG. 10, the metal layer 8 is patterned. As a result, the second covering layer 72 is formed on the third interlayer insulating layer 56 and the first covering layer 70, and the third wiring layer 40 is formed on the third interlayer insulating layer 56 and in the through hole 57. That is, the second covering layer 72 and the third wiring layer 40 are formed using the metal layer 8. The patterning of the metal layer 8 is performed by a photolithography technique and an etching technique. In this step, the second covering layer 72 and the third wiring layer 40 can be formed in the same step.

Next, the protective film 210 is formed so as to cover the second coating layer 72 and the third wiring layer 40. The protective film 210 is formed on the third interlayer insulating layer 56, the second covering layer 72, and the third wiring layer 40. The protective film 210 is a film for protecting the second coating layer 72 and the third wiring layer 40. The protective film 210 is formed by, for example, a CVD method or a sputtering method.

  Through the above steps, the electronic device 200 can be manufactured.

  The method for manufacturing the electronic device 200 according to this modification has the following features, for example.

  In the manufacturing method of the electronic device 200 according to this modification, the metal layer 8 is formed on the third interlayer insulating layer 56 and the first covering layer 70, and the through hole 71 of the first covering layer 70 is sealed. A step of forming the third wiring layer 40 on the second covering layer 72 and the third interlayer insulating layer 56. Thereby, the 2nd coating layer 72 and the 3rd wiring layer 40 can be formed in the same process. Therefore, according to the method for manufacturing the electronic device 200 according to the present modification, the manufacturing process can be simplified. Therefore, for example, cost reduction can be achieved. Furthermore, since both the second covering layer 72 and the third wiring layer 40 can be formed on the third interlayer insulating layer 56, the pressure applied to the second covering layer 72 during mounting is reduced by the third wiring layer 40. It can suppress that the 2nd coating layer 72 sinks.

  The method for manufacturing the electronic device 200 according to this modification includes a step of forming the protective film 210 that covers the second coating layer 72 and the third wiring layer 40. Thereby, the 2nd coating layer 72 and the 3rd wiring layer 40 can be protected, and the electronic device 200 with high reliability can be obtained.

2. Second Embodiment 2.1. Electronic Device Next, an electronic device according to a second embodiment will be described with reference to the drawings. FIG. 14 is a cross-sectional view schematically showing an electronic device 300 according to the second embodiment. Hereinafter, in the electronic device 300 according to the second embodiment, members having the same functions as those of the components of the electronic device 100 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the example of the electronic device 100 described above, as illustrated in FIG. 1, the third wiring layer 40 is used as a wiring for flowing a larger current than the other wiring layers 80 and 82.

  On the other hand, in the electronic device 300, the third wiring layer 40 constitutes an inductor element 310 as shown in FIG.

  The inductor element 310 is formed on the protective film 90. The third wiring layer 40 is spirally wound on the protective film 90. That is, the third wiring layer 40 forms a coil. The inductor element 310 can generate an induced electromotive force proportional to the time change of the current when a current flows through the third wiring layer 40. The inductor element 310 is electrically connected to the second wiring layer 82.

  Although not shown, the substrate 10 may be formed with a circuit portion including elements such as transistors and capacitors.

  According to the electronic device 300, since the third wiring layer 40 can constitute the inductor element 310, the inductor element 310 is formed using the same metal layer 8 (see FIG. 9) as the second covering layer 72. be able to.

Here, when the inductor element 310 is used at a high frequency, it is desirable that the DC resistance of the inductor element 310 is small in order to reduce the loss. In the electronic device 300, since the third wiring layer 40 is formed using the same metal layer 8 as the second coating layer 72, the third wiring layer 40 may be formed thicker than the other wiring layers 80 and 82. it can. Therefore, the electronic device 300
Therefore, the loss in the inductor element 310 can be reduced while simplifying the manufacturing process.

  Further, when the inductor element 310 is used at a high frequency, it is formed away from elements (not shown) formed on the substrate 10 and other wiring layers in order to reduce the influence of the proximity effect and the parasitic capacitance. Is desirable. In the electronic device 300, since the third wiring layer 40 is formed using the same metal layer 8 as the second coating layer 72, it can be formed away from the elements formed on the substrate 10 and other wiring layers. . For example, as shown in FIG. 14, the inductor element 310 can be formed of the uppermost third wiring layer 40 among the wiring layers constituting the electronic device 300. Therefore, according to the electronic device 300, the influence of the proximity effect and the parasitic capacitance can be reduced while simplifying the manufacturing process. Further, the influence of the inductor element 310 on the element formed on the substrate 10 can be reduced. Therefore, malfunction of the circuit unit can be prevented, and the characteristics of the device can be stabilized.

  Compared with the method for manufacturing the electronic device 100 according to the first embodiment described above, the method for manufacturing the electronic device 300 according to the second embodiment forms the inductor element 310 by patterning the metal layer 8 (see FIG. 9). This is the same except that the wiring layer 40 is formed, and the description thereof is omitted.

3. Third Embodiment Next, a case where the electronic device according to the present invention is an oscillator will be described as a third embodiment with reference to the drawings. Hereinafter, a case where the electronic device 100 is an oscillator will be described. FIG. 15 is a circuit diagram showing an electronic device (oscillator) 100 according to the third embodiment.

  As illustrated in FIG. 15, the electronic device 100 includes, for example, a functional element (MEMS vibrator) 20 and an inverting amplifier circuit 110. The inverting amplifier circuit 110 is provided, for example, in the circuit unit 3 shown in FIG.

  The functional element 20 includes a first terminal 20 a that is electrically connected to the first electrode 22, and a second terminal 20 b that is electrically connected to the second electrode 24. The first terminal 20a of the functional element 20 is connected to the output terminal 110b of the inverting amplifier circuit 110 at least in an AC manner. The second terminal 20b of the functional element 20 is connected to the input terminal 110a of the inverting amplifier circuit 110 at least in an AC manner.

  In the illustrated example, the inverting amplifier circuit 110 is configured by one inverter, but may be configured by combining a plurality of inverters (inverting circuits) and amplifier circuits so that a desired oscillation condition is satisfied. .

  The electronic device 100 may include a feedback resistor for the inverting amplifier circuit 110. In the example shown in FIG. 15, the input terminal and the output terminal of the inverting amplifier circuit 110 are connected via a resistor 120.

  The electronic device 100 includes a first capacitor 130 connected between an input terminal 110a of the inverting amplifier circuit 110 and a reference potential (ground potential), an output terminal 110b of the inverting amplifier circuit 110, and a reference potential (ground potential). And a second capacitor 132 connected therebetween. As a result, the functional element 20 and the capacitors 130 and 132 can form an oscillation circuit that forms a resonance circuit. The electronic device 100 outputs the oscillation signal f obtained by this oscillation circuit.

As shown in FIG. 16, the electronic device 100 may further include a frequency divider circuit 140. The frequency dividing circuit 140 divides the output signal Vout of the oscillation circuit and outputs the oscillation signal f. Thereby, the electronic device 100 can obtain an output signal having a frequency lower than the frequency of the output signal Vout, for example.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

DESCRIPTION OF SYMBOLS 2 ... Cavity part, 3 ... Circuit part, 4 ... Sacrificial layer, 8 ... Metal layer, 10 ... Substrate, 12 ... 1st base layer, 14 ... 2nd base layer, 20 ... Functional element, 20a ... 1st terminal, 20b 2nd terminal, 22 ... 1st electrode, 24 ... 2nd electrode, 24a ... Supporting part, 24b ... Beam part, 30 ... Transistor, 32 ... Gate insulating film, 34 ... Gate electrode, 36 ... Source region, 37 ... Drain Region 38, side wall, 40 wiring layer (third wiring layer), 50 interlayer insulating layer 51, 51a through hole, 52 first interlayer insulating layer 53, 53a through hole 54 second Interlayer insulating layer 56 ... third interlayer insulating layer 57 ... through hole 58 ... opening 60 ... enclosure wall 62 ... first conductive layer 64 ... second conductive layer 66 ... third conductive layer 70 ... 1st coating layer, 71 ... through-hole, 72 ... 2nd coating layer, 80 ... 1st wiring layer, 82 ... 2nd wiring layer 90 ... protective film, 92 ... first protective film, 94 ... second protective film, 100 ... electronic device, 110 ... inverting amplifier circuit, 110a ... input terminal, 110b ... output terminal, 120 ... resistor, 130 ... first capacitor, 132 ... second capacitor, 140 ... frequency divider, 200 ... electronic device, 210 ... protective film, 300 ... electronic device, 310 ... inductor element

Claims (8)

A substrate,
A functional element formed above the substrate;
A first insulating layer formed around a cavity that accommodates the functional element;
A second insulating layer formed above the first insulating layer;
A first coating layer that defines an upper surface of the cavity and has a through-hole that allows the cavity to communicate with the outside;
A second coating layer formed on the second insulating layer and the first coating layer and sealing the through hole;
A wiring layer formed on the second insulating layer;
Including electronic devices. In claim 1,
The thickness of the said wiring layer and the film thickness of the said 2nd coating layer are the same electronic devices. In claim 1 or 2,
The wiring layer is an electronic device that constitutes an inductor element. In any one of Claims 1 thru | or 3,
The electronic device, wherein the thickness of the wiring layer is larger than the thickness of other wiring layers formed on the first insulating layer. In any one of Claims 1 thru | or 4,
The electronic device, wherein the second covering layer and the wiring layer are formed using the same metal layer. In any one of Claims 1 thru | or 5,
An electronic device comprising a protective film covering the second covering layer and the wiring layer. Forming a functional element above the substrate;
Forming a first insulating layer so as to cover the functional element;
Forming a first covering layer above the first insulating layer;
Forming a through hole in the first coating layer;
Forming a second insulating layer above the first insulating layer;
Removing the first insulating layer above the functional element through the through hole to form a cavity;
Forming a metal layer on the second insulating layer and the first covering layer, sealing the through hole, and forming a wiring layer on the second insulating layer;
A method for manufacturing an electronic device, comprising: In claim 7,
The method of manufacturing an electronic device, wherein in the step of forming the second covering layer and the wiring layer, the wiring layer is formed so as to constitute an inductor element.

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