JP2014184512A - Manufacturing method of electronic device, electronic device, and oscillator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of an electronic device capable of easing a height limit of a functional element.SOLUTION: The manufacturing method of electronic device 100 according to the present invention includes: a process of forming a functional element 20 and a surrounding wall 30 which surrounds the functional element 20 in a first region 10a of a substrate 10; a process of forming a first covering layer 50 covering the functional element 20 and the surrounding wall 30; a process of forming a transistor 71 in a second region 10b of the substrate 10; a process of forming a second covering layer 54 covering the first covering layer 50; a process of forming an interlayer insulating layer 60 covering the second covering layer 54 and the transistor 71; a process of etching back the interlayer insulating layer 60 to expose the second covering layer 54 covering the first covering layer 50; a process of removing the exposed second covering layer 54; a process of forming a lid body 40 provided with through holes 41; a process of removing the first covering layer 50 surrounded by the surrounding wall 30 through the through holes 41 to form a hollow portion 2 in which the functional element 20 is arranged.

Description

  The present invention relates to an electronic device manufacturing method, an electronic device, and an oscillator.

  There is known an electronic device in which a functional element such as a MEMS (Micro Electro Mechanical Systems) is arranged in a cavity formed on a substrate (see Patent Document 1 and Patent Document 2).

  For example, in Patent Document 2, a functional element and a transistor are formed on a substrate, an interlayer insulating layer is formed so as to cover the functional element and the transistor, and the interlayer insulating layer located above the functional element is removed to form a cavity. A method of manufacturing the electronic device to be formed is described. The height of the electronic device described in Patent Document 2 is smaller than the height of the first interlayer insulating layer.

JP 2008-212435 A JP 2008-105157 A

  However, in recent years, there has been a demand for higher performance of functional elements, and accordingly, there is a need to mount functional elements having a large height in electronic devices. Therefore, in particular, there is a demand for a method for manufacturing an electronic device in which a functional element and a transistor are mixedly mounted on the same substrate, and the method for manufacturing the electronic device that can relax the restriction on the height of the functional element.

  One of the objects according to some aspects of the present invention is to provide a method for manufacturing an electronic device that can relax the restriction on the height of a functional element. Another object of some aspects of the present invention is to provide an electronic device and an oscillator that can alleviate the restriction on the height of a functional element.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following aspects or application examples.

[Application Example 1]
One aspect of a method for manufacturing an electronic device according to the present invention is:
Forming a functional element and a surrounding wall surrounding the functional element in a first region of the substrate;
Forming a first covering layer covering the functional element and the surrounding wall;
Forming a transistor in the second region of the substrate;
Forming a second coating layer covering the first coating layer;
Forming an interlayer insulating layer covering the second covering layer and the transistor;
Etching back the interlayer insulating layer to expose the second coating layer covering the first coating layer;
Removing the exposed second coating layer;
Forming a lid provided with a through hole above the first covering layer surrounded by the surrounding wall;
Removing the first covering layer surrounded by the surrounding wall through the through-hole, and forming a cavity where the functional element is disposed;
including.

  According to such a method for manufacturing an electronic device, after the functional element is covered with the first covering layer, the transistor is formed, and further, the interlayer insulating layer is etched back to cover the first covering layer. The coating layer is exposed. Therefore, in such an electronic device manufacturing method, a functional element can be formed regardless of the height of the interlayer insulating layer. Specifically, in such a method for manufacturing an electronic device, even if a functional element has a height greater than the height of the interlayer insulating layer, the functional element is not exposed when the interlayer insulating layer is etched back. Therefore, the restriction on the height of the functional element can be relaxed.

  In the description according to the present invention, the word “upper” is used, for example, “specifically” (hereinafter referred to as “A”) is formed above another specific thing (hereinafter referred to as “B”). The word “upper” is used to include the case where B is formed directly on A and the case where B is formed on A via another object. Used.

[Application Example 2]
In application example 1,
In the step of exposing the second coating layer,
The interlayer insulating layer may be etched back so that the height of the interlayer insulating layer is smaller than the height of the functional element.

  According to such a manufacturing method of an electronic device, even if the interlayer insulating layer is etched back so that the interlayer insulating layer is lower than the functional element, the functional element is covered with the first covering layer. Not exposed.

[Application Example 3]
In application example 1 or 2,
The material of the first covering layer and the material of the interlayer insulating layer are silicon oxide,
The material of the second cover layer may be silicon nitride or silicon oxynitride.

  According to such a method for manufacturing an electronic device, in the step of etching back the interlayer insulating layer and exposing the second coating layer, the etching rate for silicon nitride or silicon oxynitride is low, and the etching rate for silicon oxide is high. By etching back using an etching gas, the interlayer insulating layer can be etched with little etching of the second coating layer.

[Application Example 4]
In any one of Application Examples 1 to 3,
In the step of removing the second coating layer,
The second coating layer may be removed so that the second coating layer remains around the first coating layer.

  According to such a method for manufacturing an electronic device, it is assumed that in the step (release step) in which the first coating layer surrounded by the surrounding wall is removed to form a cavity (release step), the etchant oozes from the surrounding wall. However, the exuded etching solution can be damped by the second coating layer. Thereby, it is possible to suppress the etching solution from reaching the transistor.

[Application Example 5]
In any one of Application Examples 1 to 4,
Before the step of forming the lid,
Removing the interlayer insulating layer to form a contact hole exposing a part of the transistor;
Forming a contact portion in the contact hole;
Forming a wiring layer on the contact portion;
May be included.

  According to such an electronic device manufacturing method, the step of forming the contact portion and the wiring layer and the step of forming the surrounding wall are performed in separate steps. Therefore, it is not necessary to use titanium that is easily dissolved in the release process as the material of the surrounding wall, and the etching solution resistance of the surrounding wall can be increased. Furthermore, the surrounding wall does not need to be configured by the contact portion and the wiring layer, can be formed integrally, and the mechanical strength of the surrounding wall can be increased. As a result, a robust surrounding wall can be formed.

[Application Example 6]
One aspect of the electronic device according to the present invention is:
An enclosing wall formed in a first region of the substrate and defining a cavity;
A functional element disposed in the cavity;
A lid that covers the cavity from above;
A first covering layer formed in the first region and around the surrounding wall;
A second coating layer formed above the first coating layer;
A transistor formed in a second region of the substrate;
An interlayer insulating layer formed over the transistor,
The height of the functional element is greater than the height of the interlayer insulating layer.

  According to such an electronic device, the restriction on the height of the functional element can be relaxed.

[Application Example 7]
In Application Example 6,
The material of the first covering layer and the material of the interlayer insulating layer are silicon oxide,
The material of the second cover layer may be silicon nitride or silicon oxynitride.

  According to such an electronic device, the restriction on the height of the functional element can be relaxed.

[Application Example 8]
The electronic device according to Application Example 6 or 7 is an oscillator,
The transistor may constitute a circuit unit for driving the functional element.

  According to such an oscillator, the restriction on the height of the functional element can be relaxed.

FIG. 6 is a cross-sectional view schematically showing the electronic device according to the embodiment. FIG. 6 is a cross-sectional view schematically showing the electronic device according to the embodiment. FIG. 3 is a plan view schematically showing the electronic apparatus according to the embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the electronic device which concerns on this embodiment. Sectional drawing which shows typically the electronic apparatus which concerns on the modification of this embodiment. The circuit diagram which shows the oscillator concerning this embodiment. The circuit diagram which shows the oscillator which concerns on the modification of this embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, not all of the configurations described below are essential constituent requirements of the present invention.

1. Electronic Device First, an electronic device according to the present embodiment will be described with reference to the drawings. 1 and 2 are cross-sectional views schematically showing an electronic device 100 according to the present embodiment. FIG. 3 is a plan view schematically showing the electronic device 100 according to the present embodiment.

  1 is a cross-sectional view taken along line II shown in FIG. 3, and FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. For convenience, illustration of members other than the conductive portions 3, 4, 9, the contact portions 5, 6, 80, the functional element 20, the first surrounding wall 30, the covering layers 50, 54, and the transistor 71 is omitted. doing.

  As shown in FIGS. 1 to 3, the electronic device 100 includes a substrate 10, a base layer 16, a functional element 20, surrounding walls 30, 32, 36, lids 40, 42, and a first covering layer 50. A protective layer 52, a second covering layer 54, interlayer insulating layers 60, 62, and 64, a circuit unit 70, and passivation layers 90 and 92. The substrate 10 includes a support substrate 12 and a first base layer 14.

  The support substrate 12 of the substrate 10 is a semiconductor substrate such as a silicon substrate, for example. The support substrate 12 may be various substrates such as a ceramic substrate, a glass substrate, a sapphire substrate, a diamond substrate, and a synthetic resin substrate.

  The first foundation layer 14 of the substrate 10 is formed on the support substrate 12. The first underlayer 14 is, for example, a LOCOS (Local Oxidation of Silicon) insulating layer, a semi-recessed LOCOS insulating layer, or a trench insulating layer. The first foundation layer 14 can electrically separate the functional element 20 and the transistor 71 of the circuit unit 70.

As shown in FIG. 1, the substrate 10 includes a first region 10a and a second region 10b. The first region 10a is a portion of the substrate 10 where the first underlayer 14 is formed. The second region 10b is a portion of the substrate 10 where the first underlayer 14 is not formed. First region 10
The a and the second region 10b are formed adjacent to each other.

  The second underlayer 16 is formed on the first underlayer 14. The material of the second foundation layer 16 is, for example, silicon nitride. The second underlayer 16 can function as an etching stopper layer in a release process described later.

  The functional element 20 is formed on the second underlayer 16. The functional element 20 is formed in the first region 10 a of the substrate 10 via the second underlayer 16. The functional element 20 is disposed in the cavity 2. The functional element 20 is, for example, a cantilever type MEMS vibrator. In the illustrated example, the functional element 20 includes a first electrode 22 formed on the second base layer 16 and a second electrode 24 formed at a distance from the first electrode 22.

  As shown in FIG. 2, the second electrode 24 of the functional element 20 is disposed so as to face the support portion 26 formed on the second base layer 16 and to extend from the support portion 26 to the first electrode 22 with a gap. And a beam portion 28. In the example shown in FIG. 3, the planar shape of the beam portion 28 (the shape seen from the thickness direction of the substrate 10) is a quadrangle (square). The material of the electrodes 22 and 24 is, for example, polycrystalline silicon provided with conductivity by doping a predetermined impurity (for example, boron).

  In the functional element 20, when a voltage (alternating voltage) is applied between the electrodes 22 and 24, the beam portion 28 vibrates in the thickness direction of the substrate 10 due to an electrostatic force generated between the electrodes 22 and 24. In the example shown in FIG. 2, the first electrode 22 extends from the inside to the outside of the first surrounding wall 30, and is a wiring layer formed on the second interlayer insulating layer 62 via the conductive portion 3 and the contact portion 5. 7 is connected. Similarly, the second electrode 24 extends from the inside of the first surrounding wall 30 to the outside, and is connected to the wiring layer 8 formed on the second interlayer insulating layer 62 via the conductive portion 4 and the contact portion 6. ing. The wiring layers 7 and 8 are electrically connected to a power supply unit (not shown). Thereby, a voltage can be applied between the electrodes 22 and 24.

As shown in FIG. 1, the height H ₁ of the functional element 20 is larger than the height H _{2 of} the first interlayer insulating layer 60. That is, the functional element 20 is higher than the first interlayer insulating layer 60. Furthermore, the functional element 20 is higher than the first contact portion 80. More specifically, the height of the functional element 20 is 1 μm or more and 5 μm or less. Here, the “height” is a size in a direction parallel to the thickness direction of the substrate 10. “Height” can be replaced with “thickness”. In the illustrated example, the height H ₁ of the functional element 20 is a distance between the upper surface of the substrate 10 (the first underlayer 14 in the first region 10 a) and the upper surface of the second electrode 24. The height H ₂ of the first interlayer insulating layer 60 is a distance between the upper surface of the substrate 10 (the support substrate 12 in the second region 10 b) and the upper surface of the first interlayer insulating layer 60.

  The functional element 20 is not limited to the illustrated example, and may be, for example, a double-supported beam type vibrator in which both ends of the beam portion are fixed. In addition, the functional element 20 may be various functional elements such as a quartz crystal vibrator other than the MEMS vibrator, a SAW (surface acoustic wave) element, an acceleration sensor, a gyroscope, and a microactuator. As described above, the electronic device 100 can include an arbitrary functional element that can be accommodated in the cavity 2.

The first surrounding wall (enclosing wall) 30 is formed on the second underlayer 16. The first surrounding wall 30 is formed in the first region 10 a of the substrate 10 via the second underlayer 16. As shown in FIG. 3, the first surrounding wall 30 surrounds the functional element 20 in a plan view. The planar shape of the first surrounding wall 30 is not particularly limited as long as the functional element 20 can be surrounded. The first surrounding wall 30 defines the cavity 2. As shown in FIG. 2, the first surrounding wall 30 has an opening for passing the electrodes 22 and 24 from the inside to the outside of the first surrounding wall 30. The material of the first surrounding wall 30 is the same as the material of the electrodes 22 and 24, for example.

  The second surrounding wall 32 is formed on the first surrounding wall 30. The planar shape of the second surrounding wall 32 may be the same as the planar shape of the first surrounding wall 30. The second surrounding wall 32 defines the cavity 2. In the illustrated example, the second surrounding wall 32 includes a first portion 33 formed on the first surrounding wall 30 and a second portion 34 formed on the first portion 33. The material of the first portion 33 is, for example, the same as the material of the second contact portion 81. The material of the second portion 34 is the same as the material of the second wiring layer 84, for example.

  The third surrounding wall 36 is formed on the second surrounding wall 32. The planar shape of the third surrounding wall 36 may be the same as the planar shape of the second surrounding wall 32. The third surrounding wall 36 defines the cavity 2. In the illustrated example, the third surrounding wall 36 includes a third portion 37 formed on the second surrounding wall 32 and a fourth portion 38 formed on the third portion 37. The material of the third portion 37 is the same as the material of the third contact portion 82, for example. The material of the fourth portion 38 is the same as the material of the third wiring layer 85, for example.

  The first lid (lid) 40 covers the cavity 2 from above. In the illustrated example, the first lid 40 is continuous with the fourth portion 38 of the third surrounding wall 36. That is, the first lid 40 is formed integrally with the fourth portion 38, and the material of the first lid 40 is the same as the material of the fourth portion 38. A through-hole 41 that communicates with the cavity 2 is formed in the first lid 40. The number of through holes 41 is not particularly limited.

  The second lid body 42 is formed on the first lid body 40. The second lid 42 closes the through hole 41. The material of the second lid 42 is, for example, aluminum, copper, titanium, tungsten, or an alloy thereof. The lids 40 and 42 can cover the cavity 2 from above and seal the cavity 2.

  The surrounding walls 30, 32, 36 and the lids 40, 42 may have a constant potential (for example, ground potential). Thereby, the surrounding walls 30, 32, and 36 and the lids 40 and 42 can function as electromagnetic shields. Therefore, the functional element 20 can be shielded from an electric field or a magnetic field outside the cavity 2, and the characteristics of the functional element 20 can be further stabilized.

  The cavity 2 is a space for accommodating the functional element 20. In the illustrated example, the cavity 2 is defined (defined) by the surrounding walls 30, 32, 36, the lids 40, 42, the second underlayer 16, and the first covering layer 50. The cavity 2 is in a reduced pressure state, for example. Thereby, the operational accuracy of the functional element 20 can be improved.

  The first covering layer 50 is formed on the second underlayer 16. The first covering layer 50 is formed in the first region 10 a of the substrate 10 via the second underlayer 16. The first covering layer 50 is formed around the first surrounding wall 30 in plan view. The height of the first coating layer 50 (the height of the highest portion of the first coating layer 50) is larger than the height of the functional element 20. The height of the 1st coating layer 50 is 1.2 micrometers or more and 6 micrometers or less, for example. The material of the first cover layer 50 is, for example, silicon oxide.

  As shown in FIG. 1, the protective layer 52 is formed on the first covering layer 50, on the conductive portion 9, on the substrate 10, and on the sidewall 76 of the transistor 71. The thickness of the protective layer 52 is, for example, not less than 0.01 μm and not more than 1 μm. The material of the protective layer 52 is, for example, silicon oxide. The protective layer 52 can protect the transistor 71.

  A conductive portion 9 is formed between the first covering layer 50 and the protective layer 52. In the illustrated example, the conductive portion 9 is formed on the first base layer 14 and is formed around the first coating layer 50 and the second base layer 16 in plan view. The conductive portion 9 has a curved side surface, and the side surface is covered with a protective layer 52. The material of the conductive portion 9 is the same as the material of the gate electrode 73, for example.

  The second covering layer 54 is formed on the protective layer 52. The second coating layer 54 covers the first coating layer 50 via the protective layer 52. That is, the second coating layer 54 is formed above the first coating layer 50. In the illustrated example, the second covering layer 54 is formed to be separated from the second surrounding wall 32. The end surface 55 of the second covering layer 54 on the functional element 20 side is flush with the upper surface of the first interlayer insulating layer 60. The thickness of the 2nd coating layer 54 is 0.01 micrometer or more and 0.5 micrometer or less, for example. The material of the second covering layer 54 is, for example, silicon nitride or silicon oxynitride.

  The first interlayer insulating layer (interlayer insulating layer) 60 is formed on the second covering layer 54. The first interlayer insulating layer 60 is formed to cover the transistor 71. In the illustrated example, the first interlayer insulating layer 60 is formed around the first coating layer 50 in plan view and is in contact with the second coating layer 54. The height of the first interlayer insulating layer 60 is smaller than the height of the functional element 20. Specifically, the height of the first interlayer insulating layer 60 is not less than 0.5 μm and not more than 1.5 μm. The material of the first interlayer insulating layer 60 is, for example, silicon oxide.

  The second interlayer insulating layer 62 is formed on the protective layer 52 and the first interlayer insulating layer 60. The second interlayer insulating layer 62 is formed around the second surrounding wall 32 in plan view. The material of the second interlayer insulating layer 62 is the same as the material of the first interlayer insulating layer 60, for example.

  The third interlayer insulating layer 64 is formed on the second interlayer insulating layer 62. The third interlayer insulating layer 64 is formed around the third surrounding wall 36 in plan view. The material of the third interlayer insulating layer 64 is the same as the material of the first interlayer insulating layer 60, for example.

  The circuit unit 70 is formed on the substrate 10. In the illustrated example, the circuit unit 70 is formed in the second region 10 b of the substrate 10. Although not shown, the circuit unit 70 is electrically connected to the functional element 20. The circuit unit 70 is a circuit for driving the functional element 20. The circuit unit 70 includes a transistor 71, contact units 80, 81, and 82, and wiring layers 83, 84, and 85. Although not shown, the circuit unit 70 may include elements other than transistors (for example, capacitors and resistors).

The transistor 71 is formed in the second region 10 b of the substrate 10. The transistor 71 is a MOS (Metal Oxide Semiconductor) transistor including a gate insulating film 72, a gate electrode 73, a source region 74, a drain region 75, and a sidewall 76. As shown in FIG. 1, the height H ₃ of the transistor 71 is smaller than the height H _{2 of} the first interlayer insulating layer 60. The height H ₃ of the transistor 71 is a distance between the upper surface of the substrate 10 (the support substrate 12 in the second region 10 b) and the upper surface of the gate electrode 73.

The gate insulating film 72 of the transistor 71 is formed on the support substrate 12. The material of the gate insulating film 72 is, for example, silicon oxide. The gate electrode 73 is formed on the gate insulating film 72. The material of the gate electrode 73 is, for example, polycrystalline silicon imparted with conductivity by doping a predetermined impurity. The source region 74 and the drain region 75 are formed on the support substrate 12. The source region 74 and the drain region 75 are formed by doping the support substrate 12 with a predetermined impurity. The sidewall 76 is formed on the side of the gate electrode 73. The material of the sidewall 76 is, for example, silicon oxide or silicon nitride.

  The first contact portion 80 is formed in a first contact hole 61 provided in the first interlayer insulating layer 60. The first contact portion 80 is formed corresponding to the gate electrode 73, the source region 74, and the drain region 75. The first contact portion 80 is connected to the gate electrode 73, the source region 74, and the drain region 75. The first wiring layer 83 is formed on the first contact portion 80.

  The second contact portion 81 is formed in the second contact hole 63 provided in the second interlayer insulating layer 62 on the first wiring layer 83. The second wiring layer 84 is formed on the second contact portion 81.

  The third contact portion 82 is formed on the second wiring layer 84 and in the third contact hole 65 provided in the third interlayer insulating layer 64. The third wiring layer 85 is formed on the third contact portion 82. The material of the contact portions 80, 81, 82 is, for example, copper, tungsten, titanium, or an alloy thereof. The material of the wiring layers 83, 84, 85 is, for example, aluminum, copper, tungsten, titanium, or an alloy thereof, or polycrystalline silicon imparted with conductivity by doping a predetermined impurity (for example, boron).

  The first passivation layer 90 is formed on the third interlayer insulating layer 64. The material of the first passivation layer 90 is, for example, silicon oxide. The second passivation layer 92 is formed on the first passivation layer 90. The material of the second passivation layer 92 is, for example, silicon nitride. The passivation layers 90 and 92 can protect the third interlayer insulating layer 64 and the like.

  In the above example, an example in which three interlayer insulating layers are formed has been described. However, the number of interlayer insulating layers is not particularly limited, and may be one or two, or may be four or more. . The number of surrounding walls, contact portions, and wiring layers can also be changed as appropriate according to the number of interlayer insulating layers.

  According to the electronic apparatus 100, the restriction on the height of the functional element 20 can be relaxed. Details will be described later.

2. Next, a method for manufacturing an electronic device according to the present embodiment will be described with reference to the drawings. 4 to 19 are cross-sectional views schematically showing the manufacturing process of the electronic device 100 according to this embodiment, and correspond to FIG.

  As shown in FIG. 4, the first base layer 14 is formed on the support substrate 12. The first underlayer 14 is formed by, for example, a LOCOS method or an STI (Shallow Trench Isolation) method.

  Next, the second underlayer 16 is formed on the first underlayer 14. The second underlayer 16 is formed by, for example, a CVD (Chemical Vapor Deposition) method or a sputtering method.

Next, the first electrode 22 and the support portion 26 (see FIG. 2) for the second electrode 24 are formed on the second underlayer 16. The first electrode 22 and the support portion 26 are formed by forming a film by a CVD method, a sputtering method, or the like and then patterning (specifically, patterning by a photolithography technique and an etching technique). In the case where the first electrode 22 and the support portion 26 are made of polycrystalline silicon, a predetermined impurity is doped to impart conductivity.

  Next, the sacrificial layer 102 is formed so as to cover the first electrode 22. The sacrificial layer 102 is formed, for example, by thermally oxidizing the first electrode 22. Thermal oxidation is performed, for example, at 800 ° C. or higher and 1100 ° C. or lower.

  Next, the beam portion 28 (see FIG. 2) of the second electrode 24 is formed on the sacrificial layer 102, and the first surrounding wall 30 is formed on the second underlayer 16. The beam portion 28 and the first surrounding wall 30 are formed by, for example, a film forming process and a patterning process similar to those of the first electrode 22. When the beam portion 28 and the first surrounding wall 30 are made of polycrystalline silicon, a predetermined impurity is doped in order to impart conductivity. In addition, the process of forming the beam part 28 and the process of forming the 1st surrounding wall 30 may be performed simultaneously, and may be performed separately.

  As described above, the functional element 20 and the first surrounding wall 30 surrounding the functional element 20 can be formed in the first region 10 a of the substrate 10 via the second underlayer 16. In the step of forming the beam portion 28 and the first surrounding wall 30, the conductive portions 3 and 4 (see FIG. 2) may be formed.

  As shown in FIG. 5, the 1st coating layer 50 which covers the functional element 20 and the 1st surrounding wall 30 is formed. The first covering layer 50 is formed on the first region 10 a and the second region 10 b of the substrate 10 via the second underlayer 16. The 1st coating layer 50 is formed by CVD method, for example.

  As shown in FIG. 6, the 1st coating layer 50 and the 2nd base layer 16 are patterned. By this step, the first covering layer 50 covering the functional element 20 and the first surrounding wall 30 can be formed. Further, the first underlayer 14 is exposed by this step. In the illustrated example, patterning is performed so that the end surfaces of the first covering layer 50 and the second underlayer 16 are vertical (in parallel with the thickness direction of the substrate 10).

  As shown in FIG. 7, a gate insulating film 72 is formed on the second region 10b of the substrate 10 by, eg, thermal oxidation. Next, a gate electrode 73 is formed on the gate insulating film 72 by forming a film by, for example, a vacuum evaporation method or a sputtering method, and then patterning. Simultaneously with the formation of the gate electrode 73, the conductive portion 9 is formed around the first covering layer 50 and the second underlayer 16. Next, after forming a film by, for example, a CVD method, a sidewall 76 is formed on the side of the gate electrode 73 by etching. Next, an impurity is implanted into the support substrate 10 by ion implantation, for example, to form the source region 74 and the drain region 75. Through this step, the transistor 71 can be formed in the second region 10 b of the substrate 10.

  Next, the protective layer 52 is formed on the first covering layer 50, the conductive portion 9, and the sidewall 76. The protective layer 52 is formed by, for example, film formation by CVD and patterning.

  As shown in FIG. 8, a second coating layer 54 that covers the first coating layer 50 and the transistor 71 is formed. Specifically, the second coating layer 54 that covers the first coating layer 50 and the transistor 71 is formed via the protective layer 52. The second coating layer 54 is formed by, for example, a CVD method.

  As shown in FIG. 9, a first interlayer insulating layer 60 that covers the second covering layer 54 and the transistor 71 is formed. The first interlayer insulating layer 60 is formed by, for example, a CVD method or a coating (spin coating) method. Specifically, the transistor 71 is covered with the first interlayer insulating layer 60 via the second covering layer 54.

  As shown in FIG. 10, the first interlayer insulating layer 60 is planarized by chemical mechanical polishing (CMP). In the illustrated example, the first interlayer insulating layer 60 is planarized so that the protective layer 52 is not exposed.

  As shown in FIG. 11, the first interlayer insulating layer 60 is etched back, and the second coating layer 54 (specifically, the first coating layer 50 is interposed via the protective layer 52) covering the first coating layer 50. The second covering layer 54) covering the surface is exposed. In this step, the first interlayer insulating layer 60 is etched back so that the height of the first interlayer insulating layer 60 is smaller than the height of the functional element 20. The etch back is performed using an etching gas having a low etching rate with respect to the second covering layer 54 and a high etching rate with respect to the first interlayer insulating layer 60. Thereby, the first interlayer insulating layer 60 can be etched without almost etching the second coating layer 54.

  Note that “etch back” refers to etching for removing the entire material layer (the object to be etched, specifically, the first interlayer insulating layer 60) without using a mask such as a photoresist.

  As shown in FIG. 12, a resist layer R 1 having a predetermined shape is formed on the first interlayer insulating layer 60. The resist layer R1 is formed by a known method. Next, the first interlayer insulating layer 60 and the second covering layer 54 are etched using the resist layer R1 as a mask. Thereby, the exposed second coating layer 54 can be removed to expose the protective layer 52. In this step, the second coating layer 54 is removed so that the second coating layer 54 remains around the first coating layer 50 in plan view. Further, the first contact hole 61 that exposes the gate electrode 73, the source region 74, and the drain region 75 that are part of the transistor 71 can be formed in the first interlayer insulating layer 60 by this step. Thereafter, the resist layer R1 is removed by a known method. The step of removing the second covering layer 54 and exposing the protective layer 52 and the step of removing the first interlayer insulating layer 60 and the second covering layer 54 and exposing a part of the transistor 71 are performed simultaneously. May be performed separately.

  As shown in FIG. 13, the first contact portion 80 is formed in the first contact hole 61. Next, the first wiring layer 83 is formed on the first contact portion 80. The first contact portion 80 is formed by filling the first contact hole 61 by, for example, a sputtering method or a CVD method. The first wiring layer 83 is formed by, for example, forming a film by sputtering, CVD, or plating and then patterning.

  As shown in FIG. 14, a second interlayer insulating layer 62 that covers the protective layer 52, the first interlayer insulating layer 60, and the first wiring layer 83 is formed. The second interlayer insulating layer 62 is formed, for example, by being formed by a CVD method or a coating (spin coating) method and then planarized by CMP.

  As shown in FIG. 15, the second interlayer insulating layer 62 is patterned to form a second contact hole 63. Next, the first portion 33 of the second surrounding wall 32 and the second contact portion 81 are formed in the second contact hole 63. Next, the second portion 34 of the second surrounding wall 32 is formed on the first portion 33, and the second wiring layer 84 is formed on the second contact portion 81. The second surrounding wall 32 and the second contact portion 81 are formed by filling the second contact hole 63 by, for example, a sputtering method or a CVD method. The second wiring layer 84 is formed by, for example, forming a film by sputtering, CVD, or plating and then patterning.

As shown in FIG. 16, a third interlayer insulating layer 64 that covers the second surrounding wall 32, the second interlayer insulating layer 62, and the second wiring layer 84 is formed. For example, the third interlayer insulating layer 64 may be formed by CVD or coating (
A film is formed by spin coating), and then planarized by CMP.

  As shown in FIG. 17, the third interlayer insulating layer 64 is patterned to form a third contact hole 65. Next, the third portion 37 of the third surrounding wall 36 and the third contact portion 82 are formed in the third contact hole 65. Next, the fourth portion 38 of the third surrounding wall 36 is formed on the third portion 37, and on the second interlayer insulating layer 62 (above the first covering layer 50 surrounded by the first surrounding wall 30). A first lid 40 provided with a through hole 41 is formed. The fourth portion 38 and the first lid body 40 may be integrally formed. Further, a third wiring layer 85 is formed on the third contact portion 82. The third contact portion 82 and the third portion 37 are formed by filling the third contact hole 65 by, for example, a sputtering method or a CVD method. The third wiring layer 85, the fourth portion 38, and the first lid 40 are formed by, for example, forming a film by sputtering, CVD, or plating and then patterning.

  The first lid body 40 provided with the through hole 41 is formed by, for example, etching the first lid body 40 after forming the first lid body 40 without the through hole by sputtering or CVD. The metal layer may be formed by growing the metal layer so that the through hole 41 is provided by plating.

  As shown in FIG. 18, a first passivation layer 90 that covers the third interlayer insulating layer 64, the third surrounding wall 36, the first lid 40, and the third wiring layer 85 is formed. Next, a second passivation layer 92 that covers the first passivation layer 90 is formed. The passivation layers 90 and 92 are formed by, for example, a CVD method or a coating (spin coating) method. Next, the passivation layers 90 and 92 are patterned to expose the first lid 40. Next, a resist layer R2 having a predetermined shape is formed on the second passivation layer 92 and on the side surfaces of the passivation layers 90 and 92. The resist layer R2 is formed by a known method.

  As shown in FIG. 19, the interlayer insulating layers 62 and 64, the first covering layer 50, the protective layer 52, and the sacrificial layer are surrounded by the surrounding walls 30, 32, and 36 through an etching solution or etching gas through the through hole 41. 102 is removed (release process). Thereby, the cavity 2 in which the functional element 20 is disposed can be formed. The release process can be performed, for example, by wet etching using hydrofluoric acid or buffered hydrofluoric acid (mixed liquid of hydrofluoric acid and ammonium fluoride) or dry etching using a hydrogen fluoride-based gas. . Thereafter, the resist layer R2 is removed by a known method. If necessary, the cavity 2 may be washed with isopropyl alcohol (IPA) or water.

  As shown in FIG. 1, a second lid 42 is formed on the first lid 40 to close the through hole 41. The second lid 42 is formed, for example, by film formation and patterning by sputtering or CVD. By forming the second lid body 42 by a vapor phase growth method such as a sputtering method or a CVD method, the cavity 2 can be sealed in a reduced pressure state.

  Through the above steps, the electronic device 100 can be manufactured.

According to the method for manufacturing the electronic device 100, after covering the functional element 20 with the first covering layer 50, the transistor 71 is formed, and the first interlayer insulating layer 60 is etched back to form the first covering layer 50. The covering second covering layer 54 is exposed. Therefore, in the method for manufacturing the electronic device 100, the functional element 20 can be formed regardless of the height of the first interlayer insulating layer 60. Specifically, in the method of manufacturing the electronic device 100, even when the functional element 20 has a height larger than the height of the first interlayer insulating layer 60, the first interlayer insulating layer 60 is planarized by CMP. The functional element 20 is not exposed. Therefore, in the method of manufacturing the electronic device 100, the functional element 2
The restriction on the height of 0 can be relaxed, and the high-performance functional element 20 can be mounted.

  For example, when the first interlayer insulating layer is planarized by CMP, as a method of not exposing the functional element, it is conceivable that the height of the first interlayer insulating layer is sufficiently larger than the height of the functional element. However, in this method, the aspect ratio of the contact hole for forming the contact portion connected to the transistor becomes high, and the processing becomes difficult. Moreover, even if it can process, the resistance of a contact part will become high.

  Further, as a method of not exposing the functional element when the first interlayer insulating layer is planarized by CMP, a method of forming a depression in the substrate and arranging the functional element in the depression is conceivable. However, this method requires significant additional steps.

  According to the method for manufacturing the electronic device 100, the first interlayer insulating layer 60 is etched back so that the height of the first interlayer insulating layer 60 is smaller than the height of the functional element 20. In the method for manufacturing the electronic device 100, as described above, in the method for manufacturing the electronic device 100, even if the first interlayer insulating layer 60 is etched back so that the first interlayer insulating layer 60 is lower than the functional element 20, Since the functional element 20 is covered with the first covering layer 50, it is not exposed.

  According to the method for manufacturing the electronic device 100, the material of the first coating layer 50 and the material of the first interlayer insulating layer 60 are silicon oxide, and the material of the second coating layer 54 is silicon nitride or silicon oxynitride. . Therefore, in the step of etching back the first interlayer insulating layer 60 and exposing the second covering layer 54, an etching gas having a low etching rate for silicon nitride or silicon oxynitride and a high etching rate for silicon oxide is used. By etching back, the first interlayer insulating layer 60 can be etched with little etching of the second covering layer 54.

  According to the method for manufacturing the electronic device 100, the second coating layer 54 is removed so that the second coating layer 54 remains around the first surrounding wall 30. Therefore, in the method for manufacturing the electronic device 100, even if the etching solution oozes out from the first surrounding wall 30 in the release step, the leaching etching solution can be damped by the second coating layer 54. Thereby, it is possible to suppress the etching solution from reaching the transistor 71.

  According to the method for manufacturing the electronic device 100, the conductive portion 9 is formed around the first covering layer 50 and the second underlayer 16. Therefore, in the method for manufacturing the electronic device 100, even if the etchant oozes out from the first surrounding wall 30 in the release step, the ooze out etchant can be stopped by the conductive portion 9. Thereby, it is possible to suppress the etching solution from reaching the transistor 71.

  According to the method for manufacturing the electronic device 100, the step of removing the first interlayer insulating layer 60 to form the first contact hole 61 that exposes a part of the transistor 71, and the first contact portion in the first contact hole 61. 80 and a step of forming a first wiring layer 83 on the first contact portion 80. As described above, in the method for manufacturing the electronic device 100, the step of forming the first contact portion 80 and the first wiring layer 83 and the step of forming the first surrounding wall 30 are performed in separate steps. Therefore, it is not necessary to use titanium that dissolves easily in the release process as the material of the first surrounding wall 30, and the etchant resistance of the first surrounding wall 30 can be increased. Further, the first surrounding wall 30 does not need to be configured by the contact portion and the wiring layer, and can be integrally formed, and the mechanical strength of the first surrounding wall 30 can be increased. As a result, the robust first surrounding wall 30 can be formed.

3. Modified Example Next, an electronic device 200 according to a modified example of the present embodiment will be described with reference to the drawings. FIG. 20 is a cross-sectional view schematically showing an electronic device 200 according to a modification of the present embodiment, and corresponds to FIG.

  Hereinafter, in the electronic device 200 according to the modified example of the present embodiment, members having the same functions as the constituent members of the electronic device 100 according to the present embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the electronic device 100, as illustrated in FIG. 1, the second covering layer 54 is separated from the second surrounding wall 32. On the other hand, in the electronic device 200, as illustrated in FIG. 20, the second covering layer 54 is in contact with the second surrounding wall 32.

  According to the electronic device 200, even if the etching solution oozes out from the first surrounding wall 30 in the release process, the etching solution oozed out more reliably by the second coating layer 54 than in the electronic device 100. Can be stopped. Thereby, it is possible to suppress the etching solution from reaching the transistor 71.

  According to the electronic device 200, the second surrounding wall 32 can be supported by the second covering layer 54. Therefore, in the electronic device 200, the strength of the surrounding walls 30, 32, and 36 can be increased.

  The manufacturing method of the electronic device 200 is basically the same as the manufacturing method of the electronic device 100 except that the opening width W of the resist layer R1 shown in FIG. Therefore, the detailed description is abbreviate | omitted.

4). Oscillator Next, the case where the electronic device according to the present invention is an oscillator will be described with reference to the drawings. Hereinafter, a case where the electronic device 100 is an oscillator will be described. FIG. 21 is a circuit diagram showing an electronic device (oscillator) 100 according to this embodiment.

  As shown in FIG. 21, the oscillator 100 includes a functional element (specifically, a MEMS vibrator) 20 and an inverting amplifier circuit 110.

  The functional element 20 includes a first terminal 20a electrically connected to the first electrode 22 (with the wiring layer 7), and a second terminal 20b electrically connected to the second electrode 24 (with the wiring layer 8). ,have. The first terminal 20a of the functional element 20 is connected to the input terminal 110a of the inverting amplifier circuit 110 at least in an AC manner. The second terminal 20b of the functional element 20 is connected to the output terminal 110b of the inverting amplifier circuit 110 at least in an AC manner.

  In the illustrated example, the inverting amplifier circuit 110 is configured by one inverter, but may be configured by combining a plurality of inverters (inverting circuits) and amplifier circuits so that a desired oscillation condition is satisfied. .

  The oscillator 100 may include a feedback resistor for the inverting amplifier circuit 110. In the example shown in FIG. 21, the input terminal and the output terminal of the inverting amplifier circuit 110 are connected via a resistor 120.

The oscillator 100 includes a first capacitor 130 connected between an input terminal 110a of the inverting amplifier circuit 110 and a reference potential (ground potential), and an output terminal 110b of the inverting amplifier circuit 110 and a reference potential (ground potential). And a second capacitor 132 connected to the second capacitor 132. As a result, the functional element 20 and the capacitors 130 and 132 can form an oscillation circuit that forms a resonance circuit. The electronic device 100 outputs the oscillation signal f obtained by this oscillation circuit.

As shown in FIG. 22, the oscillator 100 may further include a frequency dividing circuit 140. The frequency dividing circuit 140 divides the output signal _Vout of the oscillation circuit and outputs the oscillation signal f. Thereby, the electronic device 100 can obtain an output signal having a frequency lower than the frequency of the output signal _Vout , for example.

  Note that the inverting amplifier circuit 110, the resistor 120, the capacitors 130 and 132, and the frequency divider circuit 140 constitute, for example, the circuit unit 70 shown in FIG.

  The above-described embodiments and modifications are merely examples, and the present invention is not limited to these. For example, it is possible to appropriately combine each embodiment and each modification.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

DESCRIPTION OF SYMBOLS 2 ... Hollow part, 3, 4 ... Conductive part, 5, 6 ... Contact part, 7, 8 ... Wiring layer, 9 ... Conductive part, 10 ... Substrate, 10a ... 1st area | region, 10b ... 2nd area | region, 12 ... Support Substrate, 14 ... first underlayer, 16 ... second underlayer, 20 ... functional element, 22 ... first electrode, 24 ... second electrode, 26 ... support, 28 ... beam, 30 ... first surrounding wall, 32 ... 2nd surrounding wall, 33 ... 1st part, 34 ... 2nd part, 36 ... 3rd surrounding wall, 37 ... 3rd part, 38 ... 4th part, 40 ... 1st cover body, 41 ... Through-hole, 42 ... second lid, 50 ... first coating layer, 52 ... protective layer, 54 ... second coating layer, 55 ... end face, 60 ... first interlayer insulating layer, 61 ... first contact hole, 62 ... second interlayer Insulating layer, 63 ... second contact hole, 64 ... third interlayer insulating layer, 65 ... third contact hole, 70 ... circuit portion, 71 ... transistor, 7 DESCRIPTION OF SYMBOLS ... Gate insulating film, 73 ... Gate electrode, 74 ... Source region, 75 ... Drain region, 76 ... Side wall, 80 ... First contact part, 81 ... Second contact part, 82 ... Third contact part, 83 ... First Wiring layer, 84 ... second wiring layer, 85 ... third wiring layer, 90 ... first passivation layer, 92 ... second passivation layer, 100 ... electronic device, 102 ... sacrificial layer, 110 ... inverting amplifier circuit, 110a ... input Terminal 110b Output terminal 120 Resistance 130 First capacitor 132 Second capacitor 140 Dividing circuit 200 Electronic device

Claims (8)

Forming a functional element and a surrounding wall surrounding the functional element in a first region of the substrate;
Forming a first covering layer covering the functional element and the surrounding wall;
Forming a transistor in the second region of the substrate;
Forming a second coating layer covering the first coating layer;
Forming an interlayer insulating layer covering the second covering layer and the transistor;
Etching back the interlayer insulating layer to expose the second coating layer covering the first coating layer;
Removing the exposed second coating layer;
Forming a lid provided with a through hole above the first covering layer surrounded by the surrounding wall;
Removing the first covering layer surrounded by the surrounding wall through the through-hole, and forming a cavity where the functional element is disposed;
A method for manufacturing an electronic device, comprising: In claim 1,
In the step of exposing the second coating layer,
A method of manufacturing an electronic device, wherein the interlayer insulating layer is etched back so that the height of the interlayer insulating layer is smaller than the height of the functional element. In claim 1 or 2,
The material of the first covering layer and the material of the interlayer insulating layer are silicon oxide,
The method for manufacturing an electronic device, wherein the material of the second covering layer is silicon nitride or silicon oxynitride. In any one of Claims 1 thru | or 3,
In the step of removing the second coating layer,
A method of manufacturing an electronic device, wherein the second coating layer is removed so that the second coating layer remains around the first coating layer. In any one of Claims 1 thru | or 4,
Before the step of forming the lid,
Removing the interlayer insulating layer to form a contact hole exposing a part of the transistor;
Forming a contact portion in the contact hole;
Forming a wiring layer on the contact portion;
A method for manufacturing an electronic device, comprising: An enclosing wall formed in a first region of the substrate and defining a cavity;
A functional element disposed in the cavity;
A lid that covers the cavity from above;
A first covering layer formed in the first region and around the surrounding wall;
A second coating layer formed above the first coating layer;
A transistor formed in a second region of the substrate;
An interlayer insulating layer formed over the transistor,
The height of the said functional element is an electronic device larger than the height of the said interlayer insulation layer. In claim 6,
The material of the first covering layer and the material of the interlayer insulating layer are silicon oxide,
The electronic device, wherein the material of the second covering layer is silicon nitride or silicon oxynitride. The electronic device according to claim 6 or 7 is an oscillator,
The transistor is an oscillator forming a circuit unit for driving the functional element.

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