JP2013004984A - 半導体パッケージ - Google Patents

半導体パッケージ Download PDF

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Publication number
JP2013004984A
JP2013004984A JP2012135669A JP2012135669A JP2013004984A JP 2013004984 A JP2013004984 A JP 2013004984A JP 2012135669 A JP2012135669 A JP 2012135669A JP 2012135669 A JP2012135669 A JP 2012135669A JP 2013004984 A JP2013004984 A JP 2013004984A
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JP
Japan
Prior art keywords
carrier
semiconductor package
component
test
seat
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Pending
Application number
JP2012135669A
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English (en)
Japanese (ja)
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JP2013004984A5 (https=
Inventor
Birge Adam
バージ アダム
Pickup Kevin
ピックアップ ケビン
A Primavera Anthony
エイ．プリマベラ アンソニー、
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Biotronik SE and Co KG
Original Assignee
Biotronik SE and Co KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Biotronik SE and Co KG filed Critical Biotronik SE and Co KG
Publication of JP2013004984A publication Critical patent/JP2013004984A/ja
Publication of JP2013004984A5 publication Critical patent/JP2013004984A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/657—Shapes or dispositions of interconnections on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/284—Configurations of stacked chips characterised by structural arrangements for measuring or testing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
JP2012135669A 2011-06-17 2012-06-15 半導体パッケージ Pending JP2013004984A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201161497966P 2011-06-17 2011-06-17
US61/497,966 2011-06-17

Publications (2)

Publication Number Publication Date
JP2013004984A true JP2013004984A (ja) 2013-01-07
JP2013004984A5 JP2013004984A5 (https=) 2015-05-21

Family

ID=46087515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012135669A Pending JP2013004984A (ja) 2011-06-17 2012-06-15 半導体パッケージ

Country Status (3)

Country Link
US (1) US8981546B2 (https=)
EP (1) EP2535926A3 (https=)
JP (1) JP2013004984A (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104966708B (zh) * 2015-07-01 2018-06-12 英特尔公司 半导体封装结构
US10916529B2 (en) * 2018-03-29 2021-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Electronics card including multi-chip module
EP3603740A1 (de) * 2018-08-02 2020-02-05 BIOTRONIK SE & Co. KG Implantat
GB2600918B (en) 2020-10-30 2022-11-23 Npl Management Ltd Ion microtrap assembly and method of making of making such an assembly

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08250620A (ja) * 1995-03-07 1996-09-27 Matsushita Electron Corp 半導体装置
JPH10233464A (ja) * 1997-02-19 1998-09-02 Nec Corp Ｂｇａ型半導体装置およびそのプローブ装置
JPH1117058A (ja) * 1997-06-26 1999-01-22 Nec Corp Ｂｇａパッケージ、その試験用ソケットおよびｂｇａパッケージの試験方法
JP2006344917A (ja) * 2005-06-10 2006-12-21 Sharp Corp 半導体装置、積層型半導体装置、および半導体装置の製造方法
WO2008035650A1 (en) * 2006-09-19 2008-03-27 Panasonic Corporation Socket, module board, and inspection system using the module board
JP2008277595A (ja) * 2007-05-01 2008-11-13 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05102262A (ja) * 1991-10-03 1993-04-23 Hitachi Ltd 半導体装置及びそれを実装した実装装置
US5334857A (en) * 1992-04-06 1994-08-02 Motorola, Inc. Semiconductor device with test-only contacts and method for making the same
JP3447908B2 (ja) * 1997-02-13 2003-09-16 富士通株式会社 ボールグリッドアレイパッケージ
US20040135242A1 (en) * 2003-01-09 2004-07-15 Hsin Chung Hsien Stacked structure of chips
US7100814B2 (en) * 2004-02-18 2006-09-05 Cardiac Pacemakers, Inc. Method for preparing integrated circuit modules for attachment to printed circuit substrates

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08250620A (ja) * 1995-03-07 1996-09-27 Matsushita Electron Corp 半導体装置
JPH10233464A (ja) * 1997-02-19 1998-09-02 Nec Corp Ｂｇａ型半導体装置およびそのプローブ装置
JPH1117058A (ja) * 1997-06-26 1999-01-22 Nec Corp Ｂｇａパッケージ、その試験用ソケットおよびｂｇａパッケージの試験方法
JP2006344917A (ja) * 2005-06-10 2006-12-21 Sharp Corp 半導体装置、積層型半導体装置、および半導体装置の製造方法
WO2008035650A1 (en) * 2006-09-19 2008-03-27 Panasonic Corporation Socket, module board, and inspection system using the module board
JP2008277595A (ja) * 2007-05-01 2008-11-13 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

Also Published As

Publication number Publication date
EP2535926A2 (en) 2012-12-19
US8981546B2 (en) 2015-03-17
EP2535926A3 (en) 2015-08-05
US20120319288A1 (en) 2012-12-20

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