JP2012523616A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2012523616A5 JP2012523616A5 JP2012504697A JP2012504697A JP2012523616A5 JP 2012523616 A5 JP2012523616 A5 JP 2012523616A5 JP 2012504697 A JP2012504697 A JP 2012504697A JP 2012504697 A JP2012504697 A JP 2012504697A JP 2012523616 A5 JP2012523616 A5 JP 2012523616A5
- Authority
- JP
- Japan
- Prior art keywords
- debug
- processor
- synchronized
- clock
- request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001360 synchronised effect Effects 0.000 claims 21
- 238000000034 method Methods 0.000 claims 1
- 238000012544 monitoring process Methods 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/420,521 US8275977B2 (en) | 2009-04-08 | 2009-04-08 | Debug signaling in a multiple processor data processing system |
| US12/420,521 | 2009-04-08 | ||
| PCT/US2010/028300 WO2010117618A2 (en) | 2009-04-08 | 2010-03-23 | Debug signaling in a multiple processor data processing system |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2012523616A JP2012523616A (ja) | 2012-10-04 |
| JP2012523616A5 true JP2012523616A5 (enExample) | 2013-05-09 |
| JP5459807B2 JP5459807B2 (ja) | 2014-04-02 |
Family
ID=42935272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012504697A Active JP5459807B2 (ja) | 2009-04-08 | 2010-03-23 | マルチプロセッサデータ処理システムにおけるデバッグシグナリング |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US8275977B2 (enExample) |
| JP (1) | JP5459807B2 (enExample) |
| CN (1) | CN102365624B (enExample) |
| TW (1) | TWI483181B (enExample) |
| WO (1) | WO2010117618A2 (enExample) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5400443B2 (ja) | 2009-03-25 | 2014-01-29 | スパンション エルエルシー | 集積回路、デバッグ回路、デバッグコマンド制御方法 |
| TW201145016A (en) * | 2010-06-15 | 2011-12-16 | Nat Univ Chung Cheng | Non-intrusive debugging framework for parallel software based on super multi-core framework |
| GB2483907A (en) * | 2010-09-24 | 2012-03-28 | Advanced Risc Mach Ltd | Privilege level switching for data processing circuitry when in a debug mode |
| US8700955B2 (en) | 2011-09-22 | 2014-04-15 | Freescale Semiconductor, Inc. | Multi-processor data processing system having synchronized exit from debug mode and method therefor |
| US9110142B2 (en) * | 2011-09-30 | 2015-08-18 | Freescale Semiconductor, Inc. | Methods and apparatus for testing multiple-IC devices |
| US8819485B2 (en) * | 2012-03-12 | 2014-08-26 | Infineon Technologies Ag | Method and system for fault containment |
| JP6360387B2 (ja) * | 2014-08-19 | 2018-07-18 | ルネサスエレクトロニクス株式会社 | プロセッサシステム、エンジン制御システム及び制御方法 |
| CN104484258A (zh) * | 2014-12-05 | 2015-04-01 | 中国航空工业集团公司第六三一研究所 | 一种多处理器的同步调试支持电路 |
| CN106776186B (zh) * | 2016-12-29 | 2020-04-07 | 湖南国科微电子股份有限公司 | 一种多cpu架构下的cpu运行状态调试方法和系统 |
| CN106933721B (zh) * | 2017-02-15 | 2020-06-26 | 北京四方继保自动化股份有限公司 | 一种就地化保护装置串口远程监视方法 |
| US10606764B1 (en) * | 2017-10-02 | 2020-03-31 | Northrop Grumman Systems Corporation | Fault-tolerant embedded root of trust using lockstep processor cores on an FPGA |
| US10528077B2 (en) * | 2017-11-21 | 2020-01-07 | The Boeing Company | Instruction processing alignment system |
| JP6981920B2 (ja) * | 2018-05-25 | 2021-12-17 | ルネサスエレクトロニクス株式会社 | 半導体装置、およびデバッグ方法 |
| JP7073285B2 (ja) * | 2019-01-09 | 2022-05-23 | ルネサスエレクトロニクス株式会社 | 動作検証プログラム、動作同期方法及び異常検出装置 |
| JP7378254B2 (ja) * | 2019-09-19 | 2023-11-13 | キヤノン株式会社 | マルチプロセッサデバイス |
| CN111240834B (zh) * | 2020-01-02 | 2024-02-02 | 北京字节跳动网络技术有限公司 | 任务执行方法、装置、电子设备和存储介质 |
| US12072971B2 (en) * | 2020-10-14 | 2024-08-27 | Mobileye Vision Technologies Ltd. | Secure debugging |
| DE102021211709A1 (de) * | 2021-10-18 | 2023-04-20 | Robert Bosch Gesellschaft mit beschränkter Haftung | Datenverarbeitungsnetzwerk zur Datenverarbeitung |
| US11892505B1 (en) * | 2022-09-15 | 2024-02-06 | Stmicroelectronics International N.V. | Debug and trace circuit in lockstep architectures, associated method, processing system, and apparatus |
Family Cites Families (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5452437A (en) | 1991-11-18 | 1995-09-19 | Motorola, Inc. | Methods of debugging multiprocessor system |
| US5313618A (en) * | 1992-09-03 | 1994-05-17 | Metalink Corp. | Shared bus in-circuit emulator system and method |
| US5537655A (en) * | 1992-09-28 | 1996-07-16 | The Boeing Company | Synchronized fault tolerant reset |
| JPH07261814A (ja) * | 1994-03-16 | 1995-10-13 | Yaskawa Electric Corp | Pcのデュアルシステムにおける割込み同期方法 |
| JP3175757B2 (ja) * | 1996-08-13 | 2001-06-11 | 日本電気株式会社 | デバッグシステム |
| US6145100A (en) * | 1998-03-04 | 2000-11-07 | Advanced Micro Devices, Inc. | Debug interface including timing synchronization logic |
| SE9801678L (sv) * | 1998-05-13 | 1999-11-14 | Axis Ab | Datorchip och datoranordning med förbättrad avlusningsförmåga |
| US6321329B1 (en) * | 1999-05-19 | 2001-11-20 | Arm Limited | Executing debug instructions |
| US6343358B1 (en) * | 1999-05-19 | 2002-01-29 | Arm Limited | Executing multiple debug instructions |
| US6826717B1 (en) | 2000-06-12 | 2004-11-30 | Altera Corporation | Synchronization of hardware and software debuggers |
| US7188063B1 (en) | 2000-10-26 | 2007-03-06 | Cypress Semiconductor Corporation | Capturing test/emulation and enabling real-time debugging using an FPGA for in-circuit emulation |
| US7206733B1 (en) | 2000-10-26 | 2007-04-17 | Cypress Semiconductor Corporation | Host to FPGA interface in an in-circuit emulation system |
| US6675334B2 (en) * | 2001-05-31 | 2004-01-06 | Texas Instruments Incorporated | Apparatus and method for multi-cycle memory access mapped to JTAG finite state machine with external flag for hardware emulation |
| US7774190B1 (en) * | 2001-11-19 | 2010-08-10 | Cypress Semiconductor Corporation | Sleep and stall in an in-circuit emulation system |
| US6993674B2 (en) * | 2001-12-27 | 2006-01-31 | Pacific Design, Inc. | System LSI architecture and method for controlling the clock of a data processing system through the use of instructions |
| EP1398700A1 (de) * | 2002-09-12 | 2004-03-17 | Siemens Aktiengesellschaft | Verfahren und Schaltungsanordnung zur Synchronisation redundanter Verarbeitungseinheiten |
| US7805638B2 (en) * | 2003-06-18 | 2010-09-28 | Nethra Imaging, Inc. | Multi-frequency debug network for a multiprocessor array |
| US20050039074A1 (en) * | 2003-07-09 | 2005-02-17 | Tremblay Glenn A. | Fault resilient/fault tolerant computing |
| US7055117B2 (en) * | 2003-12-29 | 2006-05-30 | Agere Systems, Inc. | System and method for debugging system-on-chips using single or n-cycle stepping |
| US7219265B2 (en) * | 2003-12-29 | 2007-05-15 | Agere Systems Inc. | System and method for debugging system-on-chips |
| US7237144B2 (en) * | 2004-04-06 | 2007-06-26 | Hewlett-Packard Development Company, L.P. | Off-chip lockstep checking |
| DE102004038590A1 (de) | 2004-08-06 | 2006-03-16 | Robert Bosch Gmbh | Verfahren zur Verzögerung von Zugriffen auf Daten und/oder Befehle eines Zweirechnersystems sowie entsprechende Verzögerungseinheit |
| JP2006079142A (ja) * | 2004-09-07 | 2006-03-23 | Fujitsu Ltd | マルチプロセッサ装置 |
| DE102005037222A1 (de) * | 2004-10-25 | 2007-02-15 | Robert Bosch Gmbh | Verfahren und Vorrichtung zur Auswertung eines Signals eines Rechnersystems mit wenigstens zwei Ausführungseinheiten |
| JP4532561B2 (ja) | 2004-10-25 | 2010-08-25 | ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング | マルチプロセッサシステムにおける同期化のための方法および装置 |
| JP2008518301A (ja) | 2004-10-25 | 2008-05-29 | ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング | 少なくとも2つの実行ユニットを有する計算機システムで切替を行うための方法および装置 |
| JP4154610B2 (ja) * | 2004-12-21 | 2008-09-24 | 日本電気株式会社 | フォールトトレラントコンピュータ及びその制御方法 |
| US20060161818A1 (en) * | 2005-01-14 | 2006-07-20 | Ivo Tousek | On-chip hardware debug support units utilizing multiple asynchronous clocks |
| US7549092B2 (en) * | 2005-09-29 | 2009-06-16 | Hynix Semiconductor, Inc. | Output controller with test unit |
| US7293214B2 (en) | 2005-12-02 | 2007-11-06 | Broadcom Corporation | Testable design methodology for clock domain crossing |
| TWI331278B (en) * | 2007-03-14 | 2010-10-01 | Ind Tech Res Inst | Debug method |
-
2009
- 2009-04-08 US US12/420,521 patent/US8275977B2/en active Active
-
2010
- 2010-03-23 WO PCT/US2010/028300 patent/WO2010117618A2/en not_active Ceased
- 2010-03-23 JP JP2012504697A patent/JP5459807B2/ja active Active
- 2010-03-23 CN CN2010800155110A patent/CN102365624B/zh active Active
- 2010-04-06 TW TW099110613A patent/TWI483181B/zh active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2012523616A5 (enExample) | ||
| JP5459807B2 (ja) | マルチプロセッサデータ処理システムにおけるデバッグシグナリング | |
| WO2012170954A3 (en) | Line based image processing and flexible memory system | |
| JP2012099113A5 (ja) | デバッグを実行可能にするデバイス | |
| WO2012088530A3 (en) | Dynamic and idle power reduction sequence using recombinant clock and power gating | |
| JP2015506042A5 (enExample) | ||
| CN103297055A (zh) | 一种采用fpga实现多路串行adc同步的装置 | |
| WO2006085665A3 (en) | Methods and apparatus for synchronizing data access to a local memory in a multi-processor system | |
| JP2017536616A5 (enExample) | ||
| JP2010523022A5 (enExample) | ||
| EP2565782A3 (en) | Slave mode transmit with zero delay for audio interface | |
| WO2023103297A1 (zh) | 一种优化ahb总线数据传输性能的系统、方法及服务器 | |
| JP5501900B2 (ja) | サンプリング機能付きセンサデバイス及びそれを用いたセンサデータ処理システム | |
| JP6272847B2 (ja) | クロック・ドメイン間のデータ転送 | |
| KR20150103905A (ko) | 듀얼 mcu에서 마스터 mcu 및 슬레이브 mcu 전환 방법 및 장치 | |
| ATE423340T1 (de) | Redundantes automatisierungssystem umfassend ein master- und ein stand-by-automatisierungsgerät | |
| WO2016074402A1 (zh) | 信号的传输处理方法及装置、设备 | |
| TWI557644B (zh) | 雙處理器電子裝置及其快速開機啓動的方法 | |
| WO2016127596A1 (zh) | 异步数据传输方法及系统 | |
| CN104731748B (zh) | 多路音频数据采集方法和装置 | |
| CN117807933A (zh) | 一种信号处理方法、装置、芯片及电子设备 | |
| CN111277265A (zh) | 一种基于fpga的多通道da信号同步装置及方法 | |
| JP2013250696A (ja) | プロセッサシステムおよびプロセッサ制御装置 | |
| JP2016062541A5 (enExample) | ||
| CN103646000B (zh) | 一种适用于多路热备份数据传输的高可靠中断处理方法 |