JP2012505553A - 選択的な基板領域メッキを可能とする方法 - Google Patents
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- H—ELECTRICITY
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
- H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
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- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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Abstract
Description
前記基板に第一の電気的伝導層を形成し、
前記第一の電気的導電性層を抗−無電解メッキ層で覆い、
前記抗−無電解メッキ層と前記第一の電気的伝導層とを通して延長する構造を形成するために、前記基板をパターン化し、
前記第一の電気的伝導層に隣接してかつ電気的に結合された、第二の電気的伝導層を形成し、
前記第二の電気的伝導層の上に第三の電気的伝導層を形成し、及び
前記抗−無電解メッキ層と前記第一の電気的伝導層を除去する、ことを含む。前記抗−無電解メッキ層は、例えばポリマー又はセラミックであってよいが、非電気的伝導性であり、以下説明するように、無電解メッキを抑制するものである。
201 基板
210 誘電体層、ビルドアップ層
220 パッド220
310 電気的伝導層
410 抗−無電解メッキ層
501 パターン
510 ビア
520 トレース
610 電気的伝導層
710 電気的伝導層
Claims (20)
- 基板の選択的領域メッキを可能とする方法であり:
前記基板に第一の電気的伝導層を形成し;
前記第一の電気的導電性層を抗−無電解メッキ層で覆い;
前記抗−無電解メッキ層と前記第一の電気的伝導層とを通して延長する構造を形成するために、前記基板をパターン化し;
前記第一の電気的伝導層に隣接してかつ電気的に結合された、第二の電気的伝導層を形成し;
前記第二の電気的伝導層の上に第三の電気的伝導層を形成し;及び
前記抗−無電解メッキ層と前記第一の電気的伝導層を除去すること、を含む方法。 - 請求項1に記載の方法であり:
第一の銅層を第一の無電解メッキプロセスにより形成して、前記基板に第一の電気的伝導層を形成し;
第二の銅層を第二の無電解メッキプロセスにより形成して、前記基板に第二の電気的伝導層を形成し;
前記第一の銅層が、約0.1ミクロン及び約1.0ミクロンの間の第一の厚さを持ち;及び
前記第二の銅層が、ほぼ前記第一の厚さと等しい第二の厚さを持つ、方法。 - 請求項1に記載の方法であり:
前記第一の電気的伝導層の上に、電磁波長に感受性である光感受性ソルダーレジストフィルムをコーティングして、前記第一の電気的伝導層を前記ソルダーレジスト層で覆い;及び
前記光感受性ソルダーレジストフィルムを前記電磁波長に曝露すること、を含む方法。 - ローラーコーティング、スクリーン印刷、スピンコーティング及びスプレーコーティングを含む群から選択される操作により、前記光感受性ソルダーレジストフィルムを前記第一の電気的伝導層にコーティングする、請求項3に記載の方法。
- 前記基板内に構造を形成するために、前記基板内にビアを形成することで前記基板をパターン化する、請求項1に記載の方法。
- 前記基板内に構造を形成するために、さらに前記基板内に埋込みトレースパターンを形成することで前記基板をパターン化する、請求項5に記載の方法
- 前記第三の電気的伝導層形成が、電解メッキプロセスを用いて銅で、前記構造を生めることを含む、請求項1に記載の方法。
- 前記第一の電気的伝導層の除去が、硫酸系溶液を用いた前記第一の電気的伝導層をエッチングして除くことを含む、請求項1に記載の方法。
- 基板の選択的領域メッキを可能とする方法であり:
前記基板に第一の電気的伝導層を形成し;
前記第一の電気的導電性層を疎水性ポリマー層で覆い;
前記疎水性ポリマー層と前記第一の電気的伝導層とを通して延長する構造を形成するために、前記基板をパターン化し;
前記第一の電気的伝導層に隣接してかつ電気的に結合された、第二の電気的伝導層を形成し;
前記第二の電気的伝導層の上に第三の電気的伝導層を形成し;及び
前記疎水性ポリマー層と前記第一の電気的伝導層を除去すること、を含む方法。 - PDMS、PE及びPTFEを含む群から選択されるポリマー材料を適用することで、前記第一の電気的導電性層を前記疎水性ポリマー層で覆う、請求項9に記載の方法。
- 請求項9に記載の方法であり:
第一の銅層を第一の無電解メッキプロセスにより形成して、前記基板に第一の電気的伝導層を形成し;
第二の銅層を第二の無電解メッキプロセスにより形成して、前記基板に第二の電気的伝導層を形成し;
前記第一の銅層が、約0.1ミクロン及び約1.0ミクロンの間の第一の厚さを持ち;及び
前記第二の銅層が、ほぼ前記第一の厚さと等しい第二の厚さを持つ、方法。 - 前記基板内に構造を形成するために、前記基板内にビアを形成することで前記基板をパターン化する、請求項11に記載の方法。
- 前記基板内に構造を形成するために、さらに前記基板内に埋込みトレースパターンを形成することで前記基板をパターン化する、請求項12に記載の方法。
- 前記第三の電気的伝導層形成が、電解メッキプロセスを用いて銅で、前記構造を生めることを含む、請求項14に記載の方法。
- 前記第一の電気的伝導層の除去が、硫酸系溶液を用いた前記第一の電気的伝導層をエッチングして除くことを含む、請求項14に記載の方法。
- 基板の選択的領域メッキを可能とする方法であり:
前記基板に第一の電気的伝導層を形成し;
前記第一の電気的導電性層の上に、プラズマ重合プロセスを用いて炭化水素フィルムを堆積し;
前記炭化水素フィルムと前記第一の電気的伝導層とを通して延長する構造を形成するために、前記基板をパターン化し;
前記第一の電気的伝導層に隣接してかつ電気的に結合された、第二の電気的伝導層を形成し;
前記第二の電気的伝導層の上に第三の電気的伝導層を形成し;及び
前記炭化水素フィルムと前記第一の電気的伝導層を除去すること、を含む方法。 - 請求項16に記載の方法であり:
第一の銅層を第一の無電解メッキプロセスにより形成して、前記基板に第一の電気的伝導層を形成し;
第二の銅層を第二の無電解メッキプロセスにより形成して、前記基板に第二の電気的伝導層を形成し;
前記第一の銅層が、約0.1ミクロン及び約1.0ミクロンの間の第一の厚さを持ち;及び
前記第二の銅層が、ほぼ前記第一の厚さと等しい第二の厚さを持つ、方法。 - 前記基板内に構造を形成するために、前記基板内にビア及び、さらに前記基板内に埋込みトレースパターンを形成することで前記基板をパターン化する、請求項16に記載の方法。
- 電解メッキプロセスを用いて銅で前記構造を生めることで、前記第三の電気的伝導層を形成する、請求項16に記載の方法。
- 硫酸系溶液を用いて前記第一の電気的伝導層を化学的エッチングにより除去して、前記第一の電気的伝導層を除去する、請求項16に記載の方法。
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Application Number | Priority Date | Filing Date | Title |
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US12/315,066 | 2008-11-25 | ||
US12/315,066 US7891091B2 (en) | 2008-11-25 | 2008-11-25 | Method of enabling selective area plating on a substrate |
PCT/US2009/064898 WO2010065301A2 (en) | 2008-11-25 | 2009-11-18 | Method of enabling selective area plating on a substrate |
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JP2012505553A true JP2012505553A (ja) | 2012-03-01 |
JP5722223B2 JP5722223B2 (ja) | 2015-05-20 |
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US (1) | US7891091B2 (ja) |
JP (1) | JP5722223B2 (ja) |
KR (1) | KR101222262B1 (ja) |
CN (1) | CN102171804B (ja) |
TW (1) | TWI412081B (ja) |
WO (1) | WO2010065301A2 (ja) |
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US7891091B2 (en) | 2008-11-25 | 2011-02-22 | Yonggang Li | Method of enabling selective area plating on a substrate |
KR101267277B1 (ko) * | 2011-05-19 | 2013-05-24 | 한국기계연구원 | 유연기판의 금속배선 형성방법 |
CN102392247B (zh) * | 2011-10-26 | 2013-11-06 | 首都航天机械公司 | 一种扩散焊接用零件中间局部区域电镀方法 |
US9224674B2 (en) * | 2011-12-15 | 2015-12-29 | Intel Corporation | Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages |
CN102779905B (zh) * | 2012-08-23 | 2015-04-22 | 马悦 | 一种太阳能电池电极的制备方法 |
US9653419B2 (en) | 2015-04-08 | 2017-05-16 | Intel Corporation | Microelectronic substrate having embedded trace layers with integral attachment structures |
WO2016180944A1 (en) | 2015-05-13 | 2016-11-17 | Atotech Deutschland Gmbh | Method for manufacturing of fine line circuitry |
GB201514501D0 (en) * | 2015-08-14 | 2015-09-30 | Semblant Ltd | Electroless plating method |
US9972575B2 (en) | 2016-03-03 | 2018-05-15 | Applied Materials, Inc. | Hybrid wafer dicing approach using a split beam laser scribing process and plasma etch process |
US9872399B1 (en) | 2016-07-22 | 2018-01-16 | International Business Machines Corporation | Implementing backdrilling elimination utilizing anti-electroplate coating |
GB201621177D0 (en) | 2016-12-13 | 2017-01-25 | Semblant Ltd | Protective coating |
US20200078884A1 (en) * | 2018-09-07 | 2020-03-12 | Intel Corporation | Laser planarization with in-situ surface topography control and method of planarization |
CN110545634A (zh) * | 2019-08-29 | 2019-12-06 | 江苏上达电子有限公司 | 一种先做线路再镀孔铜的多层精细线路板的制作方法 |
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TWI412081B (zh) | 2013-10-11 |
WO2010065301A2 (en) | 2010-06-10 |
CN102171804A (zh) | 2011-08-31 |
US20100126009A1 (en) | 2010-05-27 |
JP5722223B2 (ja) | 2015-05-20 |
CN102171804B (zh) | 2013-08-14 |
TW201029068A (en) | 2010-08-01 |
WO2010065301A3 (en) | 2010-08-12 |
KR101222262B1 (ko) | 2013-01-15 |
KR20110060921A (ko) | 2011-06-08 |
US7891091B2 (en) | 2011-02-22 |
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