JP2012248550A - Wiring board - Google Patents

Wiring board Download PDF

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JP2012248550A
JP2012248550A JP2011116417A JP2011116417A JP2012248550A JP 2012248550 A JP2012248550 A JP 2012248550A JP 2011116417 A JP2011116417 A JP 2011116417A JP 2011116417 A JP2011116417 A JP 2011116417A JP 2012248550 A JP2012248550 A JP 2012248550A
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semiconductor element
element connection
connection pads
wiring
opening
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JP2011116417A
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JP5835725B2 (en
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Kiminori Tada
公則 多田
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Kyocer Slc Tech Corp
Kyocera SLC Technologies Corp
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Kyocer Slc Tech Corp
Kyocera SLC Technologies Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which does not have large differences between heights of metal layers, having been subject to heating and melting treatments, on semiconductor element connection pads and always connects an electrode of a semiconductor element with the semiconductor element connection pads normally.SOLUTION: A wiring board 10 includes: an insulation substrate 1 having a mounting part 1a at a center part on an upper surface; a number of semiconductor element connection pads 4 provided at an outer peripheral part of the mounting part 1a so as to form two lines, an inner side line and an outer side line; a solder resist layer 6 adhered to the upper surface of the insulation substrate 1 and having an opening 6a exposing the two line arrangement of the semiconductor element connection pads 4; an extraction wiring 3c which connects with the semiconductor element connection pads 4 on the inner side line and extends to the outer side of the mounting part 1a passing through the opening 6a; and metal layers 7 adhered to surfaces of the semiconductor element connection pads 4 and having been subject to heating and melting treatments. The extraction wiring 3c connects with the semiconductor element connection pads 4 under the solder resist layer 6 on the inner side relative to the opening 6a.

Description

本発明は、半導体素子を搭載するために用いられる配線基板に関するものである。   The present invention relates to a wiring board used for mounting a semiconductor element.

従来、図４に示すように、下面外周部に電極端子Ｔがペリフェラル配置された半導体素子Ｓをフリップチップ接続により搭載する配線基板２０として、多数のスルーホール１２を有する樹脂系絶縁材料から成る絶縁基板１１の上面の中央部に半導体素子Ｓを搭載するための搭載部１１ａを設けるとともに、絶縁基板１１の上面からスルーホール１２内を介して下面に導出する銅から成る複数の配線導体１３を被着させ、この配線導体１３の一部を搭載部１１ａの外周部において半導体素子Ｓの電極端子Ｔに接続するための半導体素子接続パッド１４として配置するとともに絶縁基板１１の下面において外部電気回路基板と接続するための外部接続パッド１５として配置し、さらに絶縁基板１１の上下面およびスルーホール１２内に半導体素子接続パッド１４および外部接続パッド１５を露出させる開口部１６ａおよび１６ｂを有する樹脂系絶縁材料から成るソルダーレジスト層１６を被着させてなる配線基板２０が知られている。なお、半導体素子Ｓの電極端子Ｔの下端には半導体素子接続パッド１４と接続するための鉛フリー半田から成る半田バンプＢが被着されており、半導体素子接続パッド１４の露出する上面には半田バンプＢとの濡れ性を向上させるための金属層１７が被着されている。金属層１７は、例えば錫めっきから成り、半導体素子接続パッド１４の露出面に電解めっき法により０．５〜５μｍの厚みに被着された後、加熱溶融処理されて高さが２〜２５μｍのドーム状となっている。   Conventionally, as shown in FIG. 4, as a wiring board 20 on which a semiconductor element S having peripherally disposed electrode terminals T on the outer periphery of a lower surface is mounted by flip chip connection, an insulating material made of a resin-based insulating material having a large number of through holes 12 is used. A mounting portion 11 a for mounting the semiconductor element S is provided at the center of the upper surface of the substrate 11, and a plurality of wiring conductors 13 made of copper led out from the upper surface of the insulating substrate 11 to the lower surface through the through holes 12 are covered. A part of the wiring conductor 13 is disposed as a semiconductor element connection pad 14 for connecting to the electrode terminal T of the semiconductor element S on the outer peripheral portion of the mounting portion 11a, and is connected to the external electric circuit board on the lower surface of the insulating substrate 11. The semiconductor element is arranged as an external connection pad 15 for connection, and further in the upper and lower surfaces of the insulating substrate 11 and in the through hole 12. Continued pads 14 and external connection wiring board 20 formed by depositing the solder resist layer 16 made of a resin-based insulating material having openings 16a and 16b to expose the pad 15 is known. A solder bump B made of lead-free solder for connecting to the semiconductor element connection pad 14 is attached to the lower end of the electrode terminal T of the semiconductor element S, and solder is applied to the exposed upper surface of the semiconductor element connection pad 14. A metal layer 17 for improving wettability with the bump B is applied. The metal layer 17 is made of, for example, tin plating, and is applied to the exposed surface of the semiconductor element connection pad 14 to a thickness of 0.5 to 5 μm by an electrolytic plating method, and then heat-melted to have a height of 2 to 25 μm. It has a dome shape.

このような配線基板２０においては、半導体素子接続パッド１４に被着された金属層１７上に半導体素子Ｓの電極端子Ｔを載置し、その状態で半田バンプＢおよび金属層１７を加熱溶融することによって半導体素子Ｓが配線基板２０上に実装される。   In such a wiring board 20, the electrode terminal T of the semiconductor element S is placed on the metal layer 17 attached to the semiconductor element connection pad 14, and the solder bump B and the metal layer 17 are heated and melted in that state. Thus, the semiconductor element S is mounted on the wiring board 20.

ところで、このような配線基板においては、図５に上面図で示すように、多数の半導体素子接続パッド１４が搭載部１１ａの外周部に内側の列と外側の列との２列の並びに設けられることがある。このように２列の並びで設けられた半導体素子接続パッド１４は、ソルダーレジスト１６に設けられた枠状の開口部１６ａ内に露出している。そして一般的に、内側の並びの半導体素子接続パッド１４は搭載部１１ａの内側へ延びる引出配線１３ａにより搭載部１１ａの内側に引き出され、外側の並びの半導体素子接続パッド１４は搭載部１１ａの外側に延びる引出配線１３ｂにより搭載部１１ａの外側に引き出される。しかしながら、内側の列の半導体素子接続パッド１４であっても、搭載部１１ａの内側に引き出すことが設計的に困難である場合、搭載部１１ａの外側に延びる引出配線１３ｃにより搭載部１１ａの外側に引き出されることもある。この場合、内側の列の半導体素子接続パッド１４から搭載部１１ａの外側に延びる引出配線１３ｃはソルダーレジスト層１６の開口部１６ａ内で半導体素子接続パッド１４に接続されて搭載部１１ａの外側に延びていた。   By the way, in such a wiring board, as shown in a top view in FIG. 5, a large number of semiconductor element connection pads 14 are arranged in two rows of an inner row and an outer row on the outer peripheral portion of the mounting portion 11a. Sometimes. Thus, the semiconductor element connection pads 14 provided in two rows are exposed in a frame-shaped opening 16 a provided in the solder resist 16. In general, the semiconductor element connection pads 14 arranged on the inner side are led out to the inside of the mounting part 11a by the lead wiring 13a extending to the inner side of the mounting part 11a, and the semiconductor element connection pads 14 arranged on the outer side are drawn outside the mounting part 11a. The lead wire 13b extends to the outside of the mounting portion 11a. However, even in the case of the semiconductor element connection pads 14 in the inner row, when it is difficult to design the semiconductor element connection pads 14 to the inside of the mounting portion 11a, the lead wires 13c extending to the outside of the mounting portion 11a are provided outside the mounting portion 11a. Sometimes pulled out. In this case, the lead-out wiring 13c extending from the semiconductor element connection pad 14 in the inner row to the outside of the mounting portion 11a is connected to the semiconductor element connection pad 14 in the opening 16a of the solder resist layer 16 and extends to the outside of the mounting portion 11a. It was.

しかしながら、このように内側の列の半導体素子接続パッド１４から搭載部１１ａの外側に延びる引出配線１３ｃがソルダーレジスト層１６の開口部１６ａ内で半導体素子接続パッド１４に接続されて搭載部１１ａの外側に延びている場合、半導体素子接続パッド１４の露出面に例えば錫めっきにより金属層１７を被着させる際に引出配線１３ｃの露出面にも金属層１７が被着されてしまう。そして、これらの露出面に被着された金属層１７を加熱溶融すると、図６に要部拡大上面図で示すように、溶融した金属層１７が半導体素子接続パッド１４と引出配線１３ｃとの接続部Ｘに表面張力により集まってきて、この接続部Ｘにおいて形成されるドーム状の金属層１７の高さが他の半導体素子接続パッド１４のドーム状の金属層１７よりも高くなり大きく異なったものとなってしまう。   However, the lead-out wiring 13c extending from the semiconductor element connection pad 14 in the inner row to the outside of the mounting portion 11a is connected to the semiconductor element connection pad 14 in the opening 16a of the solder resist layer 16 in this way, and is thus outside the mounting portion 11a. When the metal layer 17 is deposited on the exposed surface of the semiconductor element connection pad 14 by, for example, tin plating, the metal layer 17 is also deposited on the exposed surface of the lead wiring 13c. When the metal layer 17 deposited on these exposed surfaces is heated and melted, the melted metal layer 17 is connected to the semiconductor element connection pad 14 and the lead wiring 13c as shown in the enlarged top view of the main part in FIG. The dome-shaped metal layer 17 formed in the connection portion X is gathered at the portion X due to surface tension, and the height of the dome-shaped metal layer 17 formed in the connection portion X is higher than that of the dome-shaped metal layer 17 of the other semiconductor element connection pads 14. End up.

このように、半導体素子接続パッド１４上に形成されたドーム状の金属層１７の高さに大きな違いがあると、半導体素子接続パッド１４の金属層１７上に半導体素子Ｓの電極端子Ｔを載置し、その状態で半田バンプＢおよび金属層１７を加熱溶融することによって半導体素子Ｓを配線基板２０上に実装する際に、半導体素子Ｓの電極端子Ｔの半田バンプＢと半導体素子接続パッド１４の金属層１７とが良好に接触せずに半導体素子Ｓの電極端子Ｔと半導体素子接続パッド１４とを正常に接続することができない場合があった。   Thus, if there is a large difference in the height of the dome-shaped metal layer 17 formed on the semiconductor element connection pad 14, the electrode terminal T of the semiconductor element S is mounted on the metal layer 17 of the semiconductor element connection pad 14. When the semiconductor element S is mounted on the wiring board 20 by heating and melting the solder bump B and the metal layer 17 in that state, the solder bump B and the semiconductor element connection pad 14 of the electrode terminal T of the semiconductor element S are mounted. In some cases, the electrode terminal T of the semiconductor element S and the semiconductor element connection pad 14 cannot be normally connected without being in good contact with the metal layer 17.

特開２００１−１２７１９８号公報JP 2001-127198 A

本発明の課題は、内側の列の半導体素子接続パッドに搭載部の外側に延びる引出配線が接続されている場合であっても、各半導体素子接続パッド上に形成された加熱溶融処理された金属層の高さに大きな違いが無く、それにより半導体素子の電極と半導体素子接続パッドとを常に正常に接続することが可能な配線基板を提供することにある。   An object of the present invention is to provide a heat-melted metal formed on each semiconductor element connection pad even when the lead-out wiring extending outside the mounting portion is connected to the semiconductor element connection pads in the inner row It is an object of the present invention to provide a wiring board capable of always connecting the electrodes of the semiconductor element and the semiconductor element connection pads normally without any significant difference in layer height.

本発明の配線基板は、上面中央部に半導体素子が搭載される搭載部を有する絶縁基板と、前記搭載部の外周部に内側の列と外側の列との２列の並びで設けられた多数の半導体素子接続パッドと、前記絶縁基板の上面に被着されており、前記半導体素子接続パッドの２列の並びを露出させる枠状の開口部を有するソルダーレジスト層と、前記内側の列の半導体素子接続パッドに接続されており、前記開口部内を通って前記搭載部の外側に延びる引出配線と、前記半導体素子接続パッドの表面に被着されており、加熱溶融処理された金属層とを有する配線基板であって、前記引出配線は、前記開口部よりも内側の前記ソルダーレジスト層の下で前記内側の列の半導体素子接続パッドに接続されていることを特徴とするものである。   The wiring board according to the present invention includes an insulating substrate having a mounting portion on which a semiconductor element is mounted at the center on the upper surface, and a plurality of rows arranged in two rows, an inner row and an outer row, on the outer peripheral portion of the mounting portion. Semiconductor element connection pads, a solder resist layer that is attached to the upper surface of the insulating substrate and exposes two rows of the semiconductor element connection pads, and a semiconductor in the inner row A lead wire connected to the element connection pad and extending to the outside of the mounting portion through the opening; and a metal layer that is attached to the surface of the semiconductor element connection pad and is heat-melted. The wiring board is characterized in that the lead-out wiring is connected to the semiconductor element connection pads in the inner row under the solder resist layer inside the opening.

本発明の配線基板によれば、内側の列の半導体素子接続パッドに接続されて搭載部の外側に延びる引出配線は、ソルダーレジスト層の開口部よりも内側のソルダーレジスト層の下で前記半導体素子接続パッドに接続されていることから、半導体素子接続パッドと引出配線との接続部がソルダーレジスト層の開口部内に露出することがない。したがって、内側の列の半導体素子接続パッドに搭載部の外側に延びる引出配線が接続されている場合であっても、各半導体素子接続パッド上に形成された加熱溶融処理された金属層の高さに大きな違いが発生することは無く、それにより半導体素子の電極と半導体素子接続パッドとを常に正常に接続することが可能な配線基板を提供することができる。   According to the wiring board of the present invention, the lead wiring connected to the semiconductor element connection pads in the inner row and extending to the outside of the mounting portion has the semiconductor element under the solder resist layer inside the opening of the solder resist layer. Since it is connected to the connection pad, the connection portion between the semiconductor element connection pad and the lead wiring is not exposed in the opening of the solder resist layer. Therefore, even when the lead-out wiring extending outside the mounting portion is connected to the semiconductor element connection pads in the inner row, the height of the heat-melted metal layer formed on each semiconductor element connection pad Thus, there can be provided a wiring board that can always normally connect the electrode of the semiconductor element and the semiconductor element connection pad.

図１は、本発明の配線基板における実施形態の一例を示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. 図２は、図１に示す配線基板の概略上面図である。FIG. 2 is a schematic top view of the wiring board shown in FIG. 図３は、図２に示す配線基板の要部拡大概略上面図である。FIG. 3 is an enlarged schematic top view of the main part of the wiring board shown in FIG. 図４は、従来の配線基板を示す概略断面図である。FIG. 4 is a schematic cross-sectional view showing a conventional wiring board. 図５は、図４に示す配線基板の概略上面図である。FIG. 5 is a schematic top view of the wiring board shown in FIG. 図６は、図５に示す配線基板の要部概略上面図である。6 is a schematic top view of the main part of the wiring board shown in FIG.

次に、本発明の配線基板について図１〜図３を基にして説明する。図１は、本発明の配線基板の実施形態の一例を示す概略断面図である。図１に示すように、本例の配線基板１０は、主として絶縁基板１と配線導体３とソルダーレジスト層６とから構成されており、その上面中央部に半導体素子Ｓを搭載するための搭載部１ａを有している。絶縁基板１は、例えばガラスクロス基材にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させた厚みが３０〜２００μｍ程度の単層または多層の絶縁層を熱硬化させた樹脂系電気絶縁材料から成り、その上面から下面にかけては直径が５０〜３００μｍ程度のスルーホール２が形成されている。   Next, the wiring board of the present invention will be described with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. As shown in FIG. 1, the wiring substrate 10 of this example is mainly composed of an insulating substrate 1, a wiring conductor 3, and a solder resist layer 6, and a mounting portion for mounting a semiconductor element S on the center of the upper surface thereof. 1a. The insulating substrate 1 is, for example, a resin-based electric material obtained by thermosetting a single-layer or multilayer insulating layer having a thickness of about 30 to 200 μm in which a glass cloth base material is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. A through hole 2 made of an insulating material and having a diameter of about 50 to 300 μm is formed from the upper surface to the lower surface.

絶縁基板１の内部および上下面およびスルーホール２の内壁には、厚みが１０〜２０μｍ程度の銅箔や銅めっき層等の銅から成る配線導体３が被着形成されている。これらの配線導体３のうち絶縁基板１の内部および上下面の所定のもの同士がスルーホール２を介して互いに電気的に接続されている。また、絶縁基板１の上面における配線導体３の一部は、半導体素子Ｓの電極端子Ｔが接続される半導体素子接続パッド４を形成しており、絶縁基板１の下面における配線導体３の一部は外部電気回路基板に接続するための外部接続パッド５を形成している。そして、半導体素子接続パッド４には、半導体素子Ｓの電極端子Ｔが接続され、外部接続パッド５は外部電気回路の配線導体に接続される。なお、半導体素子Ｓの電極端子Ｔには半導体素子接続パッド４と接続するための鉛フリー半田から成る半田バンプＢが被着されており、半導体素子接続パッド４の上面には半田バンプＢとの濡れ性を向上させるための錫めっきから成る金属層７が被着されている。金属層７は、例えば半導体素子接続パッド４の露出面に電解めっき法により０．５〜５μｍの厚みに被着された後、加熱溶融処理されて高さが２〜２５μｍのドーム状となっている。   A wiring conductor 3 made of copper such as a copper foil or a copper plating layer having a thickness of about 10 to 20 μm is deposited on the inside and upper and lower surfaces of the insulating substrate 1 and the inner wall of the through hole 2. Among these wiring conductors 3, predetermined ones on the inside and upper and lower surfaces of the insulating substrate 1 are electrically connected to each other through the through holes 2. Further, a part of the wiring conductor 3 on the upper surface of the insulating substrate 1 forms a semiconductor element connection pad 4 to which the electrode terminal T of the semiconductor element S is connected, and a part of the wiring conductor 3 on the lower surface of the insulating substrate 1. Form external connection pads 5 for connection to an external electric circuit board. Then, the electrode terminal T of the semiconductor element S is connected to the semiconductor element connection pad 4, and the external connection pad 5 is connected to the wiring conductor of the external electric circuit. A solder bump B made of lead-free solder for connecting to the semiconductor element connection pad 4 is attached to the electrode terminal T of the semiconductor element S. The upper surface of the semiconductor element connection pad 4 is connected to the solder bump B. A metal layer 7 made of tin plating for improving wettability is applied. For example, the metal layer 7 is deposited on the exposed surface of the semiconductor element connection pad 4 to a thickness of 0.5 to 5 μm by electrolytic plating, and then heated and melted to form a dome shape with a height of 2 to 25 μm. Yes.

さらに、絶縁基板１の上下面およびスルーホール２の内部には、配線導体３を覆うようにしてソルダーレジスト層６が被着されている。ソルダーレジスト層６は、例えばアクリル変性エポキシ樹脂等の感光性熱硬化性樹脂の硬化物から成り、絶縁基板１の上下面での厚みが１０〜３０μｍ程であり、スルーホール２の内部を充填している。そして上面側のソルダーレジスト層６には、半導体素子接続パッド４を露出させる開口部６ａが形成されているとともに、下面側のソルダーレジスト層６には外部接続パッド５を露出させる開口部６ｂが形成されている。   Further, a solder resist layer 6 is deposited on the upper and lower surfaces of the insulating substrate 1 and inside the through hole 2 so as to cover the wiring conductor 3. The solder resist layer 6 is made of a cured product of a photosensitive thermosetting resin such as an acrylic-modified epoxy resin, and has a thickness on the upper and lower surfaces of the insulating substrate 1 of about 10 to 30 μm and fills the inside of the through hole 2. ing. An opening 6a for exposing the semiconductor element connection pad 4 is formed in the solder resist layer 6 on the upper surface side, and an opening 6b for exposing the external connection pad 5 is formed in the solder resist layer 6 on the lower surface side. Has been.

そして、本例の配線基板１０においては、半導体素子接続パッド４上に半導体素子Ｓの電極端子Ｔを載置し、その状態で半田バンプＢおよび金属層７をを加熱溶融することによって半導体素子Ｓが配線基板１０上に実装される。   In the wiring board 10 of this example, the electrode terminal T of the semiconductor element S is placed on the semiconductor element connection pad 4, and the solder bump B and the metal layer 7 are heated and melted in that state, thereby the semiconductor element S. Is mounted on the wiring board 10.

ところで、本例の配線基板１０においては、図２に上面図で示すように、多数の半導体素子接続パッド４が搭載部１ａの外周部に内側の列と外側の列との２列の並びに設けられている。このように２列の並びで設けられた半導体素子接続パッド４は、ソルダーレジスト６に設けられた枠状の開口部６ａ内に露出している。そして、内側の並びの半導体素子接続パッド４はその殆どが搭載部１ａの内側へ延びる引出配線３ａにより搭載部１ａの内側に引き出され、外側の並びの半導体素子接続パッド４は搭載部１ａの外側に延びる引出配線３ｂにより搭載部１ａの外側に引き出されている。また、内側の列の半導体素子接続パッド４のうち、搭載部１ａの内側に引き出すことが設計的に困難であるものについては、搭載部１ａの外側に延びる引出配線３ｃにより搭載部１ａの外側に引き出されている。   By the way, in the wiring board 10 of this example, as shown in a top view in FIG. 2, a large number of semiconductor element connection pads 4 are arranged in two rows of an inner row and an outer row on the outer periphery of the mounting portion 1a. It has been. The semiconductor element connection pads 4 provided in two rows in this way are exposed in a frame-shaped opening 6 a provided in the solder resist 6. And most of the semiconductor element connection pads 4 on the inner side are drawn out to the inside of the mounting part 1a by the lead wiring 3a extending to the inner side of the mounting part 1a, and the semiconductor element connection pads 4 on the outer side are outside the mounting part 1a. The lead wire 3b extends to the outside of the mounting portion 1a. Among the semiconductor element connection pads 4 in the inner row, those that are difficult to design to the inside of the mounting portion 1a are placed outside the mounting portion 1a by the lead wiring 3c extending to the outside of the mounting portion 1a. Has been pulled out.

このとき、内側の列の半導体素子接続パッド４を搭載部１ａの外側に引き出す引出配線３ｃは、図３に示すように、ソルダーレジスト層６の開口部６ａよりも内側のソルダーレジスト層６の下で半導体素子接続パッド４に電気的に接続されている。そして半導体素子接続パッド４と離間した位置から開口部６ａ内に露出してさらに搭載部１ａの外側に延びている。このように、本例の配線基板１０によれば、内側の列の半導体素子接続パッド４に接続されて搭載部１ａの外側に延びる引出配線３ｃは、ソルダーレジスト層６の開口部６ａよりも内側のソルダーレジスト層６の下で半導体素子接続パッド４に接続されていることから、半導体素子接続パッド４と引出配線３ｃとの接続部がソルダーレジスト層６の開口部６ａ内に露出することがない。したがって、内側の列の半導体素子接続パッド４に搭載部１ａの外側に延びる引出配線３ｃが接続されていても、各半導体素子接続パッド４上に形成された加熱溶融処理された金属層７の高さに大きな違いが発生することは無く、それにより半導体素子Ｓの電極Ｔと半導体素子接続パッド４とを常に正常に接続することが可能な配線基板１０を提供することができる。   At this time, the lead-out wiring 3c for leading the semiconductor element connection pads 4 in the inner row to the outside of the mounting portion 1a is under the solder resist layer 6 inside the opening 6a of the solder resist layer 6, as shown in FIG. Are electrically connected to the semiconductor element connection pads 4. And it exposes in the opening part 6a from the position away from the semiconductor element connection pad 4, and further extends to the outside of the mounting part 1a. As described above, according to the wiring substrate 10 of this example, the lead-out wiring 3c connected to the semiconductor element connection pads 4 in the inner row and extending to the outside of the mounting portion 1a is inside the opening 6a of the solder resist layer 6. Since the semiconductor element connection pad 4 is connected under the solder resist layer 6, the connection portion between the semiconductor element connection pad 4 and the lead-out wiring 3 c is not exposed in the opening 6 a of the solder resist layer 6. . Therefore, even if the lead-out wiring 3c extending to the outside of the mounting portion 1a is connected to the semiconductor element connection pads 4 in the inner row, the height of the heat-melted metal layer 7 formed on each semiconductor element connection pad 4 is increased. Thus, the wiring substrate 10 can be provided in which the electrode T of the semiconductor element S and the semiconductor element connection pad 4 can always be normally connected.

１ 絶縁基板
１ａ 搭載部
３ 配線導体
３ｃ 引出配線
４ 半導体素子接続パッド
６ ソルダーレジスト層
６ａ ソルダーレジスト層の開口部
７ 金属層
Ｓ 半導体素子 DESCRIPTION OF SYMBOLS 1 Insulation board | substrate 1a Mounting part 3 Wiring conductor 3c Lead-out wiring 4 Semiconductor element connection pad 6 Solder resist layer 6a Opening part of solder resist layer 7 Metal layer S Semiconductor element

Claims (1)

上面中央部に半導体素子が搭載される搭載部を有する絶縁基板と、前記搭載部の外周部に内側の列と外側の列との２列の並びで設けられた多数の半導体素子接続パッドと、前記絶縁基板の上面に被着されており、前記半導体素子接続パッドの２列の並びを露出させる枠状の開口部を有するソルダーレジスト層と、前記内側の列の半導体素子接続パッドに接続されており、前記開口部内を通って前記搭載部の外側に延びる引出配線と、前記半導体素子接続パッドの表面に被着されており、加熱溶融処理された金属層とを有する配線基板であって、前記引出配線は、前記開口部よりも内側の前記ソルダーレジスト層の下で前記内側の列の半導体素子接続パッドに接続されていることを特徴とする配線基板。   An insulating substrate having a mounting portion on which a semiconductor element is mounted at the center of the upper surface; and a plurality of semiconductor element connection pads provided on the outer periphery of the mounting portion in two rows of an inner row and an outer row; A solder resist layer having a frame-like opening that exposes the two rows of the semiconductor element connection pads, and is connected to the semiconductor element connection pads in the inner row. A wiring substrate having a lead-out wiring extending outside the mounting portion through the opening and a metal layer that is attached to the surface of the semiconductor element connection pad and is heat-melted, The lead-out wiring is connected to the semiconductor element connection pads in the inner row under the solder resist layer inside the opening.
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