JP2014110266A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board in which disconnection is rarely generated on an extraction wire in an opening on a solder resist layer.SOLUTION: A wiring board 10 consists of an insulation substrate 1 having a mounting part 1a where a semiconductor element S is mounted on its upper surface center; a number of semiconductor element connection pads 5 arranged parallel to each other along an outer periphery of the semiconductor element S on an outer periphery of the mounting part 1a on the insulation substrate 1; an extraction wire 6 extending from semiconductor element connection pads 5 to the center side of the mounting part 1a on the insulation substrate 1; and a solder resist layer 3 applied to the upper surface of the insulation substrate 1 and having an opening 3a which exposes the semiconductor element connection pads 5 and in which its inner peripheral side 3ai gets across the extraction wire 6. The inner peripheral side 3ai has a wavy shape in which a part getting across the extraction wire 6 has a gradient θ of 45 degrees or less with respect to a virtual line L connecting the part to the center of the mounting part 1a.

Description

  The present invention relates to a wiring board used for mounting a semiconductor element.

  2. Description of the Related Art Conventionally, there is known a wiring board on which a semiconductor element having electrode terminals arranged peripherally on the outer periphery of a lower surface is mounted by flip chip connection. An example of such a conventional wiring board 20 is shown in FIGS. A conventional wiring board 20 includes an insulating substrate 11, a wiring conductor 12, and a solder resist 13. In FIG. 4B, a portion of the wiring conductor 12 on the upper surface of the insulating substrate 11 that is covered with the solder resist layer 13 is indicated by a broken line.

  The insulating substrate 11 is made of, for example, an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin, and has a mounting portion 11a for mounting the semiconductor element S on the center of the upper surface thereof. A number of through holes 14 are formed from the upper surface to the lower surface of the insulating substrate 11.

  The wiring conductor 12 is made of a copper foil or a copper plating layer, and is led out from the mounting portion 11 a on the upper surface of the insulating substrate 11 to the lower surface of the insulating substrate 11 through the inner wall of the through hole 14. The wiring conductor 12 on the upper surface of the insulating substrate 11 has a large number of semiconductor element connection pads 15 on the outer periphery of the mounting portion 11a. These semiconductor element connection pads 15 are arranged in two rows along the outer periphery of the semiconductor element S. Further, a lead wiring 16 is connected to each semiconductor element connection pad 15. The lead wiring 16 connected to the semiconductor element connection pad 15 in the inner row extends to the center side of the mounting portion 11a, and the lead wiring 16 connected to the semiconductor element connection pad 15 in the outer row is connected to the mounting portion 11a. It extends outward. Further, the wiring conductor 12 on the lower surface of the insulating substrate 11 has a large number of external connection pads 17. These external connection pads 17 are arranged in a grid on the lower surface of the insulating substrate 11. Corresponding semiconductor element connection pads 15 and external connection pads 17 are electrically connected to each other via lead wires 16 and wiring conductors 12 in the through holes 14.

  The solder resist layer 13 is made of a thermosetting resin such as an epoxy resin, and is attached to the upper and lower surfaces of the insulating substrate 11 and filled in the through holes 14. In the solder resist layer 13, an opening 13 a is formed on the upper surface side of the insulating substrate 11 to expose the semiconductor element connection pad 15 and a part of the lead wiring 16 connected thereto. The opening 13a has a rectangular frame shape along the outer peripheral portion of the mounting portion 11a so as to expose a part of the inner and outer two rows of semiconductor element connection pads 15 and a part of the lead wiring 16 connected thereto. . The solder resist layer 13 is formed with an opening 13 b that exposes the external connection pad 17 on the lower surface side of the insulating substrate 11. The opening 13b has a circular shape that exposes each external connection pad 17 individually.

  According to this conventional wiring board 20, as shown in FIG. 5, the semiconductor element S is arranged on the mounting portion 11a so that the electrode terminals T and the corresponding semiconductor element connection pads 15 face each other. At the same time, the electrode terminal T and the semiconductor element connection pad 15 are connected via solder, and then, from a thermosetting resin in which an inorganic insulating filler such as spherical silica is dispersed between the wiring substrate 20 and the semiconductor element S. The semiconductor element S is mounted on the mounting portion 11a by injecting the sealing resin U to be formed and thermosetting it.

  However, recently, the semiconductor element S has become higher in integration degree and has a large outer size of a few tens of mm square. In the semiconductor element S highly integrated in this way, the size of the electrode terminal T is also as small as 30 μm or less in diameter. For this reason, the widths of the semiconductor element connection pads 15 to which the electrode terminals T are connected and the lead-out wirings 16 connected thereto are also as narrow as 30 μm or less. When such a highly integrated semiconductor element S having a large outer size is mounted on the wiring board 20, the thermal expansion coefficient of the solder resist layer 13 and the thermal expansion coefficient of the sealing resin U are obtained as shown in FIG. Due to the thermal stress generated due to the difference, a crack C may occur between the periphery of the opening 13a of the solder resist layer 13 and the sealing resin U in contact therewith. This is because the thermal expansion coefficient of the sealing resin U containing a large amount of inorganic insulating filler such as spherical silica is smaller than the thermal expansion coefficient of the solder resist layer 13. Therefore, the solder resist layer 13 tends to shrink more than the sealing resin U when the temperature is lowered from the temperature at which the sealing resin U is thermoset to room temperature, and the stress is generated in the periphery of the opening 13a of the solder resist layer 13. It is because it concentrates between sealing resin U which touches this.

  If a crack C occurs between the inner periphery of the opening 13a of the solder resist layer 13 and the sealing resin U in contact therewith, if the heat generated during operation of the semiconductor element S is repeatedly applied to the wiring substrate 20, the crack C C progresses downward. If the lead wiring 16 is positioned below the crack C, the crack C proceeds to the lead wiring 16, and finally the lead wiring 16 can be broken. This disconnection occurs remarkably when the width of the lead-out wiring 16 is as thin as 30 μm or less.

JP 2007-227708 A

  The object of the present invention is to effectively distribute the thermal stress generated between the inner periphery of the opening of the solder resist layer and the sealing resin in contact with it on the lead wiring crossed by the inner periphery of the opening of the solder resist layer. An object of the present invention is to provide a wiring board in which disconnection is unlikely to occur in wiring.

  The wiring board of the present invention is arranged in parallel along the outer periphery of the semiconductor element on the insulating substrate having a mounting portion on which the semiconductor element is mounted at the center of the upper surface, and on the outer peripheral portion of the mounting portion on the insulating substrate. A plurality of semiconductor element connection pads, a lead wire extending from the semiconductor element connection pad toward the central portion of the mounting portion on the insulating substrate, and an upper surface of the insulating substrate. A wiring board comprising a solder resist layer having an opening that exposes a semiconductor element connection pad and has an inner periphery that crosses the lead wire, wherein the inner periphery has a portion that crosses the lead wire and the portion. It is a wave shape having an inclination of 45 degrees or less with respect to an imaginary line connecting the center of the mounting portion.

  According to the wiring board of the present invention, the inner periphery of the opening of the solder resist layer that crosses the lead wiring extending from the semiconductor element connection pad toward the center of the mounting portion has a portion that crosses the lead wiring. Is generated between the inner periphery of the opening of the solder resist layer and the sealing resin in contact with the solder resist layer, since the corrugated shape has an inclination of 45 degrees or less with respect to a virtual line connecting the center of the mounting portion and the mounting portion. Therefore, it is possible to effectively disperse the thermal stress on the lead wiring that the inner periphery of the opening of the solder resist layer crosses, thereby providing a wiring board in which disconnection of the lead wiring is unlikely to occur.

FIG. 1 is a schematic cross-sectional view and a schematic top view illustrating an example of an embodiment of a wiring board according to the present invention. FIG. 2 is a schematic cross-sectional view showing a state in which a semiconductor element is mounted on the wiring board shown in FIG. FIG. 3 is an enlarged schematic top view of the main part of the wiring board shown in FIG. FIG. 4 is a schematic cross-sectional view and a schematic top view showing a conventional wiring board. FIG. 5 is a schematic cross-sectional view showing a state in which a semiconductor element is mounted on the wiring board shown in FIG. FIG. 6 is a schematic cross-sectional view of a main part for explaining problems in the wiring board shown in FIG.

  Next, the wiring board of the present invention will be described with reference to FIGS. 1A and 1B show an example of an embodiment of a wiring board 10 of the present invention. The wiring substrate 10 of this example is mainly composed of an insulating substrate 1, a wiring conductor 2, and a solder resist layer 3. In FIG. 1B, a portion of the wiring conductor 2 on the upper surface of the insulating substrate 1 that is covered with the solder resist layer 3 is indicated by a broken line.

  The insulating substrate 1 is, for example, a resin-based electric material obtained by thermosetting a single-layer or multilayer insulating layer having a thickness of about 30 to 200 μm in which a glass cloth base material is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. It is made of an insulating material and has a mounting portion 1a for mounting the semiconductor element S at the center of the upper surface. Further, a through hole 4 having a diameter of about 50 to 300 μm is formed in the insulating substrate 1 from the upper surface to the lower surface.

  The wiring conductor 2 is made of a copper foil or a copper plating layer, and is led out from the mounting portion 1 a on the upper surface of the insulating substrate 1 to the lower surface of the insulating substrate 1 through the inner wall of the through hole 4. The thickness of the wiring conductor 2 is about 10 to 20 μm. The wiring conductor 2 on the upper surface of the insulating substrate 1 has a large number of semiconductor element connection pads 5 on the outer periphery of the mounting portion 1a. Each semiconductor element connection pad 5 has a width of about 10 to 30 μm and a length of about 20 to 60 μm. These semiconductor element connection pads 5 are arranged in two rows along the outer periphery of the semiconductor element S. Furthermore, a lead wiring 6 is connected to each semiconductor element connection pad 5. The width of the lead wiring 6 is about 10 to 30 μm at the connection portion with the semiconductor element connection pad 5. The lead wiring 6 connected to the semiconductor element connection pad 5 in the inner row extends to the center side of the mounting portion 1a, and the lead wiring 6 connected to the semiconductor element connection pad 5 in the outer row is connected to the mounting portion 1a. It extends outward. The wiring conductor 2 has a large number of external connection pads 7 on the lower surface of the insulating substrate 1. The diameter of the external connection pad 7 is about 200 to 500 μm. These external connection pads 7 are arranged in a grid on the lower surface of the insulating substrate 1. Corresponding semiconductor element connection pads 5 and external connection pads 7 are electrically connected to each other via the lead wiring 6 and the wiring conductor 2 in the through hole 4.

  The solder resist layer 3 is made of a thermosetting resin such as an epoxy resin, is attached to the upper and lower surfaces of the insulating substrate 1 and is filled in the through holes 4. The thickness of the solder resist layer 3 is about 20 to 40 μm at the portions deposited on the upper and lower surfaces of the insulating substrate 1. In the solder resist layer 3, an opening 3 a is formed on the upper surface side of the insulating substrate 1 to expose a part of the semiconductor element connection pad 5 and the lead wiring 6 connected thereto. The opening 3a has a rectangular frame shape along the outer peripheral portion of the mounting portion 1a so as to expose a part of the inner and outer two rows of semiconductor element connection pads 5 and a part of the lead wiring 6 connected thereto. . In addition, the width | variety of the extraction wiring 6 exposed from the opening part 3a is about 10-30 micrometers, and length is about 20-60 micrometers. The solder resist layer 3 is formed with an opening 3 b that exposes the external connection pad 7 on the lower surface side of the insulating substrate 1. The opening 3b has a circular shape that exposes each external connection pad 7 individually.

  According to this wiring board 10, as shown in FIG. 2, the semiconductor element S is arranged on the mounting portion 1a such that each electrode terminal T and the corresponding semiconductor element connection pad 5 face each other and the electrode terminal. T and the semiconductor element connection pad 5 are connected via solder, and then sealed with a thermosetting resin in which an inorganic insulating filler such as spherical silica is dispersed between the wiring board 10 and the semiconductor element S. By injecting the resin U and thermosetting it, the semiconductor element S is mounted on the mounting portion 1a.

  By the way, in the wiring board 10 of this example, as shown in FIG. 3, the inner periphery 3ai of the opening 3a of the solder resist layer 3 is directed from the semiconductor element connection pad 5 in the inner row toward the center of the mounting portion 1a. A portion that crosses the extending lead wire 6 has a wave shape so that it has an inclination θ of 45 degrees or less with respect to a virtual line L that connects this portion and the center of the mounting portion 1a. In this way, the inner periphery 3ai of the opening 3a of the solder resist layer 3 has a portion crossing the lead wire 6 extending from the semiconductor element connection pad 5 in the inner row toward the center of the mounting portion 1a. Since it has a wave shape so as to have an inclination θ of 45 degrees or less with respect to an imaginary line connecting the center of the mounting portion 1a, the opening 3a of the solder resist layer 3 is mounted after mounting the semiconductor element S on the mounting portion 1a. The thermal stress generated between the inner periphery 3ai and the sealing resin U in contact with the inner periphery 3ai can be effectively dispersed on the lead-out wiring 6 traversed by the inner periphery 3ai. Therefore, it is possible to provide the wiring board 10 that is less likely to cause disconnection in the lead-out wiring 6.

  Note that the inner periphery 3ai of the opening 3a of the solder resist layer 3 is the same as the inner periphery 3ai of the opening 3a of the solder resist layer 3 when the inclination θ with respect to the virtual line L in the portion crossing the lead wiring 6 exceeds 45 degrees. There is an increased risk that the thermal stress generated between the sealing resin U and the sealing resin U cannot be effectively dispersed on the lead wiring 6 across the inner periphery 3ai of the opening 3a of the solder resist layer 3. Therefore, the inner periphery 3ai of the opening 3a of the solder resist layer 3 is preferably 45 degrees or less, more preferably 30 degrees or less, with respect to the imaginary line L in the portion crossing the lead-out wiring 6.

DESCRIPTION OF SYMBOLS 1 Insulation board | substrate 1a Mounting part 2 Wiring conductor 3 Solder resist layer 3a Opening part of solder resist layer 3ai Inner periphery of opening part of solder resist layer 5 Semiconductor element connection pad L Virtual line S Semiconductor element (theta) Inclination

Claims (1)

  An insulating substrate having a mounting portion on which the semiconductor element is mounted at the center of the upper surface, and a large number of semiconductor element connection pads arranged in parallel along the outer periphery of the semiconductor element on the outer peripheral portion of the mounting portion on the insulating substrate And a lead wiring extending from the semiconductor element connection pad toward the center of the mounting portion on the insulating substrate, and an upper surface of the insulating substrate, and the semiconductor element connection pad is exposed. And a solder resist layer having an inner periphery having an opening that crosses the lead wire, wherein the inner periphery has a portion that crosses the lead wire and the center of the mounting portion. A wiring board having a corrugated shape having an inclination of 45 degrees or less with respect to a connecting virtual line.

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