JP2014110267A - Wiring board - Google Patents

Wiring board Download PDF

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JP2014110267A
JP2014110267A JP2012262689A JP2012262689A JP2014110267A JP 2014110267 A JP2014110267 A JP 2014110267A JP 2012262689 A JP2012262689 A JP 2012262689A JP 2012262689 A JP2012262689 A JP 2012262689A JP 2014110267 A JP2014110267 A JP 2014110267A
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semiconductor element
wiring
solder resist
element connection
resist layer
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Japanese (ja)
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Kenji Nakamura
憲志 中村
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Kyocera SLC Technologies Corp
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Kyocera SLC Technologies Corp
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Priority to JP2012262689A priority Critical patent/JP2014110267A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board in which disconnection is rarely generated on an extraction wire in an opening on a solder resist layer.SOLUTION: A wiring board consists of an insulation substrate having a mounting part where a semiconductor element is mounted on its upper surface center; a number of semiconductor element connection pads 5 arranged parallel to each other along an outer periphery of the semiconductor element on an outer periphery of the mounting part on the insulation substrate; an extraction wire 6 extending from semiconductor element connection pads 5 to the center side of the mounting part on the insulation substrate; and a solder resist layer 3 applied to the upper surface of the insulation substrate and having an opening 3a which exposes the semiconductor element connection pads 5 and in which its inner peripheral side 3ai gets across the extraction wire 6. The inner peripheral side 3ai has a wavy shape in which a part getting across the extraction wire 6 protrudes toward semiconductor element connection pads 5 side.

Description

本発明は、半導体素子を搭載するために用いられる配線基板に関するものである。   The present invention relates to a wiring board used for mounting a semiconductor element.

従来、下面外周部に電極端子がペリフェラル配置された半導体素子をフリップチップ接続により搭載する配線基板が知られている。このような従来の配線基板２０の例を図４（ａ），（ｂ）に示す。従来の配線基板２０は、絶縁基板１１と配線導体１２とソルダーレジスト１３とを有している。なお、図４（ｂ）においては、絶縁基板１１上面の配線導体１２のうち、ソルダーレジスト層１３で覆われている部分を破線で示している。   2. Description of the Related Art Conventionally, there is known a wiring board on which a semiconductor element having electrode terminals arranged peripherally on the outer periphery of a lower surface is mounted by flip chip connection. An example of such a conventional wiring board 20 is shown in FIGS. A conventional wiring board 20 includes an insulating substrate 11, a wiring conductor 12, and a solder resist 13. In FIG. 4B, a portion of the wiring conductor 12 on the upper surface of the insulating substrate 11 that is covered with the solder resist layer 13 is indicated by a broken line.

絶縁基板１１は、例えばガラスクロスにエポキシ樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料から成り、その上面中央部に半導体素子Ｓを搭載するための搭載部１１ａを有している。また、絶縁基板１１の上面から下面にかけては多数のスルーホール１４が形成されている。   The insulating substrate 11 is made of, for example, an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin, and has a mounting portion 11a for mounting the semiconductor element S on the center of the upper surface thereof. A number of through holes 14 are formed from the upper surface to the lower surface of the insulating substrate 11.

配線導体１２は、銅箔や銅めっき層から成り、絶縁基板１１の上面の搭載部１１ａからスルーホール１４内壁を介して絶縁基板１１の下面に導出している。絶縁基板１１の上面の配線導体１２は、搭載部１１ａの外周部に多数の半導体素子接続パッド１５を有している。これらの半導体素子接続パッド１５は、半導体素子Ｓの外周辺に沿って２列の並びで配置されている。さらに、各半導体素子接続パッド１５には引出配線１６が接続されている。内側の列の半導体素子接続パッド１５に接続された引出配線１６は搭載部１１ａの中央部側に延びており、外側の列の半導体素子接続パッド１５に接続された引出配線１６は搭載部１１ａの外側に延びている。また、絶縁基板１１の下面の配線導体１２は、多数の外部接続パッド１７を有している。これらの外部接続パッド１７は絶縁基板１１の下面に格子状の並び配置されている。そして、半導体素子接続パッド１５と外部接続パッド１７とは、対応するもの同士が引出配線１６およびスルーホール１４内の配線導体１２を介して互いに電気的に接続されている。   The wiring conductor 12 is made of a copper foil or a copper plating layer, and is led out from the mounting portion 11 a on the upper surface of the insulating substrate 11 to the lower surface of the insulating substrate 11 through the inner wall of the through hole 14. The wiring conductor 12 on the upper surface of the insulating substrate 11 has a large number of semiconductor element connection pads 15 on the outer periphery of the mounting portion 11a. These semiconductor element connection pads 15 are arranged in two rows along the outer periphery of the semiconductor element S. Further, a lead wiring 16 is connected to each semiconductor element connection pad 15. The lead wiring 16 connected to the semiconductor element connection pad 15 in the inner row extends to the center side of the mounting portion 11a, and the lead wiring 16 connected to the semiconductor element connection pad 15 in the outer row is connected to the mounting portion 11a. It extends outward. Further, the wiring conductor 12 on the lower surface of the insulating substrate 11 has a large number of external connection pads 17. These external connection pads 17 are arranged in a grid on the lower surface of the insulating substrate 11. Corresponding semiconductor element connection pads 15 and external connection pads 17 are electrically connected to each other via lead wires 16 and wiring conductors 12 in the through holes 14.

ソルダーレジスト層１３は、エポキシ樹脂等の熱硬化性樹脂から成り、絶縁基板１１の上下面に被着されているとともにスルーホール１４内に充填されている。ソルダーレジスト層１３には、絶縁基板１１の上面側において半導体素子接続パッド１５およびこれに接続された引出配線１６の一部を露出させる開口部１３ａが形成されている。開口部１３ａは、内外２列の半導体素子接続パッド１５およびこれらに接続された引出配線１６の一部を一括して露出させるように搭載部１１ａの外周部に沿った方形枠状をしている。また、ソルダーレジスト層１３には、絶縁基板１１の下面側において外部接続パッド１７を露出させる開口部１３ｂが形成されている。開口部１３ｂは、各外部接続パッド１７を個別に露出させる円形をしている。   The solder resist layer 13 is made of a thermosetting resin such as an epoxy resin, and is attached to the upper and lower surfaces of the insulating substrate 11 and filled in the through holes 14. In the solder resist layer 13, an opening 13 a is formed on the upper surface side of the insulating substrate 11 to expose the semiconductor element connection pad 15 and a part of the lead wiring 16 connected thereto. The opening 13a has a rectangular frame shape along the outer peripheral portion of the mounting portion 11a so as to expose a part of the inner and outer two rows of semiconductor element connection pads 15 and a part of the lead wiring 16 connected thereto. . The solder resist layer 13 is formed with an opening 13 b that exposes the external connection pad 17 on the lower surface side of the insulating substrate 11. The opening 13b has a circular shape that exposes each external connection pad 17 individually.

そして、この従来の配線基板２０によれば、図５に示すように、搭載部１１ａ上に半導体素子Ｓを、その各電極端子Ｔと対応する半導体素子接続パッド１５とが向かい合うようにして配置するとともに電極端子Ｔと半導体素子接続パッド１５とを半田を介して接続し、しかる後、配線基板２０と半導体素子Ｓとの間に球状シリカ等の無機絶縁物フィラーが分散された熱硬化性樹脂から成る封止樹脂Ｕを注入するとともに熱硬化させることにより、半導体素子Ｓが搭載部１１ａ上に実装されることとなる。   According to this conventional wiring board 20, as shown in FIG. 5, the semiconductor element S is arranged on the mounting portion 11a so that the electrode terminals T and the corresponding semiconductor element connection pads 15 face each other. At the same time, the electrode terminal T and the semiconductor element connection pad 15 are connected via solder, and then, from a thermosetting resin in which an inorganic insulating filler such as spherical silica is dispersed between the wiring substrate 20 and the semiconductor element S. The semiconductor element S is mounted on the mounting portion 11a by injecting the sealing resin U to be formed and thermosetting it.

しかしながら、近時、半導体素子Ｓは、その集積度が高くなるとともに外形サイズも１０数ｍｍ角と大きなものが現れてきている。このように高集積化された半導体素子Ｓにおいては、電極端子Ｔの大きさも直径３０μｍ以下と小さくなっている。そのため、電極端子Ｔが接続される半導体素子接続パッド１５およびこれに接続される引出配線１６の幅も３０μｍ以下と細いものになってきている。そして、このような高集積化され、かつ外形サイズの大きな半導体素子Ｓを配線基板２０に実装すると、図６に示すように、ソルダーレジスト層１３の熱膨張係数と封止樹脂Ｕの熱膨張係数の差に起因して発生する熱応力によって、ソルダーレジスト層１３の開口部１３ａ内周辺とこれに接する封止樹脂Ｕとの間にクラックＣが発生してしまうことがある。これは球状シリカ等の無機絶縁フィラーを多く含む封止樹脂Ｕの熱膨張係数がソルダーレジスト層１３の熱膨張係数よりも小さくなっていることによる。そのため、封止樹脂Ｕを熱硬化させる温度から室温に下がる際にソルダーレジスト層１３の方が、封止樹脂Ｕよりも大きく収縮しようとし、その応力がソルダーレジスト層１３の開口部１３ａ内周辺とこれに接する封止樹脂Ｕとの間に集中するためである。   However, recently, the semiconductor element S has become higher in integration degree and has a large outer size of a few tens of mm square. In the semiconductor element S highly integrated in this way, the size of the electrode terminal T is also as small as 30 μm or less in diameter. For this reason, the widths of the semiconductor element connection pads 15 to which the electrode terminals T are connected and the lead-out wirings 16 connected thereto are also as narrow as 30 μm or less. When such a highly integrated semiconductor element S having a large outer size is mounted on the wiring board 20, the thermal expansion coefficient of the solder resist layer 13 and the thermal expansion coefficient of the sealing resin U are obtained as shown in FIG. Due to the thermal stress generated due to the difference, a crack C may occur between the periphery of the opening 13a of the solder resist layer 13 and the sealing resin U in contact therewith. This is because the thermal expansion coefficient of the sealing resin U containing a large amount of inorganic insulating filler such as spherical silica is smaller than the thermal expansion coefficient of the solder resist layer 13. Therefore, the solder resist layer 13 tends to shrink more than the sealing resin U when the temperature is lowered from the temperature at which the sealing resin U is thermoset to room temperature, and the stress is generated in the periphery of the opening 13a of the solder resist layer 13. It is because it concentrates between sealing resin U which touches this.

ソルダーレジスト層１３の開口部１３ａ内周辺とこれに接する封止樹脂Ｕとの間にクラックＣが発生した場合、半導体素子Ｓが作動時に発生する熱が配線基板２０に繰り返し加えられると、そのクラックＣが下方に進行してしまう。そして、このクラックＣの下方に引出配線１６が位置していると、クラックＣが引出配線１６にまで進行し、ついにはその引出配線１６に断線をもたらせてしまう。この断線は、引出配線１６の幅が３０μｍ以下と細い場合に顕著に発生する。   If a crack C occurs between the inner periphery of the opening 13a of the solder resist layer 13 and the sealing resin U in contact therewith, if the heat generated during operation of the semiconductor element S is repeatedly applied to the wiring substrate 20, the crack C C progresses downward. If the lead wiring 16 is positioned below the crack C, the crack C proceeds to the lead wiring 16, and finally the lead wiring 16 can be broken. This disconnection occurs remarkably when the width of the lead-out wiring 16 is as thin as 30 μm or less.

特開２００７−２２７７０８号公報JP 2007-227708 A

本発明の課題は、ソルダーレジスト層の開口部内周辺とこれに接する封止樹脂との間に発生する熱応力をソルダーレジスト層の開口部内周辺が横切る引出配線上において有効に分散させることにより、引出配線に断線が発生しにくい配線基板を提供することにある。   The object of the present invention is to effectively distribute the thermal stress generated between the inner periphery of the opening of the solder resist layer and the sealing resin in contact with it on the lead wiring crossed by the inner periphery of the opening of the solder resist layer. An object of the present invention is to provide a wiring board in which disconnection is unlikely to occur in wiring.

本発明の配線基板は、上面中央部に半導体素子が搭載される搭載部を有する絶縁基板と、該絶縁基板上における前記搭載部の外周部に、前記半導体素子の外周辺に沿って並設された多数の半導体素子接続パッドと、前記絶縁基板上を前記半導体素子接続パッドから前記搭載部の中央部側に向けて延在する引出配線と、前記絶縁基板の上面に被着されており、前記半導体素子接続パッドを露出させるとともに内周辺が前記引出配線を横切る開口部を有するソルダーレジスト層とを具備して成る配線基板であって、前記内周辺は、前記引出配線を横切る部分が前記半導体素子接続パッド側に向けて凸状となる波型形状であることを特徴とするものである。   The wiring board of the present invention is arranged in parallel along the outer periphery of the semiconductor element on the insulating substrate having a mounting portion on which the semiconductor element is mounted at the center of the upper surface, and on the outer peripheral portion of the mounting portion on the insulating substrate. A plurality of semiconductor element connection pads, a lead wire extending from the semiconductor element connection pad toward the central portion of the mounting portion on the insulating substrate, and an upper surface of the insulating substrate. A wiring substrate comprising a solder resist layer having an opening that exposes a semiconductor element connection pad and has an inner periphery that crosses the lead wire, wherein the inner periphery has a portion that crosses the lead wire. The corrugated shape is convex toward the connection pad side.

本発明の配線基板によれば、半導体素子接続パッドから搭載部の中央部に向けて延在する引出配線を横切るソルダーレジスト層の開口部の内周辺は、前記引出配線を横切る部分が前記半導体素子接続パッド側に向けて凸状となる波型形状であることから、ソルダーレジスト層の開口部の内周辺とこれに接する封止樹脂との間に発生する熱応力をソルダーレジスト層の開口部の内周辺が横切る引出配線上において有効に分散させることができ、それにより、引出配線に断線が発生しにくい配線基板を提供することができる。   According to the wiring board of the present invention, the inner periphery of the opening of the solder resist layer that crosses the lead wiring extending from the semiconductor element connection pad toward the central portion of the mounting portion has a portion that crosses the lead wiring. Since it has a corrugated shape that is convex toward the connection pad side, the thermal stress generated between the inner periphery of the opening of the solder resist layer and the sealing resin in contact with the inner periphery of the opening of the solder resist layer It is possible to effectively disperse the lead wiring that is traversed by the inner periphery, thereby providing a wiring board in which disconnection is unlikely to occur in the lead wiring.

図１は、本発明の配線基板における実施形態の一例を示す概略断面図および概略上面図である。FIG. 1 is a schematic cross-sectional view and a schematic top view illustrating an example of an embodiment of a wiring board according to the present invention. 図２は、図１に示す配線基板に半導体素子を実装した状態を示す概略断面図である。FIG. 2 is a schematic cross-sectional view showing a state in which a semiconductor element is mounted on the wiring board shown in FIG. 図３は、図１に示す配線基板の要部拡大概略上面図である。FIG. 3 is an enlarged schematic top view of the main part of the wiring board shown in FIG. 図４は、従来の配線基板を示す概略断面図および概略上面図である。FIG. 4 is a schematic cross-sectional view and a schematic top view showing a conventional wiring board. 図５は、図４に示す配線基板に半導体素子を実装した状態を示す概略断面図である。FIG. 5 is a schematic cross-sectional view showing a state in which a semiconductor element is mounted on the wiring board shown in FIG. 図６は、図４に示す配線基板における問題点を説明するための要部概略断面図である。FIG. 6 is a schematic cross-sectional view of a main part for explaining problems in the wiring board shown in FIG.

次に、本発明の配線基板について、図１〜図３を基にして説明する。図１（ａ），（ｂ）に本発明の配線基板１０の実施形態の一例を示す。本例の配線基板１０は、主として絶縁基板１と配線導体２とソルダーレジスト層３とから構成されている。なお、図１（ｂ）においては、絶縁基板１上面の配線導体２のうち、ソルダーレジスト層３で覆われている部分を破線で示している。   Next, the wiring board of the present invention will be described with reference to FIGS. 1A and 1B show an example of an embodiment of a wiring board 10 of the present invention. The wiring substrate 10 of this example is mainly composed of an insulating substrate 1, a wiring conductor 2, and a solder resist layer 3. In FIG. 1B, a portion of the wiring conductor 2 on the upper surface of the insulating substrate 1 that is covered with the solder resist layer 3 is indicated by a broken line.

絶縁基板１は、例えばガラスクロス基材にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させた厚みが３０〜２００μｍ程度の単層または多層の絶縁層を熱硬化させた樹脂系電気絶縁材料から成り、その上面中央部に半導体素子Ｓを搭載するための搭載部１ａを有している。また、絶縁基板1には、その上面から下面にかけて直径が５０〜３００μｍ程度のスルーホール４が形成されている。   The insulating substrate 1 is, for example, a resin-based electric material obtained by thermosetting a single-layer or multilayer insulating layer having a thickness of about 30 to 200 μm in which a glass cloth base material is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. It is made of an insulating material and has a mounting portion 1a for mounting the semiconductor element S at the center of the upper surface. Further, a through hole 4 having a diameter of about 50 to 300 μm is formed in the insulating substrate 1 from the upper surface to the lower surface.

配線導体２は、銅箔や銅めっき層から成り、絶縁基板１の上面の搭載部１ａからスルーホール４内壁を介して絶縁基板１の下面に導出している。配線導体２の厚みは、１０〜２０μｍ程度である。絶縁基板１の上面の配線導体２は、搭載部１ａの外周部に多数の半導体素子接続パッド５を有している。各半導体素子接続パッド５の大きさは幅が１０〜３０μｍ程度、長さが２０〜６０μｍ程度である。これらの半導体素子接続パッド５は、半導体素子Ｓの外周辺に沿って２列の並びで配置されている。さらに、各半導体素子接続パッド５には引出配線６が接続されている。引出配線６の幅は半導体素子接続パッド５との接続部で１０〜３０μｍ程度である。内側の列の半導体素子接続パッド５に接続された引出配線６は搭載部１ａの中央部側に延びており、外側の列の半導体素子接続パッド５に接続された引出配線６は搭載部１ａの外側に延びている。また、絶縁基板１の下面に配線導体２は、多数の外部接続パッド７を有している。外部接続パッド７の直径は２００〜５００μｍ程度である。これらの外部接続パッド７は絶縁基板１の下面に格子状の並び配置されている。そして、半導体素子接続パッド５と外部接続パッド７とは、対応するもの同士が引出配線６およびスルーホール４内の配線導体２を介して互いに電気的に接続されている。   The wiring conductor 2 is made of a copper foil or a copper plating layer, and is led out from the mounting portion 1 a on the upper surface of the insulating substrate 1 to the lower surface of the insulating substrate 1 through the inner wall of the through hole 4. The thickness of the wiring conductor 2 is about 10 to 20 μm. The wiring conductor 2 on the upper surface of the insulating substrate 1 has a large number of semiconductor element connection pads 5 on the outer periphery of the mounting portion 1a. Each semiconductor element connection pad 5 has a width of about 10 to 30 μm and a length of about 20 to 60 μm. These semiconductor element connection pads 5 are arranged in two rows along the outer periphery of the semiconductor element S. Furthermore, a lead wiring 6 is connected to each semiconductor element connection pad 5. The width of the lead wiring 6 is about 10 to 30 μm at the connection portion with the semiconductor element connection pad 5. The lead wiring 6 connected to the semiconductor element connection pad 5 in the inner row extends to the center side of the mounting portion 1a, and the lead wiring 6 connected to the semiconductor element connection pad 5 in the outer row is connected to the mounting portion 1a. It extends outward. The wiring conductor 2 has a large number of external connection pads 7 on the lower surface of the insulating substrate 1. The diameter of the external connection pad 7 is about 200 to 500 μm. These external connection pads 7 are arranged in a grid on the lower surface of the insulating substrate 1. Corresponding semiconductor element connection pads 5 and external connection pads 7 are electrically connected to each other via the lead wiring 6 and the wiring conductor 2 in the through hole 4.

ソルダーレジスト層３は、エポキシ樹脂等の熱硬化性樹脂から成り、絶縁基板１の上下面に被着されているとともにスルーホール４内に充填されている。ソルダーレジスト層３の厚みは絶縁基板１の上下面に被着された部分で２０〜４０μｍ程度である。ソルダーレジスト層３には、絶縁基板１の上面側において半導体素子接続パッド５およびこれに接続された引出配線６の一部を露出させる開口部３ａが形成されている。開口部３ａは、内外２列の半導体素子接続パッド５およびこれらに接続された引出配線６の一部を一括して露出させるように搭載部１ａの外周部に沿った方形枠状をしている。なお、開口部３ａから露出する引出配線６の幅は１０〜３０μｍ程度、長さは２０〜６０μｍ程度である。また、ソルダーレジスト層３には、絶縁基板１の下面側において外部接続パッド７を露出させる開口部３ｂが形成されている。開口部３ｂは、各外部接続パッド７を個別に露出させる円形をしている。   The solder resist layer 3 is made of a thermosetting resin such as an epoxy resin, is attached to the upper and lower surfaces of the insulating substrate 1 and is filled in the through holes 4. The thickness of the solder resist layer 3 is about 20 to 40 μm at the portions deposited on the upper and lower surfaces of the insulating substrate 1. In the solder resist layer 3, an opening 3 a is formed on the upper surface side of the insulating substrate 1 to expose a part of the semiconductor element connection pad 5 and the lead wiring 6 connected thereto. The opening 3a has a rectangular frame shape along the outer peripheral portion of the mounting portion 1a so as to expose a part of the inner and outer two rows of semiconductor element connection pads 5 and a part of the lead wiring 6 connected thereto. . In addition, the width | variety of the extraction wiring 6 exposed from the opening part 3a is about 10-30 micrometers, and length is about 20-60 micrometers. The solder resist layer 3 is formed with an opening 3 b that exposes the external connection pad 7 on the lower surface side of the insulating substrate 1. The opening 3b has a circular shape that exposes each external connection pad 7 individually.

そして、この配線基板１０によれば、図２に示すように、搭載部１ａ上に半導体素子Ｓを、各電極端子Ｔと対応する半導体素子接続パッド５とが向かい合うようにして配置するとともに電極端子Ｔと半導体素子接続パッド５とを半田を介して接続し、しかる後、配線基板１０と半導体素子Ｓとの間に球状シリカ等の無機絶縁物フィラーが分散された熱硬化性樹脂から成る封止樹脂Ｕを注入するとともに熱硬化させることにより、半導体素子Ｓが搭載部１ａ上に実装されることとなる。   According to this wiring board 10, as shown in FIG. 2, the semiconductor element S is arranged on the mounting portion 1a such that each electrode terminal T and the corresponding semiconductor element connection pad 5 face each other and the electrode terminal. T and the semiconductor element connection pad 5 are connected via solder, and then sealed with a thermosetting resin in which an inorganic insulating filler such as spherical silica is dispersed between the wiring board 10 and the semiconductor element S. By injecting the resin U and thermosetting it, the semiconductor element S is mounted on the mounting portion 1a.

ところで本例の配線基板１０においては、図３（ａ），（ｂ）に示すように、ソルダーレジスト層３の開口部３ａの内周辺３ａｉは、内側の列の半導体素子接続パッド５から搭載部１ａの中央部に向けて延在する引出配線６を横切る部分が半導体素子接続パッド５側に向けて凸状となる波型形状となっている。このようにソルダーレジスト層３の開口部３ａの内周辺３ａｉは、内側の列の半導体素子接続パッド５から搭載部１ａの中央部に向けて延在する引出配線６を横切る部分が半導体素子接続パッド５側に向けて凸状となる波型形状となっていることから、搭載部１ａに半導体素子Ｓを実装後、ソルダーレジスト層３の開口部３ａの内周辺３ａｉとこれに接する封止樹脂Ｕとの間に発生する熱応力を、内周辺３ａｉが横切る引出配線上６において有効に分散させることができる。したがって、それにより引出配線６に断線が発生しにくい配線基板１０を提供することができる。   By the way, in the wiring board 10 of this example, as shown in FIGS. 3A and 3B, the inner periphery 3ai of the opening 3a of the solder resist layer 3 extends from the semiconductor element connection pad 5 in the inner row to the mounting portion. A portion traversing the lead-out wiring 6 extending toward the center of 1a has a wave shape that is convex toward the semiconductor element connection pad 5 side. As described above, the inner periphery 3ai of the opening 3a of the solder resist layer 3 is such that a portion crossing the lead-out wiring 6 extending from the semiconductor element connection pad 5 in the inner row toward the center of the mounting portion 1a is the semiconductor element connection pad. Since the semiconductor element S is mounted on the mounting portion 1a, the inner periphery 3ai of the opening 3a of the solder resist layer 3 and the sealing resin U in contact with the inner periphery 3ai are formed because the corrugated shape is convex toward the side 5. The thermal stress generated between the inner periphery 3ai and the inner periphery 3ai can be effectively dispersed on the lead wiring 6 across the inner periphery 3ai. Therefore, it is possible to provide the wiring board 10 that is less likely to cause disconnection in the lead-out wiring 6.

なお、ソルダーレジスト層３の開口部３ａの内周辺３ａｉは、図３（ｂ）に示すように、引出配線６を横切る部分における凸形状が各内周辺３ａｉの端部に近づくに従って端部側に傾くようにすると、ソルダーレジスト層３の内周辺３ａｉとこれに接する封止樹脂Ｕとの間に発生する熱応力を、ソルダーレジスト層３の開口部３ａの内周辺３ａｉが横切る引出配線６上においてさらに有効に分散させることができる。したがって、ソルダーレジスト層３の開口部３ａの内周辺３ａｉは、引出配線６を横切る部分における凸形状が各内周辺３ａｉの端部に近づくに従って端部側に傾くようにすることが好ましい。   As shown in FIG. 3B, the inner periphery 3ai of the opening 3a of the solder resist layer 3 is closer to the end as the convex shape in the portion crossing the lead-out wiring 6 approaches the end of each inner periphery 3ai. When inclined, the thermal stress generated between the inner periphery 3ai of the solder resist layer 3 and the sealing resin U in contact with the solder resist layer 3 on the lead-out wiring 6 that the inner periphery 3ai of the opening 3a of the solder resist layer 3 crosses. Further, it can be dispersed effectively. Therefore, it is preferable that the inner periphery 3ai of the opening 3a of the solder resist layer 3 is inclined toward the end as the convex shape in the portion crossing the lead-out wiring 6 approaches the end of each inner periphery 3ai.

１ 絶縁基板
１ａ 搭載部
２ 配線導体
３ ソルダーレジスト層
３ａ ソルダーレジスト層の開口部
３ａｉ ソルダーレジスト層の開口部の内周辺
５ 半導体素子接続パッド
Ｓ 半導体素子 DESCRIPTION OF SYMBOLS 1 Insulation board | substrate 1a Mounting part 2 Wiring conductor 3 Solder resist layer 3a Opening part of solder resist layer 3ai Inner periphery of opening part of solder resist layer 5 Semiconductor element connection pad S Semiconductor element

Claims (1)

上面中央部に半導体素子が搭載される搭載部を有する絶縁基板と、該絶縁基板上における前記搭載部の外周部に、前記半導体素子の外周辺に沿って並設された多数の半導体素子接続パッドと、前記絶縁基板上を前記半導体素子接続パッドから前記搭載部の中央部側に向けて延在する引出配線と、前記絶縁基板の上面に被着されており、前記半導体素子接続パッドを露出させるとともに内周辺が前記引出配線を横切る開口部を有するソルダーレジスト層とを具備して成る配線基板であって、前記内周辺は、前記引出配線を横切る部分が前記半導体素子接続パッド側に向けて凸状となる波型形状であることを特徴とする配線基板。   An insulating substrate having a mounting portion on which the semiconductor element is mounted at the center of the upper surface, and a large number of semiconductor element connection pads arranged in parallel along the outer periphery of the semiconductor element on the outer peripheral portion of the mounting portion on the insulating substrate And a lead wiring extending from the semiconductor element connection pad toward the center of the mounting portion on the insulating substrate, and an upper surface of the insulating substrate, and the semiconductor element connection pad is exposed. And a solder resist layer having an inner periphery having an opening that crosses the lead wire, and the inner periphery has a portion that crosses the lead wire protruding toward the semiconductor element connection pad side. A wiring board having a corrugated shape.
JP2012262689A 2012-11-30 2012-11-30 Wiring board Pending JP2014110267A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111696945A (en) * 2019-03-14 2020-09-22 东芝存储器株式会社 Semiconductor device with a plurality of semiconductor chips

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111696945A (en) * 2019-03-14 2020-09-22 东芝存储器株式会社 Semiconductor device with a plurality of semiconductor chips
US10985153B2 (en) 2019-03-14 2021-04-20 Toshiba Memory Corporation Semiconductor device
CN111696945B (en) * 2019-03-14 2023-10-27 铠侠股份有限公司 Semiconductor device with a semiconductor device having a plurality of semiconductor chips

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