JP2012156303A - Manufacturing method for silicon epitaxial wafer - Google Patents
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 52
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 52
- 239000010703 silicon Substances 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000013078 crystal Substances 0.000 claims abstract description 26
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 9
- 239000011574 phosphorus Substances 0.000 claims abstract description 9
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 7
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract description 7
- 238000010030 laminating Methods 0.000 claims 1
- 238000009826 distribution Methods 0.000 abstract description 28
- 235000012431 wafers Nutrition 0.000 description 45
- 239000007789 gas Substances 0.000 description 22
- 238000000034 method Methods 0.000 description 14
- 230000000052 comparative effect Effects 0.000 description 8
- 238000001947 vapour-phase growth Methods 0.000 description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 7
- 238000004140 cleaning Methods 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 3
- 239000005052 trichlorosilane Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000010943 off-gassing Methods 0.000 description 1
- 235000012771 pancakes Nutrition 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
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- H01L21/02367—Substrates
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- H01L21/02381—Silicon, silicon germanium, germanium
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- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
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- C30B29/06—Silicon
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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- H01L21/02532—Silicon, silicon germanium, germanium
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
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Abstract
Description
本発明は、シリコン単結晶基板上にシリコン単結晶をエピタキシャル成長させて、エピタキシャル層を積層するシリコンエピタキシャルウェーハの製造方法に関する。 The present invention relates to a method for manufacturing a silicon epitaxial wafer in which a silicon single crystal is epitaxially grown on a silicon single crystal substrate and an epitaxial layer is laminated.
シリコンエピタキシャルウェーハ（以下単に「エピタキシャルウェーハ」と称す）は、例えば以下の通りにして製造される。 A silicon epitaxial wafer (hereinafter simply referred to as “epitaxial wafer”) is manufactured, for example, as follows.
すなわち、シリコン単結晶基板を気相成長装置の反応容器内に載置し、水素ガスを流した状態で、１０００℃〜１２００℃まで反応容器内を昇温する（昇温工程）。反応容器内の温度が１０００℃以上になると、基板表面に形成されている自然酸化膜（ＳｉＯ２：Ｓｉｌｉｃｏｎ Ｄｉｏｘｉｄｅ）が除去される。この状態で、トリクロロシラン（ＳｉＨＣｌ３：Ｔｒｉｃｈｌｏｒｏｓｉｌａｎｅ）等のシリコン原料ガス、ジボラン（Ｂ２Ｈ６：Ｄｉｂｏｒａｎｅ）あるいはホスフィン（ＰＨ３：Ｐｈｏｓｐｈｉｎｅ）、アルシン（ＡｓＨ３：Ａｒｓｉｎｅ） 等のドーパントガスを、水素ガスとともにプロセスガスとして反応容器内に供給する。こうして基板の主表面にエピタキシャル層を気相成長させる（エピ成長工程）。
このようにしてエピタキシャル層を気相成長させた後に、シリコン原料ガスおよびドーパントガスの供給を停止し、水素雰囲気に保持したまま反応容器内の温度を降温させる（冷却工程）。
That is, a silicon single crystal substrate is placed in a reaction vessel of a vapor phase growth apparatus, and the temperature in the reaction vessel is raised to 1000 ° C. to 1200 ° C. in a state where hydrogen gas is flown (temperature raising step). When the temperature in the reaction vessel reaches 1000 ° C. or higher, the natural oxide film (SiO 2 : Silicon Dioxide) formed on the substrate surface is removed. In this state, a silicon source gas such as trichlorosilane (SiHCl 3 : Trichlorosilane), a dopant gas such as diborane (B 2 H 6 : Diborane) or phosphine (PH 3 : Phosphine), arsine (AsH 3 : Arsine), and the like It is supplied into the reaction vessel as a process gas together with the gas. In this way, the epitaxial layer is vapor-phase grown on the main surface of the substrate (epi growth process).
After vapor phase growth of the epitaxial layer in this manner, the supply of the silicon source gas and the dopant gas is stopped, and the temperature in the reaction vessel is lowered while maintaining the hydrogen atmosphere (cooling step).
このようにして製造されたエピタキシャルウェーハに対する品質について、エピタキシャル層の膜厚と抵抗率のウェーハ面内の均一性（以下「膜厚分布」と「抵抗分布」と称す）の向上がデバイスメーカーから要求されている。この中で抵抗分布についてのタイト化の要求が強い。 Regarding the quality of epitaxial wafers manufactured in this way, device manufacturers are required to improve the uniformity of the film thickness and resistivity of the epitaxial layer within the wafer surface (hereinafter referred to as “film thickness distribution” and “resistance distribution”). Has been. Among these, there is a strong demand for tightening the resistance distribution.
ところで、上述の通りにエピタキシャルウェーハを製造する過程の内、エピ成長工程では（１）成長温度、（２）シリコン原料ガス供給量、（３）反応圧力の３要素が重要であり、意図的に調整することができる。これら３要素がエピタキシャルウェーハの面内で均一であれば膜厚分布、抵抗分布が最良になる。
しかし、上記以外に抵抗分布に関する重要な、意図的に変える事が出来ない要素として、基板から発生する（４）アウトガスがある。抵抗分布とアウトガスの関係について以下に説明をする。
By the way, in the process of manufacturing an epitaxial wafer as described above, three elements of (1) growth temperature, (2) silicon source gas supply amount, and (3) reaction pressure are important in the epitaxial growth process. Can be adjusted. If these three elements are uniform in the plane of the epitaxial wafer, the film thickness distribution and resistance distribution are the best.
However, in addition to the above, an important factor regarding the resistance distribution that cannot be changed intentionally is (4) outgas generated from the substrate. The relationship between resistance distribution and outgas will be described below.
エピ成長工程では、１０００℃以上の高い温度で基板がアニールされる為、基板よりドーパントを含むアウトガスが発生する。アウトガスは特に基板裏面から発生し、表面側に回り込む。表面での気相成長はプロセスガスによって行われているが、基板裏面から回り込んできたアウトガスがプロセスガスに混ざり、成長中のエピタキシャル層に取り込まれる（今後、「オートドープ」と称す）。
従って、製造されたエピタキシャルウェーハの中心部分とエッジ部とで取り込まれたドーパント量に違いが生じ、このようなオートドープは、アウトガスが多くなる低抵抗（概ね１０．０ｍΩ・ｃｍ以下）の基板を用いた場合に影響が顕著になる。
In the epi-growth process, the substrate is annealed at a high temperature of 1000 ° C. or higher, so outgas containing dopant is generated from the substrate. Outgas is generated particularly from the back surface of the substrate and goes around to the front surface side. Vapor phase growth on the surface is performed by a process gas, but the outgas that has entered from the back of the substrate is mixed with the process gas and taken into the growing epitaxial layer (hereinafter referred to as “auto-dope”).
Therefore, a difference occurs in the amount of dopant taken in between the central portion and the edge portion of the manufactured epitaxial wafer, and such auto-doping is a low-resistance (approximately 10.0 mΩ · cm or less) substrate that increases outgassing. When used, the effect becomes significant.
このようなオートドープを低減させるために、従来において、処理炉内のガス流速を２ｍ／分以上、あるいはガス置換回数を３回／分以上の層流のキャリアガスを流下させる方法（特許文献１）等が取られてきたが、オートドープ量を大幅に低減させることは非常に困難であった。 In order to reduce such auto-doping, conventionally, a laminar carrier gas having a gas flow rate of 2 m / min or more in the processing furnace or a gas replacement frequency of 3 times / min or more is flowed down (Patent Document 1). However, it has been very difficult to significantly reduce the amount of autodope.
また、低耐圧Ｐ−ＭＯＳデバイス用途に、シリコン単結晶基板を非常に低抵抗率にしたエピタキシャルウェーハの要求が高まっている。中でも赤リンを多量にドープしたＣＺ結晶をエピタキシャル基板にした、Ｎ／Ｎ＋＋＋（５×１０１９ａｔｏｍｓ／ｃｍ３程度）エピタキシャルウェーハがこれからの主流として注目されている。
しかし、リンはＳｉ中での拡散係数が高い為、エピ成長工程での熱処理で簡単に拡散してしまい、裏面からのオートドープによってエピタキシャル層の抵抗率低下や遷移領域のプロファイルにダレが起きやすいという問題があった。
In addition, for low voltage P-MOS device applications, there is an increasing demand for an epitaxial wafer having a very low resistivity silicon single crystal substrate. In particular, N / N ++++ (about 5 × 10 19 atoms / cm 3 ) epitaxial wafers using CZ crystals doped with a large amount of red phosphorus as an epitaxial substrate have attracted attention as a mainstream in the future.
However, since phosphorus has a high diffusion coefficient in Si, it is easily diffused by heat treatment in the epi-growth process, and auto-doping from the back surface tends to cause a decrease in the resistivity of the epitaxial layer and a transition region profile. There was a problem.
そこで、本発明はこのような問題点に鑑みなされたもので、エピタキシャル成長中におけるシリコン単結晶基板からエピタキシャル層へのオートドープ量を抑制し、抵抗分布及び膜厚分布の良好なエピタキシャルウェーハを得ることができるシリコンエピタキシャルウェーハの製造方法を提供することを目的とする。 Therefore, the present invention has been made in view of such problems, and suppresses the amount of autodoping from the silicon single crystal substrate to the epitaxial layer during epitaxial growth, thereby obtaining an epitaxial wafer having a good resistance distribution and film thickness distribution. It is an object of the present invention to provide a method for producing a silicon epitaxial wafer capable of achieving the above.
上記課題を解決するため、本発明では、シリコン単結晶基板上にシリコン単結晶をエピタキシャル成長させて、エピタキシャル層を積層するシリコンエピタキシャルウェーハの製造方法において、抵抗率が０．５ｍΩ・ｃｍ以上１０．０ｍΩ・ｃｍ以下であり、リンまたはヒ素がドープされている前記シリコン単結晶基板上に、成長速度を３μｍ／分以上１５μｍ／分以下として、抵抗率が０．５Ω・ｃｍ以上２０００Ω・ｃｍ以下である前記エピタキシャル層を成長させることを特徴とするシリコンエピタキシャルウェーハの製造方法を提供する。 In order to solve the above problems, in the present invention, in a method for manufacturing a silicon epitaxial wafer in which a silicon single crystal is epitaxially grown on a silicon single crystal substrate and an epitaxial layer is laminated, the resistivity is 0.5 mΩ · cm or more and 10.0 mΩ. The resistivity is 0.5 Ω · cm or more and 2000 Ω · cm or less on the silicon single crystal substrate doped with phosphorus or arsenic at a growth rate of 3 μm / min or more and 15 μm / min or less. A method for producing a silicon epitaxial wafer is provided, wherein the epitaxial layer is grown.
このようなシリコンエピタキシャルウェーハの製造方法であれば、赤リンをドープした基板やヒ素をドープした基板など非常に低抵抗であり、オートドープの影響を大きく受けやすい基板を用いた場合であっても、その影響を最小限に抑えることができ、抵抗分布及び膜厚分布の良好なエピタキシャルウェーハを製造することができる。さらに、エピタキシャル層の成長速度を３μｍ／分以上の高速度としているため、生産性及び歩留まりの向上を図ることができる。また、成長速度を１５μｍ／分以下とすることで、エピタキシャル成長を阻害するＨＣｌガスがシリコン原料ガスと水素ガスの反応により発生することを抑制でき、安定したエピタキシャル成長ができる。
また、このようにシリコン単結晶基板の抵抗率が０．５ｍΩ・ｃｍ以上１０．０ｍΩ・ｃｍ以下であり、その上に形成されたエピタキシャル層の抵抗率が０．５Ω・ｃｍ以上２０００Ω・ｃｍ以下であるようなエピタキシャルウェーハであれば、特にオートドープによる影響を受けやすいため、本発明の製造方法が好適である。
With such a method of manufacturing a silicon epitaxial wafer, even if a substrate having a very low resistance, such as a substrate doped with red phosphorus or a substrate doped with arsenic, is easily affected by autodoping. The influence can be suppressed to the minimum, and an epitaxial wafer having a good resistance distribution and film thickness distribution can be manufactured. Furthermore, since the growth rate of the epitaxial layer is set to a high rate of 3 μm / min or more, productivity and yield can be improved. Moreover, by setting the growth rate to 15 μm / min or less, it is possible to suppress generation of HCl gas that inhibits epitaxial growth due to the reaction between the silicon source gas and hydrogen gas, and stable epitaxial growth can be achieved.
Further, the resistivity of the silicon single crystal substrate is 0.5 mΩ · cm to 10.0 mΩ · cm, and the resistivity of the epitaxial layer formed thereon is 0.5 Ω · cm to 2000 Ω · cm. If it is such an epitaxial wafer, since it is easy to be influenced especially by auto dope, the manufacturing method of this invention is suitable.
またこのとき、前記エピタキシャル成長を行う際の成長温度を、１０００℃以上とすることが好ましい。 At this time, it is preferable that the growth temperature at the time of the epitaxial growth is 1000 ° C. or higher.
このような成長温度であれば、シリコン単結晶基板上の自然酸化膜を確実に除去することができ、シリコン単結晶基板上に膜厚分布のより良好なエピタキシャルウェーハを得ることができる。 With such a growth temperature, the natural oxide film on the silicon single crystal substrate can be surely removed, and an epitaxial wafer with a better film thickness distribution can be obtained on the silicon single crystal substrate.
またこのとき、前記エピタキシャル層の成長速度を、５μｍ／分以上１５μｍ／分以下とすることが好ましい。 At this time, the growth rate of the epitaxial layer is preferably 5 μm / min or more and 15 μm / min or less.
このような成長速度であれば、より効果的にオートドープを抑制することができ、抵抗分布及び膜厚分布のより良好なエピタキシャルウェーハを安定して得ることができる。 With such a growth rate, autodoping can be more effectively suppressed, and an epitaxial wafer having a better resistance distribution and film thickness distribution can be stably obtained.
またこのとき、エピタキシャル成長中における、前記シリコン単結晶基板からエピタキシャル層へのオートドープ量と、前記エピタキシャル層の成長速度との相関関係を予め求め、該相関から前記エピタキシャル層の成長速度を決定することができる。 Also, at this time, during the epitaxial growth, a correlation between the amount of auto-doping from the silicon single crystal substrate to the epitaxial layer and the growth rate of the epitaxial layer is obtained in advance, and the growth rate of the epitaxial layer is determined from the correlation. Can do.
このようにすれば、エピタキシャルウェーハの中央部及びエッジ部の抵抗分布及び膜厚分布を、より効率良く均一にできる成長速度でエピタキシャル成長を行うことができるため、必要以上にシリコン原料ガスやキャリアガスを流入させたり、炉内温度を上げ過ぎてしまったりすることを防止でき、抵抗分布及び膜厚分布のより良好なエピタキシャルウェーハを確実に製造しつつ、さらにコストダウンすることができる。 In this way, since the epitaxial growth can be performed at a growth rate capable of making the resistance distribution and the film thickness distribution in the central portion and the edge portion of the epitaxial wafer more uniform and more efficient, the silicon source gas and the carrier gas can be added more than necessary. It is possible to prevent inflow or excessive increase in the furnace temperature, and further reduce the cost while reliably manufacturing an epitaxial wafer having a better resistance distribution and film thickness distribution.
以上説明したように、本発明によれば、エピタキシャル成長中のオートドープを効果的に抑制することができ、これによって抵抗分布及び膜厚分布の良好なエピタキシャルウェーハを製造することができる。
また、エピタキシャル層の成長速度を高速度としてエピタキシャル成長を行うため、生産性及び歩留まりを向上させることができる。
As described above, according to the present invention, autodoping during epitaxial growth can be effectively suppressed, and thereby an epitaxial wafer having a good resistance distribution and film thickness distribution can be manufactured.
In addition, since epitaxial growth is performed at a high growth rate of the epitaxial layer, productivity and yield can be improved.
以下、図４のフローチャートを参照して、本発明の実施形態であるシリコンエピタキシャルウェーハの製造方法を説明するが、本発明はこれに限定されるものではない。図４は、本発明のシリコンエピタキシャルウェーハの製造方法の一例のフローチャートを示した図である。
ここでは、エピタキシャル層の成長温度を変化させずにシリコン原料ガスを増加させて高速成長させる場合について述べるが、もちろんシリコン原料ガスの量は変化させずに成長温度を上げて成長させても良いし、シリコン原料ガスを増加させた上でさらに成長温度を上げても良い。
Hereinafter, although the manufacturing method of the silicon epitaxial wafer which is embodiment of this invention is demonstrated with reference to the flowchart of FIG. 4, this invention is not limited to this. FIG. 4 is a view showing a flowchart of an example of the method for producing a silicon epitaxial wafer of the present invention.
Here, the case where the silicon source gas is increased without changing the growth temperature of the epitaxial layer for high-speed growth will be described. Of course, the growth may be performed at a higher growth temperature without changing the amount of the silicon source gas. The growth temperature may be further increased after increasing the silicon source gas.
先ず、気相成長装置の反応容器内に備えられたサセプタ上に搬送装置を用いて、抵抗率が０．５ｍΩ・ｃｍ以上１０．０ｍΩ・ｃｍ以下で、リンがドープされたシリコン単結晶基板を載置する（仕込み工程）。このとき、シリコン単結晶基板は赤リンをドープしたＣＺ結晶より製造されたものが好適である。また、リンの代わりにヒ素をドープしても良い。
次いで、反応容器内に水素ガスを流した状態で、反応容器内の温度を、エピタキシャル層を気相成長させるための成長温度まで昇温する（昇温工程）。この成長温度は、基板表面の自然酸化膜を水素で確実に除去できる１０００℃以上に設定する。
First, using a transfer device on a susceptor provided in a reaction vessel of a vapor phase growth apparatus, a silicon single crystal substrate doped with phosphorus having a resistivity of 0.5 mΩ · cm to 10.0 mΩ · cm is used. Place (preparation process). At this time, the silicon single crystal substrate is preferably manufactured from a CZ crystal doped with red phosphorus. Further, arsenic may be doped instead of phosphorus.
Next, with the hydrogen gas flowing in the reaction vessel, the temperature in the reaction vessel is raised to a growth temperature for vapor-phase growth of the epitaxial layer (temperature raising step). This growth temperature is set to 1000 ° C. or higher at which the natural oxide film on the substrate surface can be removed with hydrogen.
次いで、反応容器内を成長温度に保持したままで、水素ガスとともにシリコン原料ガスおよびドーパントガスをそれぞれ所定流量で供給し、成長速度を３μｍ／分以上１５μｍ／分以下、より好ましくは５μｍ／分以上１５μｍ／分以下、さらに好ましくは６μｍ／分以上１５μｍ／分以下で、所定膜厚となるまで抵抗率が０．５Ω・ｃｍ以上２０００Ω・ｃｍ以下となるエピタキシャル層を成長させる（エピ成長工程）。通常の成長速度から高速成長にする場合、成長温度によって異なるが、シリコン原料ガスを通常に比べ、１．５倍〜４．０倍に増加させる。
本発明においては、１０００℃以上の高温であっても、３μｍ／分以上１５μｍ／分以下の成長速度でエピタキシャル層を高速成長させるため、基板にドープされているドーパントのオートドープ量を抑制し、抵抗分布及び膜厚分布の良好なエピタキシャル層を安定して成長させることができる。
Next, while keeping the inside of the reaction vessel at the growth temperature, the silicon raw material gas and the dopant gas are supplied at a predetermined flow rate together with the hydrogen gas, and the growth rate is 3 μm / min to 15 μm / min, more preferably 5 μm / min or more. An epitaxial layer having a resistivity of 0.5 Ω · cm to 2000 Ω · cm is grown at 15 μm / min or less, more preferably 6 μm / min or more and 15 μm / min or less until the film thickness reaches a predetermined thickness (epi growth process). When changing from a normal growth rate to a high-speed growth, although depending on the growth temperature, the silicon source gas is increased 1.5 times to 4.0 times compared to the normal growth rate.
In the present invention, the epitaxial layer is grown at a high growth rate of 3 μm / min or more and 15 μm / min or less even at a high temperature of 1000 ° C. or higher. An epitaxial layer having a good resistance distribution and film thickness distribution can be stably grown.
また、ここで基板からエピタキシャル層へのオートドープ量と、エピタキシャル層の成長速度との相関関係を予め求めておいて、該相関を基に成長速度を決定しても良い。
例えば、抵抗率が２．０ｍΩ・ｃｍであって、リンがドープされたシリコン単結晶基板上に、成長温度を１１００℃として、シリコン原料ガスであるトリクロロシランガスの流量を変化させることによって、成長速度を１〜９μｍ／分の間で変化させてエピタキシャル層を積層した。このときに得られたエピタキシャルウェーハのオートドープ量をそれぞれ測定した結果、オートドープ量と成長速度との間に図１に示すような相関が得られた。
Further, here, a correlation between the amount of autodope from the substrate to the epitaxial layer and the growth rate of the epitaxial layer may be obtained in advance, and the growth rate may be determined based on the correlation.
For example, on a silicon single crystal substrate having a resistivity of 2.0 mΩ · cm and doped with phosphorus, the growth temperature is set to 1100 ° C., and the growth rate is changed by changing the flow rate of trichlorosilane gas, which is a silicon source gas. Was changed between 1 to 9 μm / min to deposit an epitaxial layer. As a result of measuring the autodoping amount of the epitaxial wafer obtained at this time, a correlation as shown in FIG. 1 was obtained between the autodoping amount and the growth rate.
この相関を基に成長速度を決定する場合、例えば３μｍ／分以上とすれば、２μｍ／分以下の通常の成長速度でエピタキシャル成長を行った場合と比べ、オートドープ量が抑制されることがわかる。また５μｍ／分以上とすれば、より効果的にオートドープ量が抑制され、さらに６μｍ／分以上とすれば、オートドープがほとんど生じず、エピタキシャルウェーハのエッジ部と中心部とでは抵抗率にほとんど差が無くなり、抵抗分布及び膜厚分布がほぼ均一化されることがわかる。 When the growth rate is determined based on this correlation, for example, if it is 3 μm / min or more, it can be seen that the amount of autodoping is suppressed as compared with the case where epitaxial growth is performed at a normal growth rate of 2 μm / min or less. Further, if it is 5 μm / min or more, the amount of auto-doping is suppressed more effectively, and if it is 6 μm / min or more, auto-doping hardly occurs, and the resistivity at the edge portion and the center portion of the epitaxial wafer is hardly increased. It can be seen that the difference disappears and the resistance distribution and the film thickness distribution are almost uniform.
次いで、反応容器内の温度を下降させて取り出し温度までエピタキシャルウェーハを冷却する（冷却工程）。この冷却工程では、８００℃から４００℃程度の間で、水素雰囲気から窒素雰囲気へと切り換えられる。そして、窒素雰囲気のままで取り出し温度に至ったら、気相成長装置からエピタキシャルウェーハを取り出す（取り出し工程）。 Next, the temperature in the reaction vessel is lowered to cool the epitaxial wafer to the take-out temperature (cooling step). In this cooling step, the hydrogen atmosphere is switched to the nitrogen atmosphere between about 800 ° C. and 400 ° C. And if it takes out temperature in nitrogen atmosphere, an epitaxial wafer will be taken out from a vapor phase growth apparatus (takeout process).
次いで、取り出したエピタキシャルウェーハに対し、適宜ＲＣＡ洗浄等の洗浄を行う（洗浄工程）。この洗浄工程における洗浄法は、典型的なＲＣＡ洗浄の他、薬液の濃度や種類を通常行われる範囲で変更したものを用いることもできる。 Next, the extracted epitaxial wafer is appropriately cleaned such as RCA cleaning (cleaning step). As a cleaning method in this cleaning step, in addition to a typical RCA cleaning, a method in which the concentration and type of a chemical solution are changed within a normal range can be used.
そして、パーティクルカウンタにより、エピタキシャルウェーハ表面に生成するパーティクル状の異物の有無を確認し（パーティクルカウンタ計測）、その後製品となるエピタキシャルウェーハを選別する（選別）。 Then, the presence or absence of particle-like foreign matter generated on the surface of the epitaxial wafer is confirmed by a particle counter (particle counter measurement), and then an epitaxial wafer to be a product is sorted (sorting).
以下、実施例及び比較例を示して本発明をより具体的に説明するが、本発明はこれに限定されるものではない。 EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to this.
（実施例１）
抵抗率が１．０ｍΩ・ｃｍであって、リンがドープされた直径２００ｍｍのシリコン単結晶基板上に、抵抗率１．５Ω・ｃｍ、膜厚１μｍのエピタキシャル層を、成長温度１１００℃、成長速度を６μｍ／分として高速成長させ、エピタキシャルウェーハを製造した。その後、製造したエピタキシャルウェーハの抵抗率を径方向に測定した。このときの結果を図２に示す。
Example 1
An epitaxial layer having a resistivity of 1.5 Ω · cm and a thickness of 1 μm is grown on a silicon single crystal substrate having a resistivity of 1.0 mΩ · cm and doped with phosphorus and having a diameter of 200 mm, with a growth temperature of 1100 ° C. and a growth rate. Was grown at a high speed of 6 μm / min to produce an epitaxial wafer. Thereafter, the resistivity of the manufactured epitaxial wafer was measured in the radial direction. The result at this time is shown in FIG.
（実施例２）
抵抗率が２．０ｍΩ・ｃｍであって、ヒ素がドープされた直径２００ｍｍのシリコン単結晶基板上に、抵抗率２．０Ω・ｃｍ、膜厚１μｍのエピタキシャル層を、成長温度１１００℃、成長速度を６μｍ／分として高速成長させ、エピタキシャルウェーハを製造した。その後、製造したエピタキシャルウェーハの抵抗率を径方向に測定した。このときの結果を図３に示す。
(Example 2)
An epitaxial layer having a resistivity of 2.0 Ω · cm and a thickness of 1 μm on a silicon single crystal substrate having a resistivity of 2.0 mΩ · cm and doped with arsenic and having a diameter of 200 mm is grown at a growth temperature of 1100 ° C. and a growth rate. Was grown at a high speed of 6 μm / min to produce an epitaxial wafer. Thereafter, the resistivity of the manufactured epitaxial wafer was measured in the radial direction. The result at this time is shown in FIG.
（比較例１）
成長速度を２μｍ／分とすること以外は実施例１と同様にエピタキシャルウェーハを製造し、その後、製造したエピタキシャルウェーハの抵抗率を径方向に測定した。このときの結果を図２に合わせて示す。
(Comparative Example 1)
An epitaxial wafer was manufactured in the same manner as in Example 1 except that the growth rate was 2 μm / min, and then the resistivity of the manufactured epitaxial wafer was measured in the radial direction. The results at this time are also shown in FIG.
（比較例２）
成長速度を２μｍ／分とすること以外は実施例２と同様にエピタキシャルウェーハを製造し、その後、製造したエピタキシャルウェーハの抵抗率を径方向に測定した。このときの結果を図３に合わせて示す。
(Comparative Example 2)
An epitaxial wafer was manufactured in the same manner as in Example 2 except that the growth rate was 2 μm / min, and then the resistivity of the manufactured epitaxial wafer was measured in the radial direction. The results at this time are also shown in FIG.
比較例１及び比較例２に示した条件でエピタキシャル成長を行った場合、１０００℃以上の高温状態で、低抵抗基板上に高抵抗のエピタキシャル層を２μｍ／分の通常の成長速度で形成するため、基板にドープされているリンまたはヒ素が拡散し、オートドープの影響を受けやすい。このため、比較例１及び比較例２では、製造されたエピタキシャルウェーハのエッジ部の抵抗率が極端に下がってしまっている。
しかし、本発明の製造方法を用いた実施例１及び実施例２では、６μｍ／分の成長速度でエピタキシャル層を高速成長させているため、発生するオートドープ量を抑制することができる。このため、製造されたエピタキシャルウェーハのエッジ部と中心部とで抵抗率がほぼ均一化されているのがわかる。
When epitaxial growth is performed under the conditions shown in Comparative Examples 1 and 2, in order to form a high resistance epitaxial layer on a low resistance substrate at a normal growth rate of 2 μm / min at a high temperature of 1000 ° C. or higher, Phosphorus or arsenic doped in the substrate diffuses and is susceptible to autodoping. For this reason, in the comparative example 1 and the comparative example 2, the resistivity of the edge part of the manufactured epitaxial wafer has fallen extremely.
However, in Example 1 and Example 2 using the manufacturing method of the present invention, since the epitaxial layer is grown at a high growth rate of 6 μm / min, the amount of autodope generated can be suppressed. For this reason, it can be seen that the resistivity is substantially uniform at the edge and the center of the manufactured epitaxial wafer.
なお、本発明は、上記実施形態に限定されるものではない。例えば、本発明でエピタキシャル層を気相成長させる気相成長装置は限定されず、縦型（パンケーキ型）、バレル型（シリンダ型）、枚葉式等の各種気相成長装置に適用可能である。上記実施形態は、例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。 The present invention is not limited to the above embodiment. For example, the vapor phase growth apparatus for vapor growth of the epitaxial layer in the present invention is not limited, and can be applied to various vapor phase growth apparatuses such as a vertical type (pancake type), a barrel type (cylinder type), and a single wafer type. is there. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.
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| JPH08236458A (en) * | 1995-02-24 | 1996-09-13 | Sumitomo Sitix Corp | Manufacture of semiconductor substrate |
| JP2009176784A (en) * | 2008-01-22 | 2009-08-06 | Covalent Materials Tokuyama Corp | Method of manufacturing thin film epitaxial wafer |
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| JPH08236458A (en) * | 1995-02-24 | 1996-09-13 | Sumitomo Sitix Corp | Manufacture of semiconductor substrate |
| JP2009176784A (en) * | 2008-01-22 | 2009-08-06 | Covalent Materials Tokuyama Corp | Method of manufacturing thin film epitaxial wafer |
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| JP2017195273A (en) * | 2016-04-20 | 2017-10-26 | 信越半導体株式会社 | Epitaxial wafer manufacturing method |
| WO2017183277A1 (en) * | 2016-04-20 | 2017-10-26 | 信越半導体株式会社 | Method for producing epitaxial wafer |
| KR20180134907A (en) | 2016-04-20 | 2018-12-19 | 신에쯔 한도타이 가부시키가이샤 | Method for manufacturing an epitaxial wafer |
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