JPH08236458A - Manufacture of semiconductor substrate - Google Patents

Manufacture of semiconductor substrate

Info

Publication number
JPH08236458A
JPH08236458A JP6190295A JP6190295A JPH08236458A JP H08236458 A JPH08236458 A JP H08236458A JP 6190295 A JP6190295 A JP 6190295A JP 6190295 A JP6190295 A JP 6190295A JP H08236458 A JPH08236458 A JP H08236458A
Authority
JP
Japan
Prior art keywords
gas
substrate
reaction temperature
speed
flow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6190295A
Other languages
Japanese (ja)
Inventor
Takeshi Kii
健 紀伊
Hideki Nishihata
秀樹 西畑
Geinoa Kurea
ゲイノア クレア
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Sumitomo Sitix Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Sitix Corp filed Critical Sumitomo Sitix Corp
Priority to JP6190295A priority Critical patent/JPH08236458A/en
Publication of JPH08236458A publication Critical patent/JPH08236458A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase the crystal growing speed by the epitaxial growth method by using trichlorosilane as a qaseous starting material and flowing down a carrier gas in a treating furnace at a flow velocity faster than a specific value or in a high-speed laminar flow having a number of inert gas replacing times larger than a specific value so that the reaction temperature can be maintained at a specific value, CONSTITUTION: A crystal layer is grown by epitaxial growth on a single-crystal silicon substrate having a fine pattern in which an impurity is buried and diffused and a crystal axis of <100>0±1 deg.. SiCl4 is used as a gaseous starting material and a carrier gas is made to flow down in a treating furnace at a flow velocity of 2m/min or in a high-speed laminar flow having a number of inert gas replacing times of 3 times/min. The reaction temperature is maintained at 1,150±10 deg.C. The reason why the flow velocity of the carrier gas in the treating furnace is specified is to prevent the stagnation of the gaseous starting material by the high-speed laminar flow so that the occurrence of local etching and deposition can be eliminated and the reaction can be stabilized and accelerated.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体装置、特にB
ip−IC、BiCMOS用等の半導体集積回路用単結
晶シリコン基板の製造方法に係り、特定結晶軸を有する
シリコン単結晶基板にエピタキシャル成長するに際し、
SiHCl3またはSiCl4を原材料ガスとして、特定
成長温度に保持し、従来よりはるかに高速かつ層流のキ
ャリアガスを流下させることにより、SiHCl3(ト
リクロロシラン)の場合、該成長速度が2.0μm/m
in以上、さらに高速度で流下させると5.0μm/m
in以上の高速成膜を可能にした半導体基板の製造方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, particularly B
The present invention relates to a method for manufacturing a single crystal silicon substrate for semiconductor integrated circuits such as for ip-IC and BiCMOS, when epitaxially growing on a silicon single crystal substrate having a specific crystal axis,
In the case of SiHCl 3 (trichlorosilane), the growth rate is 2.0 μm by keeping the specific growth temperature by using SiHCl 3 or SiCl 4 as a raw material gas and letting the carrier gas flow at a much higher speed and laminar flow. / M
5.0 μm / m when flowing down at a speed higher than in
The present invention relates to a method for manufacturing a semiconductor substrate that enables high-speed film formation of in or more.

【0002】[0002]

【従来の技術】Bip−IC、BiCMOS用等半導体
集積回路を製造する際、始発半導体基板として<100
>0±1°の結晶軸を持つシリコン単結晶基板が多用さ
れている。この半導体基板は、少なくとも一方の表面が
鏡面に仕上げられたウェーハで、埋め込み拡散層形成の
ために、パターニングを行った後ドーパント(P型:
B、N型:Sb,As,P)を任意の部分に拡散し、そ
の後気相成長法によってエピタキシャル成長される。
2. Description of the Related Art When manufacturing a semiconductor integrated circuit for Bip-IC, BiCMOS, etc., <100 is used as a starting semiconductor substrate.
A silicon single crystal substrate having a crystal axis of> 0 ± 1 ° is often used. This semiconductor substrate is a wafer in which at least one surface is mirror-finished, and a dopant (P type:
B, N type: Sb, As, P) is diffused in an arbitrary portion, and then epitaxially grown by a vapor phase growth method.

【0003】従来、埋め込み層が形成された<100>
0±1°の結晶軸を持つシリコン単結晶ウェーハにエピ
タキシャル成長する場合、気相成長炉はシリンダー炉ま
たはパンケーキ炉が用いられている。この時、注意しな
ければならないのが、エピタキシャル成長後のパターン
ディストーションである。一般にパターンディストーシ
ョンは、成長圧力、成長温度、成長速度、Si原材料ガ
スにより影響を受けると言われている。
Conventionally, <100> in which a buried layer is formed
When epitaxially growing a silicon single crystal wafer having a crystal axis of 0 ± 1 °, a cylinder furnace or a pancake furnace is used as a vapor phase growth furnace. At this time, it is necessary to pay attention to the pattern distortion after the epitaxial growth. Generally, pattern distortion is said to be affected by growth pressure, growth temperature, growth rate, and Si raw material gas.

【0004】[0004]

【発明が解決しようとする課題】通常、SiCl4(四
塩化けい素)を原材料ガスとして用いる場合、常圧下の
反応で成長温度が1180〜1200℃、成長速度が1
μm/min以下の条件で製造される。
Generally, when SiCl 4 (silicon tetrachloride) is used as a raw material gas, the reaction is carried out under normal pressure at a growth temperature of 1180 to 1200 ° C. and a growth rate of 1 ° C.
It is manufactured under the condition of μm / min or less.

【0005】トリクロロシランを原材料ガスとして用い
る場合、これも常圧下で1180℃以上、成長速度が1
μm/min以下の条件で製造できるが、石英製の反応
容器壁内部にシリコンおよびシリコンの酸化物が堆積し
(wall Depo)、石英を失透させ温度コントロ
ールができなくなる等の不具合が生じるため、実用的で
はない。
When trichlorosilane is used as a raw material gas, it also has a growth rate of 1180 ° C. or higher under normal pressure.
Although it can be produced under the condition of μm / min or less, silicon and oxides of silicon are deposited inside the wall of the quartz reaction vessel (wall Depo), which causes a problem such as devitrification of quartz and uncontrollable temperature control. Not practical.

【0006】また、ジクロロシランまたはモノシランを
原材料ガスとして用いる場合、常圧または減圧下で10
50℃〜1150℃の反応温度で、成長速度が1μm/
min以下の条件で製造している。
Further, when dichlorosilane or monosilane is used as a raw material gas, it is used under normal pressure or reduced pressure at 10
At a reaction temperature of 50 ° C to 1150 ° C, the growth rate is 1 μm /
It is manufactured under the condition of min or less.

【0007】しかし、これらの条件はいずれも成長速度
が1μm/min以下であるため、生産性が悪いという
問題がある。さらに、SiCl4やトリクロロシランの
ような水素還元反応の場合、反応温度が非常に高温とな
り、Slipと呼ばれる結晶欠陥や埋め込み層からの不
純物のオートドープが大きくなり、エピタキシャル膜の
比抵抗コントロール(反転層の形成も含む)が難しいと
いう不具合が生じる。
However, since the growth rate is 1 μm / min or less under any of these conditions, there is a problem that productivity is poor. Furthermore, in the case of hydrogen reduction reaction such as SiCl 4 or trichlorosilane, the reaction temperature becomes extremely high, crystal defects called Slip and autodoping of impurities from the buried layer become large, and the resistivity control (reversal) of the epitaxial film is increased. It is difficult to form (including formation of layers).

【0008】この発明は、結晶軸<100>0±1°の
シリコン単結晶基板にエピタキシャル成長する製造方法
における上述の問題点に鑑み、水素還元反応時のオート
ドープを低減するとともにパターンディストーションを
発生させることなく、1μm/min以上の成長速度が
得られる半導体基板の製造方法の提供を目的としてい
る。
In view of the above problems in the manufacturing method of epitaxially growing a silicon single crystal substrate having a crystal axis of <100> 0 ± 1 °, the present invention reduces autodoping during hydrogen reduction reaction and causes pattern distortion. It is an object of the present invention to provide a method for manufacturing a semiconductor substrate, which can achieve a growth rate of 1 μm / min or more without any trouble.

【0009】[0009]

【課題を解決するための手段】発明者らは、結晶軸<1
00>0±1°のシリコン単結晶基板へのエピタキシャ
ル成長速度の高速化を目的に、反応炉内及び基板近傍の
ガス流れについて種々検討したところ、従来、ある反応
炉において、シリコン単結晶基板(5インチ)1枚当た
りのH2ガス流量は数l〜15l/min程度であり、
しかも、ガス流れは乱流でガスの濃度差が発生している
ことに着目し、さらに検討した結果、シリコン単結晶基
板(5インチ)1枚当たりのH2ガス流量を30〜12
0l/minと高速流とし、また、ガス流れを1方向
流、すなわち、基板表面に沿って一方向に流れる層流と
することにより、パターンディストーションを大きく改
善できることを知見した。
The inventors have found that the crystal axis <1
For the purpose of accelerating the epitaxial growth rate on a silicon single crystal substrate of 00> 0 ± 1 °, various studies were conducted on the gas flow in the reaction furnace and in the vicinity of the substrate. (Inch) The flow rate of H 2 gas per sheet is several l to 15 l / min,
Moreover, as a result of further studying that the gas flow is a turbulent flow and a gas concentration difference is generated, as a result, the H 2 gas flow rate per silicon single crystal substrate (5 inches) is 30 to 12
It was found that the pattern distortion can be greatly improved by setting the flow rate as high as 0 l / min and by using the gas flow in one direction, that is, a laminar flow that flows in one direction along the substrate surface.

【0010】発明者らは、さらに基板近傍のガス流れに
ついて種々検討したところ、キャリアガス流れを層流で
高速流とすることにより、原料ガスのよどみ層はほとん
ど発生せず、局所的なエッチング、デポがなく、常にフ
レッシュなガスが供給されるため反応が安定し、高速化
すること、すなわち、パターンディストーションへの影
響度に関与する因子の中で、ウェーハ1枚当たりの水素
ガス流量及びガス流れは非常に大きな影響を及ぼす因子
であることを知見した。
The inventors further conducted various studies on the gas flow in the vicinity of the substrate. As a result of the laminar flow of the carrier gas being a high-speed flow, a stagnation layer of the source gas was hardly generated, and local etching, Since there is no deposit and fresh gas is always supplied, the reaction is stable and faster, that is, the hydrogen gas flow rate and gas flow per wafer are among the factors that affect the degree of influence on pattern distortion. Was found to be a very significant factor.

【0011】そこで、発明者らは、上記知見に基づく層
流で高速流のキャリアガス流れと反応温度との関係につ
いても検討したところ、Siソースとしてトリクロロシ
ランの場合、反応温度が1150℃±10℃で、処理炉
内のガス流速が2m/min以上、あるいはガス置換回
数が3回/min以上となる高速流かつ層流のキャリア
ガスを流下させると、従来に比べて低温でかつ成長速度
も2〜10倍というこれまでの常識を越える反応が可能
となることを知見しこの発明を完成した。
Therefore, the present inventors also examined the relationship between the laminar flow and the high-speed carrier gas flow and the reaction temperature based on the above findings. When trichlorosilane was used as the Si source, the reaction temperature was 1150 ° C. ± 10. When a high-speed and laminar carrier gas having a gas flow rate of 2 m / min or more in the processing furnace or a gas replacement frequency of 3 times / min or more is flowed down at ℃, the temperature is lower than the conventional one and the growth rate is also higher. The inventors have completed the present invention by discovering that a reaction that exceeds the conventional wisdom of 2 to 10 times is possible.

【0012】すなわち、この発明は、不純物の埋め込み
拡散がなされた微細パターンを持つ結晶軸<100>0
±1°のシリコン単結晶基板にエピタキシャル成長する
に際し、SiHCl3(トリクロロシラン)を原材料ガ
スとして、処理炉内のガス流速が2m/min以上、あ
るいはガス置換回数が3回/min以上の高速流かつ層
流のキャリアガスを流下させ、反応温度を1150℃±
10℃に保持することを特徴とする半導体基板の製造方
法である。
That is, according to the present invention, the crystal axis <100> 0 having a fine pattern in which impurities are embedded and diffused.
During epitaxial growth on a silicon single crystal substrate of ± 1 °, SiHCl 3 (trichlorosilane) was used as a raw material gas and the gas flow rate in the processing furnace was 2 m / min or more, or the gas replacement frequency was 3 times / min or more. Laminar carrier gas is flown down, and the reaction temperature is 1150 ° C ±
It is a method of manufacturing a semiconductor substrate, which is characterized by holding at 10 ° C.

【0013】また、この発明は、不純物の埋め込み拡散
がなされた微細パターンを持つ結晶軸<100>0±1
°のシリコン単結晶基板にエピタキシャル成長するに際
し、SiCl4(四塩化けい素)を原材料ガスとして、
処理炉内のガス流速が2m/min以上、あるいはガス
置換回数が3回/min以上の高速流かつ層流のキャリ
アガスを流下させ、反応温度を1150℃〜1190℃
に保持することを特徴とする半導体基板の製造方法であ
る。
Further, according to the present invention, the crystal axis <100> 0 ± 1 having a fine pattern in which impurities are embedded and diffused.
At the time of epitaxial growth on a silicon single crystal substrate of ° C, SiCl 4 (silicon tetrachloride) was used as a source gas.
A high-speed and laminar carrier gas having a gas flow rate of 2 m / min or more in the processing furnace or a gas replacement frequency of 3 times / min or more is flowed down, and the reaction temperature is 1150 ° C to 1190 ° C.
The method for manufacturing a semiconductor substrate is characterized in that

【0014】この発明において、エピタキシャル成長前
の前処理は、高温H2雰囲気下でのベーキング、高温H2
及び少量のHClガス雰囲気下でのエッチング処理のい
ずれを採用してもよい。また、気相成長装置は、キャリ
アガス流量を基板表面に沿って一方向に流れる層流で所
定の高速流とすることができれば、縦型、ドーム型、チ
ューブ型等公知のいずれの構成からなる装置を採用する
こともできる。
In the present invention, the pretreatment before the epitaxial growth is performed by baking in a high temperature H 2 atmosphere and high temperature H 2
And an etching treatment under a small amount of HCl gas atmosphere may be adopted. Further, the vapor phase growth apparatus has any known structure such as a vertical type, a dome type, or a tube type as long as the carrier gas flow rate can be a predetermined high-speed flow with a laminar flow flowing in one direction along the substrate surface. A device can also be employed.

【0015】この発明において、反応炉内のキャリアガ
ス流速を限定するのは、層流で高速流とすることによ
り、原料ガスのよどみ層を発生せず、局所的なエッチン
グ、デポをなくし、反応の安定と高速化を図るためであ
るが、かかる効果を得るためには、少なくとも2m/m
in以上の流速が必要であり、速い流れであるほど効果
は高いが、流量を増やすと反応容器内の背圧が上昇して
最終的には破壊することになるため、反応炉の構成や使
用する流量制御用マスフローコントローラーの能力に応
じて上限を選定すると良く、実用的には2〜16m/m
inである。
In the present invention, the carrier gas flow rate in the reaction furnace is limited by the laminar flow at a high speed, so that a stagnation layer of the source gas is not generated, local etching and deposition are eliminated, and the reaction To stabilize and increase the speed, but to obtain such an effect, at least 2 m / m
A flow rate of more than in is required, and the higher the flow rate, the higher the effect. However, increasing the flow rate increases the back pressure in the reaction vessel and eventually destroys it. It is recommended to select the upper limit according to the capacity of the mass flow controller for flow rate control, which is practically 2 to 16 m / m.
in.

【0016】また、この発明において、反応炉内のキャ
リアガス流速の規定に代えてガス置換回数で規定するこ
ともでき、同様の効果を得るにはガス置換回数が少なく
とも3回/min以上のガス流量が必要であり、置換回
数が多いほうが好ましいが、上述と同様の理由により、
実用的には3〜26回/minである。
Further, in the present invention, the carrier gas flow rate in the reaction furnace may be replaced by the gas replacement frequency, and in order to obtain the same effect, the gas replacement frequency is at least 3 times / min or more. A flow rate is required and it is preferable that the number of replacements is large, but for the same reason as above,
Practically, it is 3 to 26 times / min.

【0017】この発明において、Siソースとしてトリ
クロロシランを用いる場合、反応温度を1150℃±1
0℃とするのは、キャリアガス流れを層流で高速流とし
ても、該反応温度域を外れると2.0〜5.0μm/m
inあるいは5.0μm/min以上の成長速度が得ら
れないためである。また、SiソースとしてSiCl4
を用いる場合も、同様の理由で反応温度が1150℃〜
1190℃域を外れると1.0〜3.0μm/minあ
るいは3.0μm/min以上の成長速度が得られな
い。
In the present invention, when trichlorosilane is used as the Si source, the reaction temperature is 1150 ° C. ± 1.
The temperature of 0 ° C. is 2.0 to 5.0 μm / m when the carrier gas flow is a laminar high-speed flow and is outside the reaction temperature range.
This is because a growth rate of in or 5.0 μm / min or more cannot be obtained. Moreover, SiCl 4 is used as the Si source.
Also when using a reaction temperature of 1150 ℃ ~ for the same reason.
If the temperature is out of the 1190 ° C. range, a growth rate of 1.0 to 3.0 μm / min or 3.0 μm / min or more cannot be obtained.

【0018】[0018]

【作用】この発明は、不純物の埋め込み拡散がなされた
微細パターンを持つ結晶軸<100>0±1°のシリコ
ン単結晶基板にエピタキシャル成長するに際し、原材料
ガスSiHCl3の場合、成長温度を1150℃±10
℃に保持し、SiCl4の場合、成長温度を1150℃
〜1190℃に保持し、従来よりはるかに高速流かつ層
流でキャリアガスを流下させることにより、SiHCl
3の場合、該成長速度が2.0μm/min以上、さら
に高速度で流下させると5.0μm/min以上の高速
成膜を可能にし、従来の2倍以上の成長速度で反応する
ことが可能であるため、生産性の向上が図れ、しかもス
リップやオートドープの少ない高品質の半導体集積回路
用シリコン単結晶基板を提供できる。
According to the present invention, in the case of epitaxial growth on a silicon single crystal substrate having a crystal axis <100> 0 ± 1 ° having a fine pattern in which impurities are embedded and diffused, in the case of a raw material gas SiHCl 3 , the growth temperature is 1150 ° C. ±. 10
℃, keep the growth temperature 1150 ℃ for SiCl 4
By maintaining the carrier gas at ˜1190 ° C. and flowing the carrier gas at a much higher speed and laminar flow than the conventional method, SiHCl
In the case of 3 , the growth rate is 2.0 μm / min or more, and if the film is flowed down at a higher speed, high-speed film formation of 5.0 μm / min or more is possible, and it is possible to react at a growth rate twice or more of the conventional rate. Therefore, it is possible to provide a high-quality silicon single crystal substrate for a semiconductor integrated circuit with improved productivity and less slip and auto-doping.

【0019】[0019]

【実施例】【Example】

実施例1 5インチ径、P型(Boron)、比抵抗5〜10Ωc
mの結晶軸<100>0±1°の基板に、図1Aに示す
ごときパターニングを形成後、不純物としてSb(N
型)を表面濃度1×1018atoms/cc、拡散深さ
が5μmの拡散層を形成した後、エピタキシャル成長を
行った。気相成長装置は、メインH2が大流量で層流と
なるガス流れを持つものを使用し、原材料Siガスとし
てトリクロロシラン、反応温度が1100〜1150
℃、ウェーハ1枚当たりの水素ガス流量が30〜120
l/min、すなわち、流速が2.36m/min〜
9.45m/min、ガス置換回数が3.9回/min
〜15.6回/minの条件でエピタキシャル成長を行
ったところ、成長速度は2.0〜5.0μm/minを
得た。
Example 1 5 inch diameter, P type (Boron), specific resistance 5 to 10 Ωc
After the patterning as shown in FIG. 1A is formed on the substrate having the crystal axis <100> 0 ± 1 ° of m, Sb (N
After forming a diffusion layer having a surface concentration of 1 × 10 18 atoms / cc and a diffusion depth of 5 μm, epitaxial growth was performed. As the vapor phase growth apparatus, one having a gas flow in which main H 2 becomes a laminar flow at a large flow rate is used, trichlorosilane is used as a raw material Si gas, and a reaction temperature is 1100 to 1150.
C, the hydrogen gas flow rate per wafer is 30 to 120
1 / min, that is, a flow velocity of 2.36 m / min
9.45 m / min, gas replacement frequency 3.9 times / min
When epitaxial growth was performed under the condition of ˜15.6 times / min, the growth rate was 2.0 to 5.0 μm / min.

【0020】図1Bと図2A,Bは、ウェーハ1枚当た
りの水素ガス流量を60l/min(ガス流速4.72
m/min、ガス置換回数7.8回/min)に設定
し、20μm厚みにエピタキシャル成長させ、5.0μ
m/minの成長速度を得たときの反応温度が1100
℃、1130℃、1150℃における得られたパターン
を示す拡大(107.5倍)図である。図2Aに示すご
とく、反応温度が1100〜1130℃の範囲で成長し
た全ての条件は、パターンディストーションが悪く、実
用的ではないが、図2Bに示すごとく、パターンディス
トーションは、従来炉の条件(0.5μm/minの成
長速度)で作製したものと同等以上の良好なものであっ
た。また、スリップやオートドープについても、なんら
問題のないレベルであった。
1B and FIGS. 2A and 2B show a hydrogen gas flow rate per wafer of 60 l / min (gas flow rate 4.72).
m / min, gas replacement frequency 7.8 times / min) and epitaxially grown to a thickness of 20 μm.
The reaction temperature is 1100 when the growth rate of m / min is obtained.
It is an expansion (107.5 time) figure which shows the obtained pattern in 1 degreeC, 1130 degreeC, and 1300 degreeC. As shown in FIG. 2A, under all the conditions where the reaction temperature was grown in the range of 1100 to 1130 ° C., the pattern distortion was bad and not practical, but as shown in FIG. 2B, the pattern distortion was the same as that of the conventional furnace (0 It was as good as or better than that produced at a growth rate of 0.5 μm / min). Also, slip and auto-dope were at a level without any problems.

【0021】実施例2 実施例1の気相成長条件において、反応温度を1150
℃とし、得られた2.0μm/min、4.0μm/m
in、4.5μm/min、5.0μm/minの各成
長速度でのパターンを示す拡大(107.5倍)図を図
3A,B、図4A,Bにそれぞれ示す。その結果、11
50℃で反応した全ての条件でパターンディストーショ
ンは、従来炉の条件で作製したものと同等以上の良好な
ものであった。また、スリップやオートドープについて
も、なんら問題のないレベルであった。
Example 2 Under the vapor phase growth conditions of Example 1, the reaction temperature was set to 1150.
℃ and obtained 2.0μm / min, 4.0μm / m
An enlarged (107.5 times) diagram showing patterns at growth rates of in, 4.5 μm / min, and 5.0 μm / min is shown in FIGS. 3A and 3B and FIGS. 4A and 4B, respectively. As a result, 11
The pattern distortion under all conditions reacted at 50 ° C. was as good as or better than that produced under the conventional furnace conditions. Also, slip and auto-dope were at a level without any problems.

【0022】実施例3 実施例1の図1Aに示す不純物拡散を実施したシリコン
単結晶基板に、実施例1のメインH2が大流量で層流と
なる気相成長装置を用い、SiソースとしてSiC
4、反応温度が1100〜1190℃、ウェーハ1枚
当たりの水素ガス流量が30〜120l/min、すな
わち、流速が2.36m/min〜9.45m/mi
n、ガス置換回数が3.9回/min〜15.6回/m
inとなる条件でエピタキシャル成長を行ったところ、
1.0〜3.0μm/minの成長速度が得られた。そ
の結果、反応温度が1100〜1130℃の範囲で成長
した全ての条件は、パターンディストーションが悪く、
実用的ではなかった。しかし、1150℃以上で反応し
た全ての条件でパターンディストーションは、比較例1
の従来炉の条件で作製したものと同等以上の良好なもの
であった。
Example 3 On the silicon single crystal substrate on which the impurity diffusion shown in FIG. 1A of Example 1 was carried out, the vapor phase growth apparatus of Example 1 in which the main H 2 becomes a laminar flow at a large flow rate was used as the Si source. SiC
L 4 , the reaction temperature is 1100 to 1190 ° C., the hydrogen gas flow rate per wafer is 30 to 120 l / min, that is, the flow rate is 2.36 m / min to 9.45 m / mi.
n, the gas replacement frequency is 3.9 times / min to 15.6 times / m
When epitaxial growth was performed under the condition of in,
A growth rate of 1.0 to 3.0 μm / min was obtained. As a result, the pattern distortion was poor under all conditions where the reaction temperature was grown in the range of 1100 to 1130 ° C.
It wasn't practical. However, the pattern distortion was observed in Comparative Example 1 under all conditions where the reaction was performed at 1150 ° C. or higher.
It was as good as or better than the one manufactured under the conventional furnace conditions.

【0023】すなわち、反応温度を1190℃、成長速
度が2.0μm/minとなるように設定し、ウェーハ
1枚当たりの水素ガス流量が30l/min、60l/
min、120l/min、流速が2.36m/mi
n、4.72m/min、9.45m/min、ガス置
換回数が3.9回/min、7.8回/min、15.
6回/minにおける基板のパターンを示す拡大(10
7.5倍)図を図5A,B,Cに示すごとく、パターン
ディストーションは良好なものであり、スリップやオー
トドープについても、なんら問題のないレベルであっ
た。
That is, the reaction temperature is set to 1190 ° C., the growth rate is set to 2.0 μm / min, and the hydrogen gas flow rate per wafer is 30 l / min and 60 l / min.
min, 120 l / min, flow velocity 2.36 m / mi
n, 4.72 m / min, 9.45 m / min, gas replacement frequency 3.9 times / min, 7.8 times / min, 15.
Enlargement showing the pattern of the substrate at 6 times / min (10
(7.5 times) As shown in FIGS. 5A, 5B and 5C, the pattern distortion was good, and there was no problem with slip and autodoping.

【0024】比較例1 5インチ径、P型(Boron)、比抵抗5〜10Ωc
mの結晶軸<100>0±1°の基板に、パターニング
形成後、不純物としてSb(N型)を表面濃度1×10
18atoms/cc、拡散深さが5μmの拡散層を形成
した後、通常のシリンダー炉でウェーハ1枚当たりの水
素ガス流量が15l/min、流速が1.18m/mi
n、ガス置換回数が1.9回/min、反応温度を12
00℃の条件でエピタキシャル成長を行ったところ、
0.26μm/minの成長速度で18μm厚みを得
た。図6A,B、図7A,Bの基板のパターンを示す拡
大(107.5倍)図に明らかなようにパターンディス
トーションは良好なものであり、スリップやオートドー
プについても、なんら問題のないレベルであった。
Comparative Example 1 5 inch diameter, P type (Boron), specific resistance 5 to 10 Ωc
After patterning and forming Sb (N type) as a surface concentration on a substrate having a crystal axis <100> 0 ± 1 ° of m of 1 × 10
After forming a diffusion layer of 18 atoms / cc and a diffusion depth of 5 μm, the flow rate of hydrogen gas per wafer is 15 l / min and the flow rate is 1.18 m / mi in a normal cylinder furnace.
n, the gas replacement frequency is 1.9 times / min, and the reaction temperature is 12
When epitaxial growth was performed under the condition of 00 ° C,
A 18 μm thickness was obtained at a growth rate of 0.26 μm / min. As is apparent from the enlarged (107.5 times) diagrams showing the patterns of the substrates of FIGS. 6A, B, and 7A, B, the pattern distortion is good, and there is no problem with slip and autodoping. there were.

【0025】[0025]

【発明の効果】この発明は、不純物の埋め込み拡散がな
された微細パターンを持つ結晶軸<100>0±1°の
シリコン単結晶基板にエピタキシャル成長するに際し、
原材料ガスSiHCl3の場合、成長温度を1150℃
±10℃に保持し、SiCl4の場合、成長温度を11
50℃〜1190℃に保持し、従来よりはるかに高速流
かつ層流でキャリアガスを流下させることにより、Si
HCl3の場合、該成長速度が2.0μm/min以
上、さらに高速度で流下させると5.0μm/min以
上の高速成膜を可能にし、従来の2倍以上の成長速度で
反応することが可能であるため、生産性の向上が図れ、
しかもスリップやオートドープの少ない高品質の半導体
集積回路用シリコン単結晶基板を提供できる。
According to the present invention, when epitaxially growing on a silicon single crystal substrate having a crystal axis <100> 0 ± 1 ° having a fine pattern in which impurities are embedded and diffused,
When the raw material gas is SiHCl 3 , the growth temperature is 1150 ° C.
Keeping the temperature at ± 10 ° C., the growth temperature is 11 in the case of SiCl 4.
By holding the carrier gas at 50 ° C to 1190 ° C and flowing the carrier gas in a laminar flow at a much higher speed than in the conventional case, Si
In the case of HCl 3 , if the growth rate is 2.0 μm / min or more, and if it is made to flow at a higher rate, high-speed film formation of 5.0 μm / min or more is possible, and the reaction rate is twice as fast as that of the conventional method. Because it is possible, productivity can be improved,
Moreover, it is possible to provide a high-quality silicon single crystal substrate for semiconductor integrated circuits with less slip and auto-doping.

【図面の簡単な説明】[Brief description of drawings]

【図1】Aは実施例におけるエピタキシャル成長前のパ
ターニングを形成した基板の拡大(107.5倍)図で
あり、Bは実施例1の反応温度が1100℃における基
板の拡大(107.5倍)図である。
FIG. 1A is an enlarged view (107.5 times) of a substrate formed with patterning before epitaxial growth in Example, and B is an enlarged view (107.5 times) of the substrate in Example 1 at a reaction temperature of 1100 ° C. It is a figure.

【図2】Aは実施例1の反応温度が1130℃における
基板の拡大(107.5倍)図、Bは実施例1の反応温
度が1150℃における基板の拡大(107.5倍)写
真図である。
2A is an enlarged view (107.5 times) of the substrate when the reaction temperature of Example 1 is 1130 ° C., and FIG. 2B is a photographed view of the substrate when the reaction temperature of Example 1 is 1150 ° C. (107.5 times). Is.

【図3】Aは実施例2の成長速度が2.0μm/min
における基板の拡大(107.5倍)図、Bは成長速度
が4.0μm/minにおける基板の拡大(107.5
倍)図である。
FIG. 3A shows a growth rate of Example 2 of 2.0 μm / min.
FIG. 9B is an enlarged view (107.5 times) of the substrate in FIG.
It is a figure.

【図4】Aは実施例2の成長速度が4.5μm/min
における基板の拡大(107.5倍)図、Bは成長速度
が5.0μm/minにおける基板の拡大(107.5
倍)図である。
FIG. 4A shows a growth rate of Example 2 of 4.5 μm / min.
(107.5 times) enlarged view of the substrate at B, and B shows the enlarged substrate (107.5 at a growth rate of 5.0 μm / min).
It is a figure.

【図5】A,B,Cは実施例3のウェーハ1枚当たりの
水素ガス流量が30l/min、60l/min、12
0l/minにおける基板のパターンを示す拡大(10
7.5倍)図である。
5A, 5B, and 5C are hydrogen gas flow rates of 30 l / min, 60 l / min, and 12 per wafer of Example 3.
Enlargement showing the pattern of the substrate at 0 l / min (10
(7.5 times) FIG.

【図6】Aは比較例1におけるエピタキシャル成長前の
パターニングを形成した基板の拡大(107.5倍)写
真図であり、Bは従来のエピタキシャル成長を行った基
板の拡大(107.5倍)写真図である。
FIG. 6A is an enlarged (107.5 times) photograph of a substrate on which patterning is performed before epitaxial growth in Comparative Example 1, and B is an enlarged (107.5 times) photograph of a substrate on which conventional epitaxial growth is performed. Is.

【図7】Aは比較例1におけるエピタキシャル成長前の
パターニングを形成した基板の図6とは角度を変えて見
た拡大(107.5倍)図であり、Bは従来のエピタキ
シャル成長を行った基板の図6とは角度を変えて見た拡
大(107.5倍)図である。
FIG. 7A is an enlarged (107.5 times) view of the substrate on which patterning before epitaxial growth is formed in Comparative Example 1 at a different angle from FIG. 6, and B is a conventional epitaxially grown substrate. FIG. 6 is an enlarged view (107.5 times) viewed from a different angle.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/20 H01L 21/20 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H01L 21/20 H01L 21/20

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 不純物の埋め込み拡散がなされた微細パ
ターンを持つ結晶軸<100>0±1°のシリコン単結
晶基板にエピタキシャル成長するに際し、SiHCl3
(トリクロロシラン)を原材料ガスとして、処理炉内の
ガス流速が2m/min以上、あるいはガス置換回数が
3回/min以上の高速流かつ層流のキャリアガスを流
下させ、反応温度を1150℃±10℃に保持すること
を特徴とする半導体基板の製造方法。
1. SiHCl 3 is used for epitaxial growth on a silicon single crystal substrate having a crystal axis <100> 0 ± 1 ° having a fine pattern in which impurities are embedded and diffused.
Using (trichlorosilane) as a raw material gas, a high-speed and laminar carrier gas with a gas flow rate of 2 m / min or more in the processing furnace or a gas replacement frequency of 3 times / min or more is allowed to flow down, and the reaction temperature is 1150 ° C ± A method of manufacturing a semiconductor substrate, characterized by holding at 10 ° C.
【請求項2】 不純物の埋め込み拡散がなされた微細パ
ターンを持つ結晶軸<100>0±1°のシリコン単結
晶基板にエピタキシャル成長するに際し、SiCl
4(四塩化けい素)を原材料ガスとして、処理炉内のガ
ス流速が2m/min以上、あるいはガス置換回数が3
回/min以上の高速流かつ層流のキャリアガスを流下
させ、反応温度を1150℃〜1190℃に保持するこ
とを特徴とする半導体基板の製造方法。
2. SiCl is epitaxially grown on a silicon single crystal substrate having a crystal axis <100> 0 ± 1 ° having a fine pattern in which impurities are embedded and diffused.
Using 4 (silicon tetrachloride) as the raw material gas, the gas flow rate in the processing furnace is 2 m / min or more, or the gas replacement frequency is 3
A method for manufacturing a semiconductor substrate, characterized in that a high-speed and laminar carrier gas at a flow rate of at least 1 turn / min is flowed down, and the reaction temperature is maintained at 1150 ° C to 1190 ° C.
JP6190295A 1995-02-24 1995-02-24 Manufacture of semiconductor substrate Pending JPH08236458A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6190295A JPH08236458A (en) 1995-02-24 1995-02-24 Manufacture of semiconductor substrate

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Application Number Priority Date Filing Date Title
JP6190295A JPH08236458A (en) 1995-02-24 1995-02-24 Manufacture of semiconductor substrate

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Publication Number Publication Date
JPH08236458A true JPH08236458A (en) 1996-09-13

Family

ID=13184551

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Country Link
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1123423A1 (en) * 1998-09-16 2001-08-16 Torrex Equipment Corporation High rate silicon deposition method at low pressures
WO2004020705A1 (en) * 2002-08-30 2004-03-11 Sumitomo Mitsubishi Silicon Corporation Epitaxial wafer and its manufacturing method
WO2012101968A1 (en) * 2011-01-26 2012-08-02 信越半導体株式会社 Method for manufacturing silicon epitaxial wafer
JP2015527743A (en) * 2012-09-05 2015-09-17 無錫華潤上華半導体有限公司 Method for manufacturing a plurality of trench structures
JP2017117974A (en) * 2015-12-25 2017-06-29 信越半導体株式会社 Epitaxial wafer and method of manufacturing epitaxial wafer
US10858758B2 (en) 2017-04-04 2020-12-08 Mitsubishi Electric Corporation Manufacturing method for silicon carbide epitaxial wafer and manufacturing method for silicon carbide semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1123423A1 (en) * 1998-09-16 2001-08-16 Torrex Equipment Corporation High rate silicon deposition method at low pressures
JP2002525841A (en) * 1998-09-16 2002-08-13 トーレックス・イクイップメント・コーポレーション High-speed silicon deposition at low pressure
EP1123423A4 (en) * 1998-09-16 2005-05-11 Torrex Equipment Corp High rate silicon deposition method at low pressures
WO2004020705A1 (en) * 2002-08-30 2004-03-11 Sumitomo Mitsubishi Silicon Corporation Epitaxial wafer and its manufacturing method
WO2012101968A1 (en) * 2011-01-26 2012-08-02 信越半導体株式会社 Method for manufacturing silicon epitaxial wafer
JP2012156303A (en) * 2011-01-26 2012-08-16 Shin Etsu Handotai Co Ltd Manufacturing method for silicon epitaxial wafer
JP2015527743A (en) * 2012-09-05 2015-09-17 無錫華潤上華半導体有限公司 Method for manufacturing a plurality of trench structures
JP2017117974A (en) * 2015-12-25 2017-06-29 信越半導体株式会社 Epitaxial wafer and method of manufacturing epitaxial wafer
US10858758B2 (en) 2017-04-04 2020-12-08 Mitsubishi Electric Corporation Manufacturing method for silicon carbide epitaxial wafer and manufacturing method for silicon carbide semiconductor device

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