JP2012124486A5 - - Google Patents
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- Publication number
- JP2012124486A5 JP2012124486A5 JP2011266379A JP2011266379A JP2012124486A5 JP 2012124486 A5 JP2012124486 A5 JP 2012124486A5 JP 2011266379 A JP2011266379 A JP 2011266379A JP 2011266379 A JP2011266379 A JP 2011266379A JP 2012124486 A5 JP2012124486 A5 JP 2012124486A5
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- passivation layer
- device package
- package
- laminate sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims 34
- 239000010410 layer Substances 0.000 claims 15
- 238000002161 passivation Methods 0.000 claims 15
- 239000002184 metal Substances 0.000 claims 9
- 239000000758 substrate Substances 0.000 claims 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 239000012790 adhesive layer Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 239000003989 dielectric material Substances 0.000 claims 1
- 239000007788 liquid Substances 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 238000000465 moulding Methods 0.000 claims 1
- 230000003287 optical effect Effects 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 239000007921 spray Substances 0.000 claims 1
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/962,761 | 2010-12-08 | ||
| US12/962,761 US8310040B2 (en) | 2010-12-08 | 2010-12-08 | Semiconductor device package having high breakdown voltage and low parasitic inductance and method of manufacturing thereof |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2012124486A JP2012124486A (ja) | 2012-06-28 |
| JP2012124486A5 true JP2012124486A5 (OSRAM) | 2015-01-22 |
| JP5926547B2 JP5926547B2 (ja) | 2016-05-25 |
Family
ID=45002829
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011266379A Active JP5926547B2 (ja) | 2010-12-08 | 2011-12-06 | 半導体デバイスパッケージ |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US8310040B2 (OSRAM) |
| EP (1) | EP2463901B1 (OSRAM) |
| JP (1) | JP5926547B2 (OSRAM) |
| KR (1) | KR101944477B1 (OSRAM) |
| CN (1) | CN102543946B (OSRAM) |
| PH (1) | PH12011000403A1 (OSRAM) |
| SG (1) | SG182076A1 (OSRAM) |
| TW (1) | TWI544590B (OSRAM) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8431438B2 (en) * | 2010-04-06 | 2013-04-30 | Intel Corporation | Forming in-situ micro-feature structures with coreless packages |
| US9209151B2 (en) | 2013-09-26 | 2015-12-08 | General Electric Company | Embedded semiconductor device package and method of manufacturing thereof |
| US9806051B2 (en) | 2014-03-04 | 2017-10-31 | General Electric Company | Ultra-thin embedded semiconductor device package and method of manufacturing thereof |
| WO2015174993A1 (en) * | 2014-05-15 | 2015-11-19 | Intel Corporation | Molded composite enclosure for integrated circuit assembly |
| SG11201609064XA (en) * | 2014-05-29 | 2016-12-29 | Az Electronic Materials Luxembourg Sarl | Composition for gap formation, and semiconductor device comprising gaps formed using the composition, and method for producing semiconductor device using the composition |
| EP3065164A1 (en) * | 2015-03-04 | 2016-09-07 | ABB Technology AG | Power semiconductor arrangement and method of generating a power semiconductor arrangement |
| CN112740425A (zh) * | 2018-07-13 | 2021-04-30 | 阵列光子学公司 | 用于大型背接触太阳能电池的双深度通孔器件和工艺 |
| DE102020135088A1 (de) * | 2020-03-27 | 2021-09-30 | Samsung Electronics Co., Ltd. | Halbleitervorrichtung |
| CN113517205A (zh) * | 2020-04-27 | 2021-10-19 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
| US11699663B2 (en) | 2020-04-27 | 2023-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Passivation scheme design for wafer singulation |
| CN115939222B (zh) * | 2022-11-24 | 2025-10-17 | 湖南三安半导体有限责任公司 | 半导体器件及其制备方法 |
| CN116936592A (zh) * | 2023-07-24 | 2023-10-24 | 华天科技（昆山）电子有限公司 | 一种高可靠性的cis芯片封装结构及方法 |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4198444A (en) * | 1975-08-04 | 1980-04-15 | General Electric Company | Method for providing substantially hermetic sealing means for electronic components |
| US4249299A (en) * | 1979-03-05 | 1981-02-10 | Hughes Aircraft Company | Edge-around leads for backside connections to silicon circuit die |
| US5161093A (en) | 1990-07-02 | 1992-11-03 | General Electric Company | Multiple lamination high density interconnect process and structure employing a variable crosslinking adhesive |
| JP3453390B2 (ja) * | 1996-10-08 | 2003-10-06 | 日立化成工業株式会社 | 半導体装置、半導体チップ搭載用基板及びその製造法 |
| EP0926729A3 (en) * | 1997-12-10 | 1999-12-08 | Mitsubishi Gas Chemical Company, Inc. | Semiconductor plastic package and process for the production thereof |
| US6239980B1 (en) | 1998-08-31 | 2001-05-29 | General Electric Company | Multimodule interconnect structure and process |
| US6306680B1 (en) | 1999-02-22 | 2001-10-23 | General Electric Company | Power overlay chip scale packages for discrete power devices |
| JP3602000B2 (ja) * | 1999-04-26 | 2004-12-15 | 沖電気工業株式会社 | 半導体装置および半導体モジュール |
| US6232151B1 (en) | 1999-11-01 | 2001-05-15 | General Electric Company | Power electronic module packaging |
| JP4454814B2 (ja) * | 2000-08-29 | 2010-04-21 | Ｎｅｃエレクトロニクス株式会社 | 樹脂封止型半導体装置及びその製造方法 |
| US7633765B1 (en) * | 2004-03-23 | 2009-12-15 | Amkor Technology, Inc. | Semiconductor package including a top-surface metal layer for implementing circuit features |
| US7262444B2 (en) | 2005-08-17 | 2007-08-28 | General Electric Company | Power semiconductor packaging method and structure |
| JP5033682B2 (ja) * | 2008-03-12 | 2012-09-26 | 株式会社テラミクロス | 半導体素子およびその製造方法並びに半導体装置およびその製造方法 |
| US8963314B2 (en) * | 2008-06-26 | 2015-02-24 | Nxp B.V. | Packaged semiconductor product and method for manufacture thereof |
| TW201101547A (en) * | 2009-06-23 | 2011-01-01 | Univ Kun Shan | Packaging structure of light emitting diode |
-
2010
- 2010-12-08 US US12/962,761 patent/US8310040B2/en active Active
-
2011
- 2011-11-28 EP EP11190875.2A patent/EP2463901B1/en active Active
- 2011-11-30 TW TW100144032A patent/TWI544590B/zh active
- 2011-12-02 PH PH1/2011/000403A patent/PH12011000403A1/en unknown
- 2011-12-06 JP JP2011266379A patent/JP5926547B2/ja active Active
- 2011-12-07 SG SG2011090644A patent/SG182076A1/en unknown
- 2011-12-08 KR KR1020110131042A patent/KR101944477B1/ko active Active
- 2011-12-08 CN CN201110427046.8A patent/CN102543946B/zh active Active
-
2012
- 2012-09-07 US US13/606,186 patent/US8586421B2/en active Active
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